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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_2bb2e10400507f879251f0324a0a8c7c.html">component</a></li> </ul>
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<div class="title">qspi.h</div> </div>
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<div class="contents">
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<a href="component_2qspi_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_QSPI_COMPONENT_</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_QSPI_COMPONENT_</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========================================================================== */</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="comment">/* ========================================================================== */</span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span>  </div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define QSPI_U2008</span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REV_QSPI 0x163</span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span>  </div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="comment">/* -------- QSPI_CTRLA : (QSPI Offset: 0x00) (R/W 32) Control A -------- */</span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLA__Type.html"> 44</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00046"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLA__Type.html#aaaf46f72299c34d5891124f614041b1d"> 46</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLA__Type.html#aaaf46f72299c34d5891124f614041b1d">SWRST</a>:1; </div>
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<div class="line"><a name="l00047"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLA__Type.html#ae872a6aac9d29d5685228a3adfc8d04c"> 47</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLA__Type.html#ae872a6aac9d29d5685228a3adfc8d04c">ENABLE</a>:1; </div>
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<div class="line"><a name="l00048"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLA__Type.html#a98968c9c93ea4ee6a4391acb0a0ea77e"> 48</a></span>  uint32_t :22; </div>
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<div class="line"><a name="l00049"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLA__Type.html#ae7ec0782952fbc3348b26e0560f08845"> 49</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLA__Type.html#ae7ec0782952fbc3348b26e0560f08845">LASTXFER</a>:1; </div>
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<div class="line"><a name="l00050"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLA__Type.html#a1630f7711b2489c9ae65bc9a06e315ca"> 50</a></span>  uint32_t :7; </div>
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<div class="line"><a name="l00051"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLA__Type.html#abe9e047d3e7c7bbecdeee091b4af5121"> 51</a></span>  } bit; </div>
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<div class="line"><a name="l00052"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLA__Type.html#ab372145e424a0b9f1642f60db196a22e"> 52</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLA__Type.html#ab372145e424a0b9f1642f60db196a22e">reg</a>; </div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> } <a class="code" href="unionQSPI__CTRLA__Type.html">QSPI_CTRLA_Type</a>;</div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span>  </div>
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<div class="line"><a name="l00056"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a3c85ecdbf2e9a83baa5c02c477e2d219"> 56</a></span> <span class="preprocessor">#define QSPI_CTRLA_OFFSET 0x00 </span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a07465827fd18264d444500bdb55286ce"> 57</a></span> <span class="preprocessor">#define QSPI_CTRLA_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ac61b8c6799b93af4b19eb1cc8c1060ad"> 59</a></span> <span class="preprocessor">#define QSPI_CTRLA_SWRST_Pos 0 </span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor">#define QSPI_CTRLA_SWRST (_U_(0x1) << QSPI_CTRLA_SWRST_Pos)</span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a102905a5d5179136df4a67e14b6694b1"> 61</a></span> <span class="preprocessor">#define QSPI_CTRLA_ENABLE_Pos 1 </span></div>
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<div class="line"><a name="l00062"></a><span class="lineno"> 62</span> <span class="preprocessor">#define QSPI_CTRLA_ENABLE (_U_(0x1) << QSPI_CTRLA_ENABLE_Pos)</span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a33e902d88b6c5b91eeacc0019d6ae36f"> 63</a></span> <span class="preprocessor">#define QSPI_CTRLA_LASTXFER_Pos 24 </span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="preprocessor">#define QSPI_CTRLA_LASTXFER (_U_(0x1) << QSPI_CTRLA_LASTXFER_Pos)</span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ac433c9f1f4db34c9891f589daf7d3f8b"> 65</a></span> <span class="preprocessor">#define QSPI_CTRLA_MASK _U_(0x01000003) </span></div>
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<div class="line"><a name="l00067"></a><span class="lineno"> 67</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_CTRLB : (QSPI Offset: 0x04) (R/W 32) Control B -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00068"></a><span class="lineno"> 68</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html"> 69</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00070"></a><span class="lineno"> 70</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html#a40b9f8126928b0a8cc5daa6402d10de8"> 71</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLB__Type.html#a40b9f8126928b0a8cc5daa6402d10de8">MODE</a>:1; </div>
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<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html#a35329ec65e15a45e4024ff0a98e67264"> 72</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLB__Type.html#a35329ec65e15a45e4024ff0a98e67264">LOOPEN</a>:1; </div>
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<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html#a6822f70c8971f01fc5f43423df00728d"> 73</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLB__Type.html#a6822f70c8971f01fc5f43423df00728d">WDRBT</a>:1; </div>
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<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html#a9e1fb6cb01d99e5e2926afd364ae7622"> 74</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLB__Type.html#a9e1fb6cb01d99e5e2926afd364ae7622">SMEMREG</a>:1; </div>
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<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html#a2f38f8719f25fec2aded949490118061"> 75</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLB__Type.html#a2f38f8719f25fec2aded949490118061">CSMODE</a>:2; </div>
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<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html#acc04a7d96beb3c2300ba7006f911f4b5"> 76</a></span>  uint32_t :2; </div>
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<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html#a5d4f4af7969a6eff3fe6db9c0eff9601"> 77</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLB__Type.html#a5d4f4af7969a6eff3fe6db9c0eff9601">DATALEN</a>:4; </div>
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<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html#af480aed91b99f33ee6dc1ecdff1c2e69"> 78</a></span>  uint32_t :4; </div>
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<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html#ab2963d007c9dc7aa23eea3209f519a13"> 79</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLB__Type.html#ab2963d007c9dc7aa23eea3209f519a13">DLYBCT</a>:8; </div>
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<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html#aed3b90e61dcef23674f2b060fc6ac7a0"> 80</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLB__Type.html#aed3b90e61dcef23674f2b060fc6ac7a0">DLYCS</a>:8; </div>
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<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html#a9a7f2be0080b314e945d83e3a2f11291"> 81</a></span>  } bit; </div>
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<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="unionQSPI__CTRLB__Type.html#a1d43cda21360188eb04fa9a339aa544c"> 82</a></span>  uint32_t <a class="code" href="unionQSPI__CTRLB__Type.html#a1d43cda21360188eb04fa9a339aa544c">reg</a>; </div>
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<div class="line"><a name="l00083"></a><span class="lineno"> 83</span> } <a class="code" href="unionQSPI__CTRLB__Type.html">QSPI_CTRLB_Type</a>;</div>
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<div class="line"><a name="l00084"></a><span class="lineno"> 84</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"> 85</span>  </div>
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<div class="line"><a name="l00086"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a86b6ab4b906b5c6aefa6c0ebd5d60224"> 86</a></span> <span class="preprocessor">#define QSPI_CTRLB_OFFSET 0x04 </span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a5d56bf1cfa14015b777b28f2fa09fb1e"> 87</a></span> <span class="preprocessor">#define QSPI_CTRLB_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a79698078d30d3cb7fd87b60982a61ad9"> 89</a></span> <span class="preprocessor">#define QSPI_CTRLB_MODE_Pos 0 </span></div>
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<div class="line"><a name="l00090"></a><span class="lineno"> 90</span> <span class="preprocessor">#define QSPI_CTRLB_MODE (_U_(0x1) << QSPI_CTRLB_MODE_Pos)</span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a29d105cadb9ae4f52d8cb4ad48e6dceb"> 91</a></span> <span class="preprocessor">#define QSPI_CTRLB_MODE_SPI_Val _U_(0x0) </span></div>
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<div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a5c39c83034ab25732435350864217682"> 92</a></span> <span class="preprocessor">#define QSPI_CTRLB_MODE_MEMORY_Val _U_(0x1) </span></div>
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<div class="line"><a name="l00093"></a><span class="lineno"> 93</span> <span class="preprocessor">#define QSPI_CTRLB_MODE_SPI (QSPI_CTRLB_MODE_SPI_Val << QSPI_CTRLB_MODE_Pos)</span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor">#define QSPI_CTRLB_MODE_MEMORY (QSPI_CTRLB_MODE_MEMORY_Val << QSPI_CTRLB_MODE_Pos)</span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a14f661b36ae775aa061f37807a3aa7d7"> 95</a></span> <span class="preprocessor">#define QSPI_CTRLB_LOOPEN_Pos 1 </span></div>
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<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="preprocessor">#define QSPI_CTRLB_LOOPEN (_U_(0x1) << QSPI_CTRLB_LOOPEN_Pos)</span></div>
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<div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a45256d78ae287f4e5fcf0a645ba4c539"> 97</a></span> <span class="preprocessor">#define QSPI_CTRLB_WDRBT_Pos 2 </span></div>
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<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#define QSPI_CTRLB_WDRBT (_U_(0x1) << QSPI_CTRLB_WDRBT_Pos)</span></div>
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<div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a15fc44efc7860a14e05bca369ddc4410"> 99</a></span> <span class="preprocessor">#define QSPI_CTRLB_SMEMREG_Pos 3 </span></div>
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<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor">#define QSPI_CTRLB_SMEMREG (_U_(0x1) << QSPI_CTRLB_SMEMREG_Pos)</span></div>
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<div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a0f5424f9db41af3e52e84645a0873d39"> 101</a></span> <span class="preprocessor">#define QSPI_CTRLB_CSMODE_Pos 4 </span></div>
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<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="preprocessor">#define QSPI_CTRLB_CSMODE_Msk (_U_(0x3) << QSPI_CTRLB_CSMODE_Pos)</span></div>
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<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#define QSPI_CTRLB_CSMODE(value) (QSPI_CTRLB_CSMODE_Msk & ((value) << QSPI_CTRLB_CSMODE_Pos))</span></div>
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<div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ad0df34874d30309d93969a5483e3d0e5"> 104</a></span> <span class="preprocessor">#define QSPI_CTRLB_CSMODE_NORELOAD_Val _U_(0x0) </span></div>
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<div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#aea301858cab20b7bd4623300b017ea5f"> 105</a></span> <span class="preprocessor">#define QSPI_CTRLB_CSMODE_LASTXFER_Val _U_(0x1) </span></div>
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<div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a1396d5436eea5bde0a7ebccb2c0c1e58"> 106</a></span> <span class="preprocessor">#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val _U_(0x2) </span></div>
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<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="preprocessor">#define QSPI_CTRLB_CSMODE_NORELOAD (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos)</span></div>
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<div class="line"><a name="l00108"></a><span class="lineno"> 108</span> <span class="preprocessor">#define QSPI_CTRLB_CSMODE_LASTXFER (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos)</span></div>
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<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor">#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos)</span></div>
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<div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#aef938bb6cc8a3c3838d48bc5d6201c6b"> 110</a></span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_Pos 8 </span></div>
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<div class="line"><a name="l00111"></a><span class="lineno"> 111</span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_Msk (_U_(0xF) << QSPI_CTRLB_DATALEN_Pos)</span></div>
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<div class="line"><a name="l00112"></a><span class="lineno"> 112</span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN(value) (QSPI_CTRLB_DATALEN_Msk & ((value) << QSPI_CTRLB_DATALEN_Pos))</span></div>
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<div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ad539db686ab592cc39c9c59378b18edf"> 113</a></span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_8BITS_Val _U_(0x0) </span></div>
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<div class="line"><a name="l00114"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a9aa55203ef83894f7cc3d38187b61373"> 114</a></span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_9BITS_Val _U_(0x1) </span></div>
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<div class="line"><a name="l00115"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a7c65a21275cd48e354f63841fcc0d686"> 115</a></span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_10BITS_Val _U_(0x2) </span></div>
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<div class="line"><a name="l00116"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a0cf11534e7b532b44c2b04d8942cb9f5"> 116</a></span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_11BITS_Val _U_(0x3) </span></div>
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<div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a485e5774639d6c9aec32a24a3a03bef5"> 117</a></span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_12BITS_Val _U_(0x4) </span></div>
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<div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a1993041aeb88652286ed5a9110bc9433"> 118</a></span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_13BITS_Val _U_(0x5) </span></div>
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<div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a014c5a76b1890913ca8ea610c508f0c3"> 119</a></span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_14BITS_Val _U_(0x6) </span></div>
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<div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ab8603426bf9532ca41c619ac1780315f"> 120</a></span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_15BITS_Val _U_(0x7) </span></div>
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<div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#afebcc48c02889a870025933a4775cfb7"> 121</a></span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_16BITS_Val _U_(0x8) </span></div>
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<div class="line"><a name="l00122"></a><span class="lineno"> 122</span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_8BITS (QSPI_CTRLB_DATALEN_8BITS_Val << QSPI_CTRLB_DATALEN_Pos)</span></div>
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<div class="line"><a name="l00123"></a><span class="lineno"> 123</span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_9BITS (QSPI_CTRLB_DATALEN_9BITS_Val << QSPI_CTRLB_DATALEN_Pos)</span></div>
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<div class="line"><a name="l00124"></a><span class="lineno"> 124</span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_10BITS (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos)</span></div>
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<div class="line"><a name="l00125"></a><span class="lineno"> 125</span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_11BITS (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos)</span></div>
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<div class="line"><a name="l00126"></a><span class="lineno"> 126</span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_12BITS (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos)</span></div>
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<div class="line"><a name="l00127"></a><span class="lineno"> 127</span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_13BITS (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos)</span></div>
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<div class="line"><a name="l00128"></a><span class="lineno"> 128</span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_14BITS (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos)</span></div>
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<div class="line"><a name="l00129"></a><span class="lineno"> 129</span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_15BITS (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos)</span></div>
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<div class="line"><a name="l00130"></a><span class="lineno"> 130</span> <span class="preprocessor">#define QSPI_CTRLB_DATALEN_16BITS (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos)</span></div>
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<div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a824a62193678245b9bdb100eabc7ae0b"> 131</a></span> <span class="preprocessor">#define QSPI_CTRLB_DLYBCT_Pos 16 </span></div>
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<div class="line"><a name="l00132"></a><span class="lineno"> 132</span> <span class="preprocessor">#define QSPI_CTRLB_DLYBCT_Msk (_U_(0xFF) << QSPI_CTRLB_DLYBCT_Pos)</span></div>
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<div class="line"><a name="l00133"></a><span class="lineno"> 133</span> <span class="preprocessor">#define QSPI_CTRLB_DLYBCT(value) (QSPI_CTRLB_DLYBCT_Msk & ((value) << QSPI_CTRLB_DLYBCT_Pos))</span></div>
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<div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a85d8473d6936ea535e4af9eb23b519aa"> 134</a></span> <span class="preprocessor">#define QSPI_CTRLB_DLYCS_Pos 24 </span></div>
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<div class="line"><a name="l00135"></a><span class="lineno"> 135</span> <span class="preprocessor">#define QSPI_CTRLB_DLYCS_Msk (_U_(0xFF) << QSPI_CTRLB_DLYCS_Pos)</span></div>
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<div class="line"><a name="l00136"></a><span class="lineno"> 136</span> <span class="preprocessor">#define QSPI_CTRLB_DLYCS(value) (QSPI_CTRLB_DLYCS_Msk & ((value) << QSPI_CTRLB_DLYCS_Pos))</span></div>
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<div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a81d90a83f5b714371ebd7f2192b5a039"> 137</a></span> <span class="preprocessor">#define QSPI_CTRLB_MASK _U_(0xFFFF0F3F) </span></div>
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<div class="line"><a name="l00139"></a><span class="lineno"> 139</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_BAUD : (QSPI Offset: 0x08) (R/W 32) Baud Rate -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00140"></a><span class="lineno"> 140</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="unionQSPI__BAUD__Type.html"> 141</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00142"></a><span class="lineno"> 142</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="unionQSPI__BAUD__Type.html#a1fff893bd4e78a90f2ed61a48132173f"> 143</a></span>  uint32_t <a class="code" href="unionQSPI__BAUD__Type.html#a1fff893bd4e78a90f2ed61a48132173f">CPOL</a>:1; </div>
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<div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="unionQSPI__BAUD__Type.html#a9ce4956564c40a25a9df46c5954e4f6f"> 144</a></span>  uint32_t <a class="code" href="unionQSPI__BAUD__Type.html#a9ce4956564c40a25a9df46c5954e4f6f">CPHA</a>:1; </div>
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<div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="unionQSPI__BAUD__Type.html#a168df26b5e7757f470258578d5df2bd2"> 145</a></span>  uint32_t :6; </div>
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<div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="unionQSPI__BAUD__Type.html#a43b94ea36888e3dc000f4303fc308a84"> 146</a></span>  uint32_t <a class="code" href="unionQSPI__BAUD__Type.html#a43b94ea36888e3dc000f4303fc308a84">BAUD</a>:8; </div>
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<div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="unionQSPI__BAUD__Type.html#ae4ea5e341e2d5d447848963b97fb1f07"> 147</a></span>  uint32_t <a class="code" href="unionQSPI__BAUD__Type.html#ae4ea5e341e2d5d447848963b97fb1f07">DLYBS</a>:8; </div>
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<div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="unionQSPI__BAUD__Type.html#ae48222fd337a4ba6ae42027d2e6b40fc"> 148</a></span>  uint32_t :8; </div>
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<div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="unionQSPI__BAUD__Type.html#a7022ae04d9dfe9b70940ed51b9001c38"> 149</a></span>  } bit; </div>
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<div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="unionQSPI__BAUD__Type.html#a0fc65a43295c1df795b6e794b8c04d80"> 150</a></span>  uint32_t <a class="code" href="unionQSPI__BAUD__Type.html#a0fc65a43295c1df795b6e794b8c04d80">reg</a>; </div>
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<div class="line"><a name="l00151"></a><span class="lineno"> 151</span> } <a class="code" href="unionQSPI__BAUD__Type.html">QSPI_BAUD_Type</a>;</div>
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<div class="line"><a name="l00152"></a><span class="lineno"> 152</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00153"></a><span class="lineno"> 153</span>  </div>
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<div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a91864e8b4413f0c0b3ee02bc1adad69d"> 154</a></span> <span class="preprocessor">#define QSPI_BAUD_OFFSET 0x08 </span></div>
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<div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a3d6ec16e0db1129c9a9ba80cac0a4c9e"> 155</a></span> <span class="preprocessor">#define QSPI_BAUD_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a4ad7ad10245db652c86b15531aa8b17d"> 157</a></span> <span class="preprocessor">#define QSPI_BAUD_CPOL_Pos 0 </span></div>
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<div class="line"><a name="l00158"></a><span class="lineno"> 158</span> <span class="preprocessor">#define QSPI_BAUD_CPOL (_U_(0x1) << QSPI_BAUD_CPOL_Pos)</span></div>
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<div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a84d3cf60569cc949d27b2087ccac6760"> 159</a></span> <span class="preprocessor">#define QSPI_BAUD_CPHA_Pos 1 </span></div>
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<div class="line"><a name="l00160"></a><span class="lineno"> 160</span> <span class="preprocessor">#define QSPI_BAUD_CPHA (_U_(0x1) << QSPI_BAUD_CPHA_Pos)</span></div>
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<div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a58218959c2dabde357d38efcc1b83d76"> 161</a></span> <span class="preprocessor">#define QSPI_BAUD_BAUD_Pos 8 </span></div>
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<div class="line"><a name="l00162"></a><span class="lineno"> 162</span> <span class="preprocessor">#define QSPI_BAUD_BAUD_Msk (_U_(0xFF) << QSPI_BAUD_BAUD_Pos)</span></div>
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<div class="line"><a name="l00163"></a><span class="lineno"> 163</span> <span class="preprocessor">#define QSPI_BAUD_BAUD(value) (QSPI_BAUD_BAUD_Msk & ((value) << QSPI_BAUD_BAUD_Pos))</span></div>
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<div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a3e441fa461541cedde2d9cebff18806f"> 164</a></span> <span class="preprocessor">#define QSPI_BAUD_DLYBS_Pos 16 </span></div>
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<div class="line"><a name="l00165"></a><span class="lineno"> 165</span> <span class="preprocessor">#define QSPI_BAUD_DLYBS_Msk (_U_(0xFF) << QSPI_BAUD_DLYBS_Pos)</span></div>
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<div class="line"><a name="l00166"></a><span class="lineno"> 166</span> <span class="preprocessor">#define QSPI_BAUD_DLYBS(value) (QSPI_BAUD_DLYBS_Msk & ((value) << QSPI_BAUD_DLYBS_Pos))</span></div>
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<div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ad1b5f1c147c5c49bdb3ee765aa452ff4"> 167</a></span> <span class="preprocessor">#define QSPI_BAUD_MASK _U_(0x00FFFF03) </span></div>
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<div class="line"><a name="l00169"></a><span class="lineno"> 169</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_RXDATA : (QSPI Offset: 0x0C) (R/ 32) Receive Data -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00170"></a><span class="lineno"> 170</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="unionQSPI__RXDATA__Type.html"> 171</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00172"></a><span class="lineno"> 172</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="unionQSPI__RXDATA__Type.html#ac60e9581b211e70b39ad4ab1f6566049"> 173</a></span>  uint32_t <a class="code" href="unionQSPI__RXDATA__Type.html#ac60e9581b211e70b39ad4ab1f6566049">DATA</a>:16; </div>
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<div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="unionQSPI__RXDATA__Type.html#a9eff7e5f2ca13da6a28d8b0bf99a92f6"> 174</a></span>  uint32_t :16; </div>
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<div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="unionQSPI__RXDATA__Type.html#a0d8d33531b0f95a5149804382ec8e76c"> 175</a></span>  } bit; </div>
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<div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="unionQSPI__RXDATA__Type.html#af8af6e25ff115308ebeb9bab37848455"> 176</a></span>  uint32_t <a class="code" href="unionQSPI__RXDATA__Type.html#af8af6e25ff115308ebeb9bab37848455">reg</a>; </div>
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<div class="line"><a name="l00177"></a><span class="lineno"> 177</span> } <a class="code" href="unionQSPI__RXDATA__Type.html">QSPI_RXDATA_Type</a>;</div>
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<div class="line"><a name="l00178"></a><span class="lineno"> 178</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00179"></a><span class="lineno"> 179</span>  </div>
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<div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a87be3956bd37543321c112cbb877e782"> 180</a></span> <span class="preprocessor">#define QSPI_RXDATA_OFFSET 0x0C </span></div>
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<div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a9cd293dea7e9832403612f95104ed613"> 181</a></span> <span class="preprocessor">#define QSPI_RXDATA_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ad47fc7a9b32733011d0cbbf53b974aeb"> 183</a></span> <span class="preprocessor">#define QSPI_RXDATA_DATA_Pos 0 </span></div>
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<div class="line"><a name="l00184"></a><span class="lineno"> 184</span> <span class="preprocessor">#define QSPI_RXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_RXDATA_DATA_Pos)</span></div>
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<div class="line"><a name="l00185"></a><span class="lineno"> 185</span> <span class="preprocessor">#define QSPI_RXDATA_DATA(value) (QSPI_RXDATA_DATA_Msk & ((value) << QSPI_RXDATA_DATA_Pos))</span></div>
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<div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a3fd4ee385b606854e969ddc1e60ad209"> 186</a></span> <span class="preprocessor">#define QSPI_RXDATA_MASK _U_(0x0000FFFF) </span></div>
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<div class="line"><a name="l00188"></a><span class="lineno"> 188</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_TXDATA : (QSPI Offset: 0x10) ( /W 32) Transmit Data -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00189"></a><span class="lineno"> 189</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="unionQSPI__TXDATA__Type.html"> 190</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00191"></a><span class="lineno"> 191</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="unionQSPI__TXDATA__Type.html#a9bee83ef09844cc99cb5bac60e32e0c9"> 192</a></span>  uint32_t <a class="code" href="unionQSPI__TXDATA__Type.html#a9bee83ef09844cc99cb5bac60e32e0c9">DATA</a>:16; </div>
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<div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="unionQSPI__TXDATA__Type.html#af633020eef13d47e16f6541414b30e47"> 193</a></span>  uint32_t :16; </div>
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<div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="unionQSPI__TXDATA__Type.html#a551d1b3fb19774f78969732490338822"> 194</a></span>  } bit; </div>
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<div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="unionQSPI__TXDATA__Type.html#a4a243118dc07f06e2fe435281b31631e"> 195</a></span>  uint32_t <a class="code" href="unionQSPI__TXDATA__Type.html#a4a243118dc07f06e2fe435281b31631e">reg</a>; </div>
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<div class="line"><a name="l00196"></a><span class="lineno"> 196</span> } <a class="code" href="unionQSPI__TXDATA__Type.html">QSPI_TXDATA_Type</a>;</div>
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<div class="line"><a name="l00197"></a><span class="lineno"> 197</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00198"></a><span class="lineno"> 198</span>  </div>
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<div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a0ca429506a8e6b03fb928b3a26c20bfc"> 199</a></span> <span class="preprocessor">#define QSPI_TXDATA_OFFSET 0x10 </span></div>
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<div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a3477e070bac8c154a985baae65233b38"> 200</a></span> <span class="preprocessor">#define QSPI_TXDATA_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#aebe5e7d967560044c44c7c65b4420e69"> 202</a></span> <span class="preprocessor">#define QSPI_TXDATA_DATA_Pos 0 </span></div>
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<div class="line"><a name="l00203"></a><span class="lineno"> 203</span> <span class="preprocessor">#define QSPI_TXDATA_DATA_Msk (_U_(0xFFFF) << QSPI_TXDATA_DATA_Pos)</span></div>
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<div class="line"><a name="l00204"></a><span class="lineno"> 204</span> <span class="preprocessor">#define QSPI_TXDATA_DATA(value) (QSPI_TXDATA_DATA_Msk & ((value) << QSPI_TXDATA_DATA_Pos))</span></div>
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<div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a1da1b467d64f72334eb2797919ceec36"> 205</a></span> <span class="preprocessor">#define QSPI_TXDATA_MASK _U_(0x0000FFFF) </span></div>
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<div class="line"><a name="l00207"></a><span class="lineno"> 207</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_INTENCLR : (QSPI Offset: 0x14) (R/W 32) Interrupt Enable Clear -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00208"></a><span class="lineno"> 208</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00209"></a><span class="lineno"><a class="line" href="unionQSPI__INTENCLR__Type.html"> 209</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00210"></a><span class="lineno"> 210</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00211"></a><span class="lineno"><a class="line" href="unionQSPI__INTENCLR__Type.html#a8d6b46846898fd220fe13afd575e2cdc"> 211</a></span>  uint32_t <a class="code" href="unionQSPI__INTENCLR__Type.html#a8d6b46846898fd220fe13afd575e2cdc">RXC</a>:1; </div>
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<div class="line"><a name="l00212"></a><span class="lineno"><a class="line" href="unionQSPI__INTENCLR__Type.html#a43364fbb0a002e6ec67d6f4add99264c"> 212</a></span>  uint32_t <a class="code" href="unionQSPI__INTENCLR__Type.html#a43364fbb0a002e6ec67d6f4add99264c">DRE</a>:1; </div>
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<div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="unionQSPI__INTENCLR__Type.html#ab4105436857762b9a2386aacdeed5bf5"> 213</a></span>  uint32_t <a class="code" href="unionQSPI__INTENCLR__Type.html#ab4105436857762b9a2386aacdeed5bf5">TXC</a>:1; </div>
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<div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="unionQSPI__INTENCLR__Type.html#af93a9ea2597954d114e08eb276585504"> 214</a></span>  uint32_t <a class="code" href="unionQSPI__INTENCLR__Type.html#af93a9ea2597954d114e08eb276585504">ERROR</a>:1; </div>
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<div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="unionQSPI__INTENCLR__Type.html#a0429aaf48027e8d627bd97f6cf3ceabf"> 215</a></span>  uint32_t :4; </div>
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<div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="unionQSPI__INTENCLR__Type.html#af7fd69f6df15870be2385284008aea70"> 216</a></span>  uint32_t <a class="code" href="unionQSPI__INTENCLR__Type.html#af7fd69f6df15870be2385284008aea70">CSRISE</a>:1; </div>
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<div class="line"><a name="l00217"></a><span class="lineno"><a class="line" href="unionQSPI__INTENCLR__Type.html#a4decee37be777063e4189921576b76ac"> 217</a></span>  uint32_t :1; </div>
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<div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="unionQSPI__INTENCLR__Type.html#a1487ebc330c7c34c3e8cfe2d40d83866"> 218</a></span>  uint32_t <a class="code" href="unionQSPI__INTENCLR__Type.html#a1487ebc330c7c34c3e8cfe2d40d83866">INSTREND</a>:1; </div>
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<div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="unionQSPI__INTENCLR__Type.html#a024ccf5ad4461cedf2565fa2b000c58f"> 219</a></span>  uint32_t :21; </div>
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<div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="unionQSPI__INTENCLR__Type.html#ab3a7c4e0f4057a8a8fc6a6b8c992e768"> 220</a></span>  } bit; </div>
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<div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="unionQSPI__INTENCLR__Type.html#a2fd40dd28ffb06979281df6f416b1381"> 221</a></span>  uint32_t <a class="code" href="unionQSPI__INTENCLR__Type.html#a2fd40dd28ffb06979281df6f416b1381">reg</a>; </div>
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<div class="line"><a name="l00222"></a><span class="lineno"> 222</span> } <a class="code" href="unionQSPI__INTENCLR__Type.html">QSPI_INTENCLR_Type</a>;</div>
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<div class="line"><a name="l00223"></a><span class="lineno"> 223</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00224"></a><span class="lineno"> 224</span>  </div>
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<div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a4321f52defba88894f82de95c788061c"> 225</a></span> <span class="preprocessor">#define QSPI_INTENCLR_OFFSET 0x14 </span></div>
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<div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ab73ffd7857c52aaaaf917fa1d84d0328"> 226</a></span> <span class="preprocessor">#define QSPI_INTENCLR_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a5b9805de8712962cc9135be72b0b5d71"> 228</a></span> <span class="preprocessor">#define QSPI_INTENCLR_RXC_Pos 0 </span></div>
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<div class="line"><a name="l00229"></a><span class="lineno"> 229</span> <span class="preprocessor">#define QSPI_INTENCLR_RXC (_U_(0x1) << QSPI_INTENCLR_RXC_Pos)</span></div>
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<div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ac563a4fd687c21fa4afae3ef903fe85b"> 230</a></span> <span class="preprocessor">#define QSPI_INTENCLR_DRE_Pos 1 </span></div>
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<div class="line"><a name="l00231"></a><span class="lineno"> 231</span> <span class="preprocessor">#define QSPI_INTENCLR_DRE (_U_(0x1) << QSPI_INTENCLR_DRE_Pos)</span></div>
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<div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ae24c24d43074574f48a3b4d3286ff8cd"> 232</a></span> <span class="preprocessor">#define QSPI_INTENCLR_TXC_Pos 2 </span></div>
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<div class="line"><a name="l00233"></a><span class="lineno"> 233</span> <span class="preprocessor">#define QSPI_INTENCLR_TXC (_U_(0x1) << QSPI_INTENCLR_TXC_Pos)</span></div>
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<div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a1d86a274a38b2658da8dfbc529929172"> 234</a></span> <span class="preprocessor">#define QSPI_INTENCLR_ERROR_Pos 3 </span></div>
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<div class="line"><a name="l00235"></a><span class="lineno"> 235</span> <span class="preprocessor">#define QSPI_INTENCLR_ERROR (_U_(0x1) << QSPI_INTENCLR_ERROR_Pos)</span></div>
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<div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#aba20d5848fc2b9b010b84e2c28c6ca81"> 236</a></span> <span class="preprocessor">#define QSPI_INTENCLR_CSRISE_Pos 8 </span></div>
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<div class="line"><a name="l00237"></a><span class="lineno"> 237</span> <span class="preprocessor">#define QSPI_INTENCLR_CSRISE (_U_(0x1) << QSPI_INTENCLR_CSRISE_Pos)</span></div>
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<div class="line"><a name="l00238"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a89c51cbaa84c36e63aab68f6ff9c7e8c"> 238</a></span> <span class="preprocessor">#define QSPI_INTENCLR_INSTREND_Pos 10 </span></div>
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<div class="line"><a name="l00239"></a><span class="lineno"> 239</span> <span class="preprocessor">#define QSPI_INTENCLR_INSTREND (_U_(0x1) << QSPI_INTENCLR_INSTREND_Pos)</span></div>
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<div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a22f05d7b924c11eb3ff9aa1539a70e4e"> 240</a></span> <span class="preprocessor">#define QSPI_INTENCLR_MASK _U_(0x0000050F) </span></div>
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<div class="line"><a name="l00242"></a><span class="lineno"> 242</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_INTENSET : (QSPI Offset: 0x18) (R/W 32) Interrupt Enable Set -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00243"></a><span class="lineno"> 243</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="unionQSPI__INTENSET__Type.html"> 244</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00245"></a><span class="lineno"> 245</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="unionQSPI__INTENSET__Type.html#a7a0e65ab51f1e2a81aea30ba5773900a"> 246</a></span>  uint32_t <a class="code" href="unionQSPI__INTENSET__Type.html#a7a0e65ab51f1e2a81aea30ba5773900a">RXC</a>:1; </div>
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<div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="unionQSPI__INTENSET__Type.html#abfad9d948c90044fcaf367e3499301a1"> 247</a></span>  uint32_t <a class="code" href="unionQSPI__INTENSET__Type.html#abfad9d948c90044fcaf367e3499301a1">DRE</a>:1; </div>
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<div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="unionQSPI__INTENSET__Type.html#a1ecfd772eb0b7fd8b56745bde327edee"> 248</a></span>  uint32_t <a class="code" href="unionQSPI__INTENSET__Type.html#a1ecfd772eb0b7fd8b56745bde327edee">TXC</a>:1; </div>
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<div class="line"><a name="l00249"></a><span class="lineno"><a class="line" href="unionQSPI__INTENSET__Type.html#a0b6a000f84f497776d67f13756937ee1"> 249</a></span>  uint32_t <a class="code" href="unionQSPI__INTENSET__Type.html#a0b6a000f84f497776d67f13756937ee1">ERROR</a>:1; </div>
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<div class="line"><a name="l00250"></a><span class="lineno"><a class="line" href="unionQSPI__INTENSET__Type.html#adf341d62c5de3bde684a1528db190968"> 250</a></span>  uint32_t :4; </div>
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<div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="unionQSPI__INTENSET__Type.html#a54e6cfe0fded456c1f115964c22ee5a4"> 251</a></span>  uint32_t <a class="code" href="unionQSPI__INTENSET__Type.html#a54e6cfe0fded456c1f115964c22ee5a4">CSRISE</a>:1; </div>
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<div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="unionQSPI__INTENSET__Type.html#a99da191d9555483e5758bfa14e79c287"> 252</a></span>  uint32_t :1; </div>
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<div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="unionQSPI__INTENSET__Type.html#ad00a5f3343ee143b50a8000c879ca109"> 253</a></span>  uint32_t <a class="code" href="unionQSPI__INTENSET__Type.html#ad00a5f3343ee143b50a8000c879ca109">INSTREND</a>:1; </div>
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<div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="unionQSPI__INTENSET__Type.html#ac8074dbe667ad115898af47f4fa8aa62"> 254</a></span>  uint32_t :21; </div>
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<div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="unionQSPI__INTENSET__Type.html#ad45e1b3abdbfe6130f116aaefbc81428"> 255</a></span>  } bit; </div>
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<div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="unionQSPI__INTENSET__Type.html#a3eb8216a8ed325db6a6c8a748150717a"> 256</a></span>  uint32_t <a class="code" href="unionQSPI__INTENSET__Type.html#a3eb8216a8ed325db6a6c8a748150717a">reg</a>; </div>
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<div class="line"><a name="l00257"></a><span class="lineno"> 257</span> } <a class="code" href="unionQSPI__INTENSET__Type.html">QSPI_INTENSET_Type</a>;</div>
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<div class="line"><a name="l00258"></a><span class="lineno"> 258</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00259"></a><span class="lineno"> 259</span>  </div>
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<div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a2a63dd66c5cb383bb8084b64937c3558"> 260</a></span> <span class="preprocessor">#define QSPI_INTENSET_OFFSET 0x18 </span></div>
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<div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a408d2403d145db488089cbfbb0943b2c"> 261</a></span> <span class="preprocessor">#define QSPI_INTENSET_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a651a6fd970141862c48f631cbe357722"> 263</a></span> <span class="preprocessor">#define QSPI_INTENSET_RXC_Pos 0 </span></div>
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<div class="line"><a name="l00264"></a><span class="lineno"> 264</span> <span class="preprocessor">#define QSPI_INTENSET_RXC (_U_(0x1) << QSPI_INTENSET_RXC_Pos)</span></div>
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<div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a1ee4feba51c2d52059d91c847816c461"> 265</a></span> <span class="preprocessor">#define QSPI_INTENSET_DRE_Pos 1 </span></div>
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<div class="line"><a name="l00266"></a><span class="lineno"> 266</span> <span class="preprocessor">#define QSPI_INTENSET_DRE (_U_(0x1) << QSPI_INTENSET_DRE_Pos)</span></div>
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<div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#aa632d7c75c0c176136f760243fc92ecc"> 267</a></span> <span class="preprocessor">#define QSPI_INTENSET_TXC_Pos 2 </span></div>
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<div class="line"><a name="l00268"></a><span class="lineno"> 268</span> <span class="preprocessor">#define QSPI_INTENSET_TXC (_U_(0x1) << QSPI_INTENSET_TXC_Pos)</span></div>
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<div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ae56879a2c995c8759c94236e6b225fbd"> 269</a></span> <span class="preprocessor">#define QSPI_INTENSET_ERROR_Pos 3 </span></div>
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<div class="line"><a name="l00270"></a><span class="lineno"> 270</span> <span class="preprocessor">#define QSPI_INTENSET_ERROR (_U_(0x1) << QSPI_INTENSET_ERROR_Pos)</span></div>
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<div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a7a39ce2779333876efea464eb8abd6a6"> 271</a></span> <span class="preprocessor">#define QSPI_INTENSET_CSRISE_Pos 8 </span></div>
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<div class="line"><a name="l00272"></a><span class="lineno"> 272</span> <span class="preprocessor">#define QSPI_INTENSET_CSRISE (_U_(0x1) << QSPI_INTENSET_CSRISE_Pos)</span></div>
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<div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a28af271389d49bba36a16e773053afbc"> 273</a></span> <span class="preprocessor">#define QSPI_INTENSET_INSTREND_Pos 10 </span></div>
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<div class="line"><a name="l00274"></a><span class="lineno"> 274</span> <span class="preprocessor">#define QSPI_INTENSET_INSTREND (_U_(0x1) << QSPI_INTENSET_INSTREND_Pos)</span></div>
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<div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a363a82e8a3a1262e9894d537d3269a80"> 275</a></span> <span class="preprocessor">#define QSPI_INTENSET_MASK _U_(0x0000050F) </span></div>
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<div class="line"><a name="l00277"></a><span class="lineno"> 277</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_INTFLAG : (QSPI Offset: 0x1C) (R/W 32) Interrupt Flag Status and Clear -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00278"></a><span class="lineno"> 278</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="unionQSPI__INTFLAG__Type.html"> 279</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{ <span class="comment">// __I to avoid read-modify-write on write-to-clear register</span></div>
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<div class="line"><a name="l00280"></a><span class="lineno"> 280</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="unionQSPI__INTFLAG__Type.html#a80d501d18d0dfa44ed1dc4a0d3cb5117"> 281</a></span>  __I uint32_t <a class="code" href="unionQSPI__INTFLAG__Type.html#a80d501d18d0dfa44ed1dc4a0d3cb5117">RXC</a>:1; </div>
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<div class="line"><a name="l00282"></a><span class="lineno"><a class="line" href="unionQSPI__INTFLAG__Type.html#a307d69bd98ee2ae1e1dd069007fd4e4e"> 282</a></span>  __I uint32_t <a class="code" href="unionQSPI__INTFLAG__Type.html#a307d69bd98ee2ae1e1dd069007fd4e4e">DRE</a>:1; </div>
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<div class="line"><a name="l00283"></a><span class="lineno"><a class="line" href="unionQSPI__INTFLAG__Type.html#a1f3e1e85e417bf929650b0f01ef37c80"> 283</a></span>  __I uint32_t <a class="code" href="unionQSPI__INTFLAG__Type.html#a1f3e1e85e417bf929650b0f01ef37c80">TXC</a>:1; </div>
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<div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="unionQSPI__INTFLAG__Type.html#a0f54f299c07c5df0f9f299b832d662eb"> 284</a></span>  __I uint32_t <a class="code" href="unionQSPI__INTFLAG__Type.html#a0f54f299c07c5df0f9f299b832d662eb">ERROR</a>:1; </div>
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<div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="unionQSPI__INTFLAG__Type.html#a3923a82733e6127e615da2dd8f593ac9"> 285</a></span>  __I <a class="code" href="unionQSPI__INTFLAG__Type.html#a3923a82733e6127e615da2dd8f593ac9">uint32_t</a> :4; </div>
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<div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="unionQSPI__INTFLAG__Type.html#ae6c22aa80c54b555f339b289aa701ac4"> 286</a></span>  __I uint32_t <a class="code" href="unionQSPI__INTFLAG__Type.html#ae6c22aa80c54b555f339b289aa701ac4">CSRISE</a>:1; </div>
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<div class="line"><a name="l00287"></a><span class="lineno"> 287</span>  __I uint32_t :1; </div>
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<div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="unionQSPI__INTFLAG__Type.html#a68c37907555a5b16ed601d7f40801f3c"> 288</a></span>  __I uint32_t <a class="code" href="unionQSPI__INTFLAG__Type.html#a68c37907555a5b16ed601d7f40801f3c">INSTREND</a>:1; </div>
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<div class="line"><a name="l00289"></a><span class="lineno"> 289</span>  __I uint32_t :21; </div>
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<div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="unionQSPI__INTFLAG__Type.html#aba1f34b84704201a660ef3178e535b7c"> 290</a></span>  } bit; </div>
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<div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="unionQSPI__INTFLAG__Type.html#a2f7d3aecf7c0fd69f725ce28acca5dae"> 291</a></span>  uint32_t <a class="code" href="unionQSPI__INTFLAG__Type.html#a2f7d3aecf7c0fd69f725ce28acca5dae">reg</a>; </div>
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<div class="line"><a name="l00292"></a><span class="lineno"> 292</span> } <a class="code" href="unionQSPI__INTFLAG__Type.html">QSPI_INTFLAG_Type</a>;</div>
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<div class="line"><a name="l00293"></a><span class="lineno"> 293</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00294"></a><span class="lineno"> 294</span>  </div>
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<div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a0295b33774924d3c333739f5f9b205ff"> 295</a></span> <span class="preprocessor">#define QSPI_INTFLAG_OFFSET 0x1C </span></div>
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<div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a405437e73598fcb9f2465bac8aeef3fe"> 296</a></span> <span class="preprocessor">#define QSPI_INTFLAG_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a98f549e10ec9cf4e071155feaa20b73d"> 298</a></span> <span class="preprocessor">#define QSPI_INTFLAG_RXC_Pos 0 </span></div>
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<div class="line"><a name="l00299"></a><span class="lineno"> 299</span> <span class="preprocessor">#define QSPI_INTFLAG_RXC (_U_(0x1) << QSPI_INTFLAG_RXC_Pos)</span></div>
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<div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a7a4cdfdde32baa8545e768a00980777f"> 300</a></span> <span class="preprocessor">#define QSPI_INTFLAG_DRE_Pos 1 </span></div>
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<div class="line"><a name="l00301"></a><span class="lineno"> 301</span> <span class="preprocessor">#define QSPI_INTFLAG_DRE (_U_(0x1) << QSPI_INTFLAG_DRE_Pos)</span></div>
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<div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#aae8ba2dd8ab5ade39b7d2ea19f3ac535"> 302</a></span> <span class="preprocessor">#define QSPI_INTFLAG_TXC_Pos 2 </span></div>
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<div class="line"><a name="l00303"></a><span class="lineno"> 303</span> <span class="preprocessor">#define QSPI_INTFLAG_TXC (_U_(0x1) << QSPI_INTFLAG_TXC_Pos)</span></div>
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<div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a6f575f7d2c7bb689dc601da3aa22350c"> 304</a></span> <span class="preprocessor">#define QSPI_INTFLAG_ERROR_Pos 3 </span></div>
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<div class="line"><a name="l00305"></a><span class="lineno"> 305</span> <span class="preprocessor">#define QSPI_INTFLAG_ERROR (_U_(0x1) << QSPI_INTFLAG_ERROR_Pos)</span></div>
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<div class="line"><a name="l00306"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a8adf0a69720752ce53f38530e723d4f8"> 306</a></span> <span class="preprocessor">#define QSPI_INTFLAG_CSRISE_Pos 8 </span></div>
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<div class="line"><a name="l00307"></a><span class="lineno"> 307</span> <span class="preprocessor">#define QSPI_INTFLAG_CSRISE (_U_(0x1) << QSPI_INTFLAG_CSRISE_Pos)</span></div>
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<div class="line"><a name="l00308"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a2630fdda56c7f0cd4c6a96c68963d933"> 308</a></span> <span class="preprocessor">#define QSPI_INTFLAG_INSTREND_Pos 10 </span></div>
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<div class="line"><a name="l00309"></a><span class="lineno"> 309</span> <span class="preprocessor">#define QSPI_INTFLAG_INSTREND (_U_(0x1) << QSPI_INTFLAG_INSTREND_Pos)</span></div>
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<div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ae24f836c5679c8d2b3ac47ca6834aa17"> 310</a></span> <span class="preprocessor">#define QSPI_INTFLAG_MASK _U_(0x0000050F) </span></div>
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<div class="line"><a name="l00312"></a><span class="lineno"> 312</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_STATUS : (QSPI Offset: 0x20) (R/ 32) Status Register -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00313"></a><span class="lineno"> 313</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="unionQSPI__STATUS__Type.html"> 314</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00315"></a><span class="lineno"> 315</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="unionQSPI__STATUS__Type.html#a440957ae0b4296b420d5456617c9d93a"> 316</a></span>  uint32_t :1; </div>
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<div class="line"><a name="l00317"></a><span class="lineno"><a class="line" href="unionQSPI__STATUS__Type.html#ad0f2f07cfdeb7f190fdae3b9ec102f67"> 317</a></span>  uint32_t <a class="code" href="unionQSPI__STATUS__Type.html#ad0f2f07cfdeb7f190fdae3b9ec102f67">ENABLE</a>:1; </div>
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<div class="line"><a name="l00318"></a><span class="lineno"><a class="line" href="unionQSPI__STATUS__Type.html#a69c344eb795496caead6ad2f524ef1df"> 318</a></span>  uint32_t :7; </div>
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<div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="unionQSPI__STATUS__Type.html#a8118ba918187482b90661ade08ff8cd3"> 319</a></span>  uint32_t <a class="code" href="unionQSPI__STATUS__Type.html#a8118ba918187482b90661ade08ff8cd3">CSSTATUS</a>:1; </div>
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<div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="unionQSPI__STATUS__Type.html#aee4c0b07d8a61e5d914cb328e43df513"> 320</a></span>  uint32_t :22; </div>
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<div class="line"><a name="l00321"></a><span class="lineno"><a class="line" href="unionQSPI__STATUS__Type.html#ac243faeeabeb3e5c01d8efb917d3a4f2"> 321</a></span>  } bit; </div>
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<div class="line"><a name="l00322"></a><span class="lineno"><a class="line" href="unionQSPI__STATUS__Type.html#a3f0852a86d19cdde5a080aa904ed1263"> 322</a></span>  uint32_t <a class="code" href="unionQSPI__STATUS__Type.html#a3f0852a86d19cdde5a080aa904ed1263">reg</a>; </div>
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<div class="line"><a name="l00323"></a><span class="lineno"> 323</span> } <a class="code" href="unionQSPI__STATUS__Type.html">QSPI_STATUS_Type</a>;</div>
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<div class="line"><a name="l00324"></a><span class="lineno"> 324</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00325"></a><span class="lineno"> 325</span>  </div>
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<div class="line"><a name="l00326"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a7e6800de30b18ee1c16a17e8c3683b7d"> 326</a></span> <span class="preprocessor">#define QSPI_STATUS_OFFSET 0x20 </span></div>
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<div class="line"><a name="l00327"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#af605ee4eedd56fe75b161ca047fe240f"> 327</a></span> <span class="preprocessor">#define QSPI_STATUS_RESETVALUE _U_(0x00000200) </span></div>
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<div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#aaa88fd251eb3cf0fb4d9654ee7e3d0b1"> 329</a></span> <span class="preprocessor">#define QSPI_STATUS_ENABLE_Pos 1 </span></div>
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<div class="line"><a name="l00330"></a><span class="lineno"> 330</span> <span class="preprocessor">#define QSPI_STATUS_ENABLE (_U_(0x1) << QSPI_STATUS_ENABLE_Pos)</span></div>
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<div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a1c5b8b83243125a3d95ef7cf08405528"> 331</a></span> <span class="preprocessor">#define QSPI_STATUS_CSSTATUS_Pos 9 </span></div>
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<div class="line"><a name="l00332"></a><span class="lineno"> 332</span> <span class="preprocessor">#define QSPI_STATUS_CSSTATUS (_U_(0x1) << QSPI_STATUS_CSSTATUS_Pos)</span></div>
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<div class="line"><a name="l00333"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a2e8ceb017e15659067e5a0290bc3aae0"> 333</a></span> <span class="preprocessor">#define QSPI_STATUS_MASK _U_(0x00000202) </span></div>
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<div class="line"><a name="l00335"></a><span class="lineno"> 335</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_INSTRADDR : (QSPI Offset: 0x30) (R/W 32) Instruction Address -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00336"></a><span class="lineno"> 336</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00337"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRADDR__Type.html"> 337</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00338"></a><span class="lineno"> 338</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00339"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRADDR__Type.html#aeaa5706347b9a351be7d8487eb034f9c"> 339</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRADDR__Type.html#aeaa5706347b9a351be7d8487eb034f9c">ADDR</a>:32; </div>
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<div class="line"><a name="l00340"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRADDR__Type.html#af1d50a840bf7a15c1e9aefeb24a264e6"> 340</a></span>  } bit; </div>
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<div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRADDR__Type.html#affbc8d4e4c51354523c0fb7088403eb0"> 341</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRADDR__Type.html#affbc8d4e4c51354523c0fb7088403eb0">reg</a>; </div>
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<div class="line"><a name="l00342"></a><span class="lineno"> 342</span> } <a class="code" href="unionQSPI__INSTRADDR__Type.html">QSPI_INSTRADDR_Type</a>;</div>
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<div class="line"><a name="l00343"></a><span class="lineno"> 343</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00344"></a><span class="lineno"> 344</span>  </div>
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<div class="line"><a name="l00345"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a53d53b732b99eb81d9fa21610fccf04f"> 345</a></span> <span class="preprocessor">#define QSPI_INSTRADDR_OFFSET 0x30 </span></div>
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<div class="line"><a name="l00346"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a8041535b7b3cd42eb509b610555c5d02"> 346</a></span> <span class="preprocessor">#define QSPI_INSTRADDR_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00348"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ab4d2a4b67a0a69a68bfd8580f8e32ae0"> 348</a></span> <span class="preprocessor">#define QSPI_INSTRADDR_ADDR_Pos 0 </span></div>
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<div class="line"><a name="l00349"></a><span class="lineno"> 349</span> <span class="preprocessor">#define QSPI_INSTRADDR_ADDR_Msk (_U_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos)</span></div>
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<div class="line"><a name="l00350"></a><span class="lineno"> 350</span> <span class="preprocessor">#define QSPI_INSTRADDR_ADDR(value) (QSPI_INSTRADDR_ADDR_Msk & ((value) << QSPI_INSTRADDR_ADDR_Pos))</span></div>
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<div class="line"><a name="l00351"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#af657506ed36c42c07169c45d1a81afa0"> 351</a></span> <span class="preprocessor">#define QSPI_INSTRADDR_MASK _U_(0xFFFFFFFF) </span></div>
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<div class="line"><a name="l00353"></a><span class="lineno"> 353</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_INSTRCTRL : (QSPI Offset: 0x34) (R/W 32) Instruction Code -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00354"></a><span class="lineno"> 354</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRCTRL__Type.html"> 355</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00356"></a><span class="lineno"> 356</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00357"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRCTRL__Type.html#a356bb6a5c99c9d96c896d7000e61bdc3"> 357</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRCTRL__Type.html#a356bb6a5c99c9d96c896d7000e61bdc3">INSTR</a>:8; </div>
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<div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRCTRL__Type.html#afb49edd3ba2be8366867fa56f5be9627"> 358</a></span>  uint32_t :8; </div>
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<div class="line"><a name="l00359"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRCTRL__Type.html#a1a7769aa0471f5cef5a1cc7a45953783"> 359</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRCTRL__Type.html#a1a7769aa0471f5cef5a1cc7a45953783">OPTCODE</a>:8; </div>
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<div class="line"><a name="l00360"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRCTRL__Type.html#a090534f0ec871276826c594300fc9d89"> 360</a></span>  uint32_t :8; </div>
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<div class="line"><a name="l00361"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRCTRL__Type.html#a243f08d3bc4c3d822914a0f3a0598e26"> 361</a></span>  } bit; </div>
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<div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRCTRL__Type.html#a4cdbcc3b434cd974e65fcc699405001d"> 362</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRCTRL__Type.html#a4cdbcc3b434cd974e65fcc699405001d">reg</a>; </div>
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<div class="line"><a name="l00363"></a><span class="lineno"> 363</span> } <a class="code" href="unionQSPI__INSTRCTRL__Type.html">QSPI_INSTRCTRL_Type</a>;</div>
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<div class="line"><a name="l00364"></a><span class="lineno"> 364</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00365"></a><span class="lineno"> 365</span>  </div>
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<div class="line"><a name="l00366"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a74728d0912c0a270c705e0416893f7ce"> 366</a></span> <span class="preprocessor">#define QSPI_INSTRCTRL_OFFSET 0x34 </span></div>
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<div class="line"><a name="l00367"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#aa1ce0ee489840800779fa57320d9e7f0"> 367</a></span> <span class="preprocessor">#define QSPI_INSTRCTRL_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00369"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a5737034b6cd99686ed0476d8139c14f3"> 369</a></span> <span class="preprocessor">#define QSPI_INSTRCTRL_INSTR_Pos 0 </span></div>
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<div class="line"><a name="l00370"></a><span class="lineno"> 370</span> <span class="preprocessor">#define QSPI_INSTRCTRL_INSTR_Msk (_U_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos)</span></div>
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<div class="line"><a name="l00371"></a><span class="lineno"> 371</span> <span class="preprocessor">#define QSPI_INSTRCTRL_INSTR(value) (QSPI_INSTRCTRL_INSTR_Msk & ((value) << QSPI_INSTRCTRL_INSTR_Pos))</span></div>
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<div class="line"><a name="l00372"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a3f78f87325cc59f720d3c5d731ae9dfd"> 372</a></span> <span class="preprocessor">#define QSPI_INSTRCTRL_OPTCODE_Pos 16 </span></div>
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<div class="line"><a name="l00373"></a><span class="lineno"> 373</span> <span class="preprocessor">#define QSPI_INSTRCTRL_OPTCODE_Msk (_U_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos)</span></div>
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<div class="line"><a name="l00374"></a><span class="lineno"> 374</span> <span class="preprocessor">#define QSPI_INSTRCTRL_OPTCODE(value) (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << QSPI_INSTRCTRL_OPTCODE_Pos))</span></div>
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<div class="line"><a name="l00375"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ad1e2bfa26c544c940adf6d484e4c5631"> 375</a></span> <span class="preprocessor">#define QSPI_INSTRCTRL_MASK _U_(0x00FF00FF) </span></div>
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<div class="line"><a name="l00377"></a><span class="lineno"> 377</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_INSTRFRAME : (QSPI Offset: 0x38) (R/W 32) Instruction Frame -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00378"></a><span class="lineno"> 378</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html"> 379</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00380"></a><span class="lineno"> 380</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00381"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#af4e9717d15fbd6daa759da9ab6308641"> 381</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRFRAME__Type.html#af4e9717d15fbd6daa759da9ab6308641">WIDTH</a>:3; </div>
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<div class="line"><a name="l00382"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#a466b46ca78cda0652ff84c94903aafef"> 382</a></span>  uint32_t :1; </div>
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<div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#aba0ceb37c44ea2b53a216333ec6d4b09"> 383</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRFRAME__Type.html#aba0ceb37c44ea2b53a216333ec6d4b09">INSTREN</a>:1; </div>
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<div class="line"><a name="l00384"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#a5a5d3938a338789c3eb040dccb632344"> 384</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRFRAME__Type.html#a5a5d3938a338789c3eb040dccb632344">ADDREN</a>:1; </div>
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<div class="line"><a name="l00385"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#a6c27c6138d6479df2cd8494513a381c0"> 385</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRFRAME__Type.html#a6c27c6138d6479df2cd8494513a381c0">OPTCODEEN</a>:1; </div>
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<div class="line"><a name="l00386"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#a7b56cbadd3b07a83807a60d0f84b7010"> 386</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRFRAME__Type.html#a7b56cbadd3b07a83807a60d0f84b7010">DATAEN</a>:1; </div>
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<div class="line"><a name="l00387"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#a7c66c0225ebd04b6fe659b8ac437feb1"> 387</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRFRAME__Type.html#a7c66c0225ebd04b6fe659b8ac437feb1">OPTCODELEN</a>:2; </div>
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<div class="line"><a name="l00388"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#aa3f3bde47157054c4abb8ef35bfe9722"> 388</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRFRAME__Type.html#aa3f3bde47157054c4abb8ef35bfe9722">ADDRLEN</a>:1; </div>
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<div class="line"><a name="l00389"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#a5aa506201c8e8bbbd1ff5a5b6ac7a66f"> 389</a></span>  uint32_t :1; </div>
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<div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#ab97b3b1aa98ff1c17a5269a3bcf04774"> 390</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRFRAME__Type.html#ab97b3b1aa98ff1c17a5269a3bcf04774">TFRTYPE</a>:2; </div>
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<div class="line"><a name="l00391"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#abbcb827971433af94254a9c7eb9c11bd"> 391</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRFRAME__Type.html#abbcb827971433af94254a9c7eb9c11bd">CRMODE</a>:1; </div>
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<div class="line"><a name="l00392"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#a1470de99b6c195d41fd42bd265483e07"> 392</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRFRAME__Type.html#a1470de99b6c195d41fd42bd265483e07">DDREN</a>:1; </div>
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<div class="line"><a name="l00393"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#aa5f775fcab7e4c40869e065951f95291"> 393</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRFRAME__Type.html#aa5f775fcab7e4c40869e065951f95291">DUMMYLEN</a>:5; </div>
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<div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#ae7b4f6bc08aae70de042fd2ce44d823b"> 394</a></span>  uint32_t :11; </div>
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<div class="line"><a name="l00395"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#a4ffe42722905573b886e1f9d8de0726a"> 395</a></span>  } bit; </div>
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<div class="line"><a name="l00396"></a><span class="lineno"><a class="line" href="unionQSPI__INSTRFRAME__Type.html#aad5648a1261cee34645a8284b55b310e"> 396</a></span>  uint32_t <a class="code" href="unionQSPI__INSTRFRAME__Type.html#aad5648a1261cee34645a8284b55b310e">reg</a>; </div>
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<div class="line"><a name="l00397"></a><span class="lineno"> 397</span> } <a class="code" href="unionQSPI__INSTRFRAME__Type.html">QSPI_INSTRFRAME_Type</a>;</div>
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<div class="line"><a name="l00398"></a><span class="lineno"> 398</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00399"></a><span class="lineno"> 399</span>  </div>
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<div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ab66ce90540b377e88cc87ff352c536a4"> 400</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_OFFSET 0x38 </span></div>
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<div class="line"><a name="l00401"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#aedcbbeea8784cb67427cb06f00b9b73e"> 401</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00403"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a5f6b8cb121eb8e171b4a864252c6e837"> 403</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_Pos 0 </span></div>
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<div class="line"><a name="l00404"></a><span class="lineno"> 404</span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_Msk (_U_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos)</span></div>
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<div class="line"><a name="l00405"></a><span class="lineno"> 405</span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH(value) (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << QSPI_INSTRFRAME_WIDTH_Pos))</span></div>
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<div class="line"><a name="l00406"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ab8b427909c7320d8ca41e0ff6034ffcf"> 406</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val _U_(0x0) </span></div>
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<div class="line"><a name="l00407"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a03c466b6e763fa6d75f18b88536bcef6"> 407</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val _U_(0x1) </span></div>
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<div class="line"><a name="l00408"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a28a462a81538156bd39098f8f1f4c908"> 408</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val _U_(0x2) </span></div>
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<div class="line"><a name="l00409"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a64363c446a0322ad48abc9115f7a4073"> 409</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val _U_(0x3) </span></div>
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<div class="line"><a name="l00410"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a8082139abf8aea1bf61d2d73417e0d63"> 410</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val _U_(0x4) </span></div>
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<div class="line"><a name="l00411"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a0c9c48a46e4243e666f5d2778616d5fd"> 411</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val _U_(0x5) </span></div>
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<div class="line"><a name="l00412"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a4b16ae5f4120aba8080c2075c0c85107"> 412</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val _U_(0x6) </span></div>
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<div class="line"><a name="l00413"></a><span class="lineno"> 413</span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos)</span></div>
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<div class="line"><a name="l00414"></a><span class="lineno"> 414</span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)</span></div>
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<div class="line"><a name="l00415"></a><span class="lineno"> 415</span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)</span></div>
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<div class="line"><a name="l00416"></a><span class="lineno"> 416</span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_DUAL_IO (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)</span></div>
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<div class="line"><a name="l00417"></a><span class="lineno"> 417</span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_QUAD_IO (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)</span></div>
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<div class="line"><a name="l00418"></a><span class="lineno"> 418</span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)</span></div>
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<div class="line"><a name="l00419"></a><span class="lineno"> 419</span> <span class="preprocessor">#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)</span></div>
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<div class="line"><a name="l00420"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a0843a1698c23e27569fb71b0b3ae02ba"> 420</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_INSTREN_Pos 4 </span></div>
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<div class="line"><a name="l00421"></a><span class="lineno"> 421</span> <span class="preprocessor">#define QSPI_INSTRFRAME_INSTREN (_U_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos)</span></div>
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<div class="line"><a name="l00422"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ac6406ae6a861ba312ba41d9431bf52a7"> 422</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_ADDREN_Pos 5 </span></div>
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<div class="line"><a name="l00423"></a><span class="lineno"> 423</span> <span class="preprocessor">#define QSPI_INSTRFRAME_ADDREN (_U_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos)</span></div>
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<div class="line"><a name="l00424"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#af7ff4d7f4f670762eba7a59aa22e9c29"> 424</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODEEN_Pos 6 </span></div>
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<div class="line"><a name="l00425"></a><span class="lineno"> 425</span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODEEN (_U_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos)</span></div>
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<div class="line"><a name="l00426"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#adee8fa29957db9951e7c5fd33a406695"> 426</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_DATAEN_Pos 7 </span></div>
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<div class="line"><a name="l00427"></a><span class="lineno"> 427</span> <span class="preprocessor">#define QSPI_INSTRFRAME_DATAEN (_U_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos)</span></div>
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<div class="line"><a name="l00428"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a923187fc9942a4915faf4044178d1a05"> 428</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODELEN_Pos 8 </span></div>
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<div class="line"><a name="l00429"></a><span class="lineno"> 429</span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODELEN_Msk (_U_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos)</span></div>
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<div class="line"><a name="l00430"></a><span class="lineno"> 430</span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODELEN(value) (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODELEN_Pos))</span></div>
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<div class="line"><a name="l00431"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a64f49c3e874ab484109880274c45d2eb"> 431</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val _U_(0x0) </span></div>
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<div class="line"><a name="l00432"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#acf488437ecfe7c0c0aa186c7080dda5f"> 432</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val _U_(0x1) </span></div>
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<div class="line"><a name="l00433"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ac74f989f9c35449db596e47892d8ebdd"> 433</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val _U_(0x2) </span></div>
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<div class="line"><a name="l00434"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#aafeff47fb7739c3048d6be6f3f10d490"> 434</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val _U_(0x3) </span></div>
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<div class="line"><a name="l00435"></a><span class="lineno"> 435</span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODELEN_1BIT (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)</span></div>
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<div class="line"><a name="l00436"></a><span class="lineno"> 436</span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODELEN_2BITS (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)</span></div>
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<div class="line"><a name="l00437"></a><span class="lineno"> 437</span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODELEN_4BITS (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)</span></div>
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<div class="line"><a name="l00438"></a><span class="lineno"> 438</span> <span class="preprocessor">#define QSPI_INSTRFRAME_OPTCODELEN_8BITS (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)</span></div>
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<div class="line"><a name="l00439"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a440d902fc7241e1108aeb3d50e700624"> 439</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_ADDRLEN_Pos 10 </span></div>
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<div class="line"><a name="l00440"></a><span class="lineno"> 440</span> <span class="preprocessor">#define QSPI_INSTRFRAME_ADDRLEN (_U_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos)</span></div>
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<div class="line"><a name="l00441"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a8727889d2a96d4323b9c96d03e53e451"> 441</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_ADDRLEN_24BITS_Val _U_(0x0) </span></div>
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<div class="line"><a name="l00442"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ada34328fde3d54c15380cd1c5e5ca3a9"> 442</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_ADDRLEN_32BITS_Val _U_(0x1) </span></div>
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<div class="line"><a name="l00443"></a><span class="lineno"> 443</span> <span class="preprocessor">#define QSPI_INSTRFRAME_ADDRLEN_24BITS (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)</span></div>
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<div class="line"><a name="l00444"></a><span class="lineno"> 444</span> <span class="preprocessor">#define QSPI_INSTRFRAME_ADDRLEN_32BITS (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)</span></div>
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<div class="line"><a name="l00445"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#aa72d8939be0af6821a1593d0597af785"> 445</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_TFRTYPE_Pos 12 </span></div>
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<div class="line"><a name="l00446"></a><span class="lineno"> 446</span> <span class="preprocessor">#define QSPI_INSTRFRAME_TFRTYPE_Msk (_U_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos)</span></div>
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<div class="line"><a name="l00447"></a><span class="lineno"> 447</span> <span class="preprocessor">#define QSPI_INSTRFRAME_TFRTYPE(value) (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << QSPI_INSTRFRAME_TFRTYPE_Pos))</span></div>
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<div class="line"><a name="l00448"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ab8537a06c56a445da40d0947edba99b7"> 448</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_TFRTYPE_READ_Val _U_(0x0) </span></div>
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<div class="line"><a name="l00449"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#afe76dd530506516ca7ab6756bea3d23e"> 449</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val _U_(0x1) </span></div>
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<div class="line"><a name="l00450"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ab78f113a8fe8b4fc0fd056f2f49eeb04"> 450</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_TFRTYPE_WRITE_Val _U_(0x2) </span></div>
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<div class="line"><a name="l00451"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a836f913b830e6d77f2e89a5034a79f84"> 451</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val _U_(0x3) </span></div>
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<div class="line"><a name="l00452"></a><span class="lineno"> 452</span> <span class="preprocessor">#define QSPI_INSTRFRAME_TFRTYPE_READ (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)</span></div>
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<div class="line"><a name="l00453"></a><span class="lineno"> 453</span> <span class="preprocessor">#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)</span></div>
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<div class="line"><a name="l00454"></a><span class="lineno"> 454</span> <span class="preprocessor">#define QSPI_INSTRFRAME_TFRTYPE_WRITE (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)</span></div>
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<div class="line"><a name="l00455"></a><span class="lineno"> 455</span> <span class="preprocessor">#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)</span></div>
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<div class="line"><a name="l00456"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a476f3ff950fefce63da315c5bdf86ec5"> 456</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_CRMODE_Pos 14 </span></div>
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<div class="line"><a name="l00457"></a><span class="lineno"> 457</span> <span class="preprocessor">#define QSPI_INSTRFRAME_CRMODE (_U_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos)</span></div>
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<div class="line"><a name="l00458"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a26ec5331c17d1fdcb0b29af957828a14"> 458</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_DDREN_Pos 15 </span></div>
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<div class="line"><a name="l00459"></a><span class="lineno"> 459</span> <span class="preprocessor">#define QSPI_INSTRFRAME_DDREN (_U_(0x1) << QSPI_INSTRFRAME_DDREN_Pos)</span></div>
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<div class="line"><a name="l00460"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#af0ca18bc8af0098f38b5a7f536d8cab9"> 460</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_DUMMYLEN_Pos 16 </span></div>
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<div class="line"><a name="l00461"></a><span class="lineno"> 461</span> <span class="preprocessor">#define QSPI_INSTRFRAME_DUMMYLEN_Msk (_U_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos)</span></div>
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<div class="line"><a name="l00462"></a><span class="lineno"> 462</span> <span class="preprocessor">#define QSPI_INSTRFRAME_DUMMYLEN(value) (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << QSPI_INSTRFRAME_DUMMYLEN_Pos))</span></div>
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<div class="line"><a name="l00463"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a45edf136a4e4b5219cda1aed53461ad1"> 463</a></span> <span class="preprocessor">#define QSPI_INSTRFRAME_MASK _U_(0x001FF7F7) </span></div>
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<div class="line"><a name="l00465"></a><span class="lineno"> 465</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_SCRAMBCTRL : (QSPI Offset: 0x40) (R/W 32) Scrambling Mode -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00466"></a><span class="lineno"> 466</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00467"></a><span class="lineno"><a class="line" href="unionQSPI__SCRAMBCTRL__Type.html"> 467</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00468"></a><span class="lineno"> 468</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00469"></a><span class="lineno"><a class="line" href="unionQSPI__SCRAMBCTRL__Type.html#ad5dcc58c8e20dc1c93c9275502c3d09d"> 469</a></span>  uint32_t <a class="code" href="unionQSPI__SCRAMBCTRL__Type.html#ad5dcc58c8e20dc1c93c9275502c3d09d">ENABLE</a>:1; </div>
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<div class="line"><a name="l00470"></a><span class="lineno"><a class="line" href="unionQSPI__SCRAMBCTRL__Type.html#abbdc62da58889b56a0046e387dcc61d9"> 470</a></span>  uint32_t <a class="code" href="unionQSPI__SCRAMBCTRL__Type.html#abbdc62da58889b56a0046e387dcc61d9">RANDOMDIS</a>:1; </div>
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<div class="line"><a name="l00471"></a><span class="lineno"><a class="line" href="unionQSPI__SCRAMBCTRL__Type.html#a1914e0919e66c42a1e74498aba6d815c"> 471</a></span>  uint32_t :30; </div>
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<div class="line"><a name="l00472"></a><span class="lineno"><a class="line" href="unionQSPI__SCRAMBCTRL__Type.html#afb15da6ce1aae39ab30e983d490d4a48"> 472</a></span>  } bit; </div>
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<div class="line"><a name="l00473"></a><span class="lineno"><a class="line" href="unionQSPI__SCRAMBCTRL__Type.html#a052962dacf4c4eec5acb9812e9e84c9a"> 473</a></span>  uint32_t <a class="code" href="unionQSPI__SCRAMBCTRL__Type.html#a052962dacf4c4eec5acb9812e9e84c9a">reg</a>; </div>
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<div class="line"><a name="l00474"></a><span class="lineno"> 474</span> } <a class="code" href="unionQSPI__SCRAMBCTRL__Type.html">QSPI_SCRAMBCTRL_Type</a>;</div>
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<div class="line"><a name="l00475"></a><span class="lineno"> 475</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00476"></a><span class="lineno"> 476</span>  </div>
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<div class="line"><a name="l00477"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a9f7acff6060bd153c03ee375a416abc1"> 477</a></span> <span class="preprocessor">#define QSPI_SCRAMBCTRL_OFFSET 0x40 </span></div>
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<div class="line"><a name="l00478"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a6da38b6cbd11e1d96dc9ad1e2222b8bd"> 478</a></span> <span class="preprocessor">#define QSPI_SCRAMBCTRL_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00480"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a2f232227955f50262bddc1e61a89ff84"> 480</a></span> <span class="preprocessor">#define QSPI_SCRAMBCTRL_ENABLE_Pos 0 </span></div>
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<div class="line"><a name="l00481"></a><span class="lineno"> 481</span> <span class="preprocessor">#define QSPI_SCRAMBCTRL_ENABLE (_U_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos)</span></div>
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<div class="line"><a name="l00482"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ae0be1ea93dedc3ea78044e7689027215"> 482</a></span> <span class="preprocessor">#define QSPI_SCRAMBCTRL_RANDOMDIS_Pos 1 </span></div>
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<div class="line"><a name="l00483"></a><span class="lineno"> 483</span> <span class="preprocessor">#define QSPI_SCRAMBCTRL_RANDOMDIS (_U_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos)</span></div>
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<div class="line"><a name="l00484"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ad22d15dfb114dc6a1a1ed5fd883336db"> 484</a></span> <span class="preprocessor">#define QSPI_SCRAMBCTRL_MASK _U_(0x00000003) </span></div>
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<div class="line"><a name="l00486"></a><span class="lineno"> 486</span> <span class="preprocessor"></span><span class="comment">/* -------- QSPI_SCRAMBKEY : (QSPI Offset: 0x44) ( /W 32) Scrambling Key -------- */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00487"></a><span class="lineno"> 487</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00488"></a><span class="lineno"><a class="line" href="unionQSPI__SCRAMBKEY__Type.html"> 488</a></span> <span class="keyword">typedef</span> <span class="keyword">union </span>{</div>
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<div class="line"><a name="l00489"></a><span class="lineno"> 489</span>  <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00490"></a><span class="lineno"><a class="line" href="unionQSPI__SCRAMBKEY__Type.html#a3ad1c3c8a178b733ac83375faa3f9ab4"> 490</a></span>  uint32_t <a class="code" href="unionQSPI__SCRAMBKEY__Type.html#a3ad1c3c8a178b733ac83375faa3f9ab4">KEY</a>:32; </div>
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<div class="line"><a name="l00491"></a><span class="lineno"><a class="line" href="unionQSPI__SCRAMBKEY__Type.html#af31227b75a36554b63ec702b43120992"> 491</a></span>  } bit; </div>
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<div class="line"><a name="l00492"></a><span class="lineno"><a class="line" href="unionQSPI__SCRAMBKEY__Type.html#ae6a5ec1d96755202750e371951cd3c5f"> 492</a></span>  uint32_t <a class="code" href="unionQSPI__SCRAMBKEY__Type.html#ae6a5ec1d96755202750e371951cd3c5f">reg</a>; </div>
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<div class="line"><a name="l00493"></a><span class="lineno"> 493</span> } <a class="code" href="unionQSPI__SCRAMBKEY__Type.html">QSPI_SCRAMBKEY_Type</a>;</div>
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<div class="line"><a name="l00494"></a><span class="lineno"> 494</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00495"></a><span class="lineno"> 495</span>  </div>
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<div class="line"><a name="l00496"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a8b2884969f43bf3ab836cc58f80c6f60"> 496</a></span> <span class="preprocessor">#define QSPI_SCRAMBKEY_OFFSET 0x44 </span></div>
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<div class="line"><a name="l00497"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#ab7bf6ac11510711a9128d215c055bc53"> 497</a></span> <span class="preprocessor">#define QSPI_SCRAMBKEY_RESETVALUE _U_(0x00000000) </span></div>
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<div class="line"><a name="l00499"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#a2b83fe892cc0b989a9b1790ba647eff9"> 499</a></span> <span class="preprocessor">#define QSPI_SCRAMBKEY_KEY_Pos 0 </span></div>
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<div class="line"><a name="l00500"></a><span class="lineno"> 500</span> <span class="preprocessor">#define QSPI_SCRAMBKEY_KEY_Msk (_U_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos)</span></div>
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<div class="line"><a name="l00501"></a><span class="lineno"> 501</span> <span class="preprocessor">#define QSPI_SCRAMBKEY_KEY(value) (QSPI_SCRAMBKEY_KEY_Msk & ((value) << QSPI_SCRAMBKEY_KEY_Pos))</span></div>
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<div class="line"><a name="l00502"></a><span class="lineno"><a class="line" href="component_2qspi_8h.html#af89ee04ceeef535fbe3d6167c7ae040a"> 502</a></span> <span class="preprocessor">#define QSPI_SCRAMBKEY_MASK _U_(0xFFFFFFFF) </span></div>
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<div class="line"><a name="l00505"></a><span class="lineno"> 505</span> <span class="preprocessor">#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00506"></a><span class="lineno"><a class="line" href="structQspi.html"> 506</a></span> <span class="keyword">typedef</span> <span class="keyword">struct </span>{</div>
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<div class="line"><a name="l00507"></a><span class="lineno"><a class="line" href="structQspi.html#a036135899d8b56cb0da657f92fd7f33b"> 507</a></span>  __IO <a class="code" href="unionQSPI__CTRLA__Type.html">QSPI_CTRLA_Type</a> <a class="code" href="structQspi.html#a036135899d8b56cb0da657f92fd7f33b">CTRLA</a>; </div>
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<div class="line"><a name="l00508"></a><span class="lineno"><a class="line" href="structQspi.html#ad82456fa96981795d4d4dc4c737fe477"> 508</a></span>  __IO <a class="code" href="unionQSPI__CTRLB__Type.html">QSPI_CTRLB_Type</a> <a class="code" href="structQspi.html#ad82456fa96981795d4d4dc4c737fe477">CTRLB</a>; </div>
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<div class="line"><a name="l00509"></a><span class="lineno"><a class="line" href="structQspi.html#a8ffd9fd736eb1904a3bac44c74d38e86"> 509</a></span>  __IO <a class="code" href="unionQSPI__BAUD__Type.html">QSPI_BAUD_Type</a> <a class="code" href="structQspi.html#a8ffd9fd736eb1904a3bac44c74d38e86">BAUD</a>; </div>
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<div class="line"><a name="l00510"></a><span class="lineno"><a class="line" href="structQspi.html#a6575f26e79b6630b2f204db527ed6e02"> 510</a></span>  __I <a class="code" href="unionQSPI__RXDATA__Type.html">QSPI_RXDATA_Type</a> <a class="code" href="structQspi.html#a6575f26e79b6630b2f204db527ed6e02">RXDATA</a>; </div>
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<div class="line"><a name="l00511"></a><span class="lineno"><a class="line" href="structQspi.html#a337729f71a0cefe9e7846257d114ec33"> 511</a></span>  __O <a class="code" href="unionQSPI__TXDATA__Type.html">QSPI_TXDATA_Type</a> <a class="code" href="structQspi.html#a337729f71a0cefe9e7846257d114ec33">TXDATA</a>; </div>
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<div class="line"><a name="l00512"></a><span class="lineno"><a class="line" href="structQspi.html#ac87eada8e9fb313301f67cbc40c93eb3"> 512</a></span>  __IO <a class="code" href="unionQSPI__INTENCLR__Type.html">QSPI_INTENCLR_Type</a> <a class="code" href="structQspi.html#ac87eada8e9fb313301f67cbc40c93eb3">INTENCLR</a>; </div>
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<div class="line"><a name="l00513"></a><span class="lineno"><a class="line" href="structQspi.html#a87ffbe45eb4baaebac25849d60fec1b7"> 513</a></span>  __IO <a class="code" href="unionQSPI__INTENSET__Type.html">QSPI_INTENSET_Type</a> <a class="code" href="structQspi.html#a87ffbe45eb4baaebac25849d60fec1b7">INTENSET</a>; </div>
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<div class="line"><a name="l00514"></a><span class="lineno"><a class="line" href="structQspi.html#aec5e882df9b5ddf5a4398ab89ad4f70c"> 514</a></span>  __IO <a class="code" href="unionQSPI__INTFLAG__Type.html">QSPI_INTFLAG_Type</a> <a class="code" href="structQspi.html#aec5e882df9b5ddf5a4398ab89ad4f70c">INTFLAG</a>; </div>
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<div class="line"><a name="l00515"></a><span class="lineno"><a class="line" href="structQspi.html#a13817f23c84d3f9db5acaf239d6f4bf6"> 515</a></span>  __I <a class="code" href="unionQSPI__STATUS__Type.html">QSPI_STATUS_Type</a> <a class="code" href="structQspi.html#a13817f23c84d3f9db5acaf239d6f4bf6">STATUS</a>; </div>
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<div class="line"><a name="l00516"></a><span class="lineno"> 516</span>  <a class="code" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> Reserved1[0xC];</div>
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<div class="line"><a name="l00517"></a><span class="lineno"><a class="line" href="structQspi.html#a1ca888f8481c2f74f17202f86da43bb4"> 517</a></span>  __IO <a class="code" href="unionQSPI__INSTRADDR__Type.html">QSPI_INSTRADDR_Type</a> <a class="code" href="structQspi.html#a1ca888f8481c2f74f17202f86da43bb4">INSTRADDR</a>; </div>
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<div class="line"><a name="l00518"></a><span class="lineno"><a class="line" href="structQspi.html#a028aaca0f980cadda025f73b78702bdd"> 518</a></span>  __IO <a class="code" href="unionQSPI__INSTRCTRL__Type.html">QSPI_INSTRCTRL_Type</a> <a class="code" href="structQspi.html#a028aaca0f980cadda025f73b78702bdd">INSTRCTRL</a>; </div>
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<div class="line"><a name="l00519"></a><span class="lineno"><a class="line" href="structQspi.html#a4caceb6a280cbde82946b99189c08438"> 519</a></span>  __IO <a class="code" href="unionQSPI__INSTRFRAME__Type.html">QSPI_INSTRFRAME_Type</a> <a class="code" href="structQspi.html#a4caceb6a280cbde82946b99189c08438">INSTRFRAME</a>; </div>
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<div class="line"><a name="l00520"></a><span class="lineno"> 520</span>  <a class="code" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> Reserved2[0x4];</div>
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<div class="line"><a name="l00521"></a><span class="lineno"><a class="line" href="structQspi.html#ad55fe0189a3683730f5cc1b3db933dec"> 521</a></span>  __IO <a class="code" href="unionQSPI__SCRAMBCTRL__Type.html">QSPI_SCRAMBCTRL_Type</a> <a class="code" href="structQspi.html#ad55fe0189a3683730f5cc1b3db933dec">SCRAMBCTRL</a>; </div>
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<div class="line"><a name="l00522"></a><span class="lineno"><a class="line" href="structQspi.html#a1c55f219ca8463e412b8a92bd8250747"> 522</a></span>  __O <a class="code" href="unionQSPI__SCRAMBKEY__Type.html">QSPI_SCRAMBKEY_Type</a> <a class="code" href="structQspi.html#a1c55f219ca8463e412b8a92bd8250747">SCRAMBKEY</a>; </div>
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<div class="line"><a name="l00523"></a><span class="lineno"> 523</span> } <a class="code" href="structQspi.html">Qspi</a>;</div>
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<div class="line"><a name="l00524"></a><span class="lineno"> 524</span> <span class="preprocessor">#endif </span><span class="comment">/* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00525"></a><span class="lineno"> 525</span>  </div>
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<div class="line"><a name="l00528"></a><span class="lineno"> 528</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_QSPI_COMPONENT_ */</span><span class="preprocessor"></span></div>
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</div><!-- fragment --></div><!-- contents -->
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<div class="ttc" id="aunionQSPI__INTFLAG__Type_html_a68c37907555a5b16ed601d7f40801f3c"><div class="ttname"><a href="unionQSPI__INTFLAG__Type.html#a68c37907555a5b16ed601d7f40801f3c">QSPI_INTFLAG_Type::INSTREND</a></div><div class="ttdeci">__I uint32_t INSTREND</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00288">qspi.h:288</a></div></div>
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<div class="ttc" id="aunionQSPI__STATUS__Type_html_a3f0852a86d19cdde5a080aa904ed1263"><div class="ttname"><a href="unionQSPI__STATUS__Type.html#a3f0852a86d19cdde5a080aa904ed1263">QSPI_STATUS_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00322">qspi.h:322</a></div></div>
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<div class="ttc" id="aunionQSPI__RXDATA__Type_html"><div class="ttname"><a href="unionQSPI__RXDATA__Type.html">QSPI_RXDATA_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00171">qspi.h:171</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLB__Type_html_a6822f70c8971f01fc5f43423df00728d"><div class="ttname"><a href="unionQSPI__CTRLB__Type.html#a6822f70c8971f01fc5f43423df00728d">QSPI_CTRLB_Type::WDRBT</a></div><div class="ttdeci">uint32_t WDRBT</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00073">qspi.h:73</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENSET__Type_html_a0b6a000f84f497776d67f13756937ee1"><div class="ttname"><a href="unionQSPI__INTENSET__Type.html#a0b6a000f84f497776d67f13756937ee1">QSPI_INTENSET_Type::ERROR</a></div><div class="ttdeci">uint32_t ERROR</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00249">qspi.h:249</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENSET__Type_html_a54e6cfe0fded456c1f115964c22ee5a4"><div class="ttname"><a href="unionQSPI__INTENSET__Type.html#a54e6cfe0fded456c1f115964c22ee5a4">QSPI_INTENSET_Type::CSRISE</a></div><div class="ttdeci">uint32_t CSRISE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00251">qspi.h:251</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html_aa3f3bde47157054c4abb8ef35bfe9722"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html#aa3f3bde47157054c4abb8ef35bfe9722">QSPI_INSTRFRAME_Type::ADDRLEN</a></div><div class="ttdeci">uint32_t ADDRLEN</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00388">qspi.h:388</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENCLR__Type_html"><div class="ttname"><a href="unionQSPI__INTENCLR__Type.html">QSPI_INTENCLR_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00209">qspi.h:209</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html_a5a5d3938a338789c3eb040dccb632344"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html#a5a5d3938a338789c3eb040dccb632344">QSPI_INSTRFRAME_Type::ADDREN</a></div><div class="ttdeci">uint32_t ADDREN</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00384">qspi.h:384</a></div></div>
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<div class="ttc" id="aunionQSPI__INTFLAG__Type_html_ae6c22aa80c54b555f339b289aa701ac4"><div class="ttname"><a href="unionQSPI__INTFLAG__Type.html#ae6c22aa80c54b555f339b289aa701ac4">QSPI_INTFLAG_Type::CSRISE</a></div><div class="ttdeci">__I uint32_t CSRISE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00286">qspi.h:286</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLB__Type_html_a40b9f8126928b0a8cc5daa6402d10de8"><div class="ttname"><a href="unionQSPI__CTRLB__Type.html#a40b9f8126928b0a8cc5daa6402d10de8">QSPI_CTRLB_Type::MODE</a></div><div class="ttdeci">uint32_t MODE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00071">qspi.h:71</a></div></div>
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<div class="ttc" id="astructQspi_html_a87ffbe45eb4baaebac25849d60fec1b7"><div class="ttname"><a href="structQspi.html#a87ffbe45eb4baaebac25849d60fec1b7">Qspi::INTENSET</a></div><div class="ttdeci">__IO QSPI_INTENSET_Type INTENSET</div><div class="ttdoc">Offset: 0x18 (R/W 32) Interrupt Enable Set.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00513">qspi.h:513</a></div></div>
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<div class="ttc" id="astructQspi_html_a036135899d8b56cb0da657f92fd7f33b"><div class="ttname"><a href="structQspi.html#a036135899d8b56cb0da657f92fd7f33b">Qspi::CTRLA</a></div><div class="ttdeci">__IO QSPI_CTRLA_Type CTRLA</div><div class="ttdoc">Offset: 0x00 (R/W 32) Control A.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00507">qspi.h:507</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLA__Type_html"><div class="ttname"><a href="unionQSPI__CTRLA__Type.html">QSPI_CTRLA_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00044">qspi.h:44</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html_af4e9717d15fbd6daa759da9ab6308641"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html#af4e9717d15fbd6daa759da9ab6308641">QSPI_INSTRFRAME_Type::WIDTH</a></div><div class="ttdeci">uint32_t WIDTH</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00381">qspi.h:381</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENCLR__Type_html_a2fd40dd28ffb06979281df6f416b1381"><div class="ttname"><a href="unionQSPI__INTENCLR__Type.html#a2fd40dd28ffb06979281df6f416b1381">QSPI_INTENCLR_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00221">qspi.h:221</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENCLR__Type_html_a8d6b46846898fd220fe13afd575e2cdc"><div class="ttname"><a href="unionQSPI__INTENCLR__Type.html#a8d6b46846898fd220fe13afd575e2cdc">QSPI_INTENCLR_Type::RXC</a></div><div class="ttdeci">uint32_t RXC</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00211">qspi.h:211</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENCLR__Type_html_ab4105436857762b9a2386aacdeed5bf5"><div class="ttname"><a href="unionQSPI__INTENCLR__Type.html#ab4105436857762b9a2386aacdeed5bf5">QSPI_INTENCLR_Type::TXC</a></div><div class="ttdeci">uint32_t TXC</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00213">qspi.h:213</a></div></div>
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<div class="ttc" id="astructQspi_html_a4caceb6a280cbde82946b99189c08438"><div class="ttname"><a href="structQspi.html#a4caceb6a280cbde82946b99189c08438">Qspi::INSTRFRAME</a></div><div class="ttdeci">__IO QSPI_INSTRFRAME_Type INSTRFRAME</div><div class="ttdoc">Offset: 0x38 (R/W 32) Instruction Frame.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00519">qspi.h:519</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENCLR__Type_html_a1487ebc330c7c34c3e8cfe2d40d83866"><div class="ttname"><a href="unionQSPI__INTENCLR__Type.html#a1487ebc330c7c34c3e8cfe2d40d83866">QSPI_INTENCLR_Type::INSTREND</a></div><div class="ttdeci">uint32_t INSTREND</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00218">qspi.h:218</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENCLR__Type_html_af93a9ea2597954d114e08eb276585504"><div class="ttname"><a href="unionQSPI__INTENCLR__Type.html#af93a9ea2597954d114e08eb276585504">QSPI_INTENCLR_Type::ERROR</a></div><div class="ttdeci">uint32_t ERROR</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00214">qspi.h:214</a></div></div>
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<div class="ttc" id="aunionQSPI__SCRAMBKEY__Type_html"><div class="ttname"><a href="unionQSPI__SCRAMBKEY__Type.html">QSPI_SCRAMBKEY_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00488">qspi.h:488</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLB__Type_html_a2f38f8719f25fec2aded949490118061"><div class="ttname"><a href="unionQSPI__CTRLB__Type.html#a2f38f8719f25fec2aded949490118061">QSPI_CTRLB_Type::CSMODE</a></div><div class="ttdeci">uint32_t CSMODE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00075">qspi.h:75</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENSET__Type_html_a1ecfd772eb0b7fd8b56745bde327edee"><div class="ttname"><a href="unionQSPI__INTENSET__Type.html#a1ecfd772eb0b7fd8b56745bde327edee">QSPI_INTENSET_Type::TXC</a></div><div class="ttdeci">uint32_t TXC</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00248">qspi.h:248</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENSET__Type_html"><div class="ttname"><a href="unionQSPI__INTENSET__Type.html">QSPI_INTENSET_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00244">qspi.h:244</a></div></div>
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<div class="ttc" id="astructQspi_html_ac87eada8e9fb313301f67cbc40c93eb3"><div class="ttname"><a href="structQspi.html#ac87eada8e9fb313301f67cbc40c93eb3">Qspi::INTENCLR</a></div><div class="ttdeci">__IO QSPI_INTENCLR_Type INTENCLR</div><div class="ttdoc">Offset: 0x14 (R/W 32) Interrupt Enable Clear.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00512">qspi.h:512</a></div></div>
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<div class="ttc" id="aunionQSPI__STATUS__Type_html_a8118ba918187482b90661ade08ff8cd3"><div class="ttname"><a href="unionQSPI__STATUS__Type.html#a8118ba918187482b90661ade08ff8cd3">QSPI_STATUS_Type::CSSTATUS</a></div><div class="ttdeci">uint32_t CSSTATUS</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00319">qspi.h:319</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENSET__Type_html_abfad9d948c90044fcaf367e3499301a1"><div class="ttname"><a href="unionQSPI__INTENSET__Type.html#abfad9d948c90044fcaf367e3499301a1">QSPI_INTENSET_Type::DRE</a></div><div class="ttdeci">uint32_t DRE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00247">qspi.h:247</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html_aad5648a1261cee34645a8284b55b310e"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html#aad5648a1261cee34645a8284b55b310e">QSPI_INSTRFRAME_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00396">qspi.h:396</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRADDR__Type_html"><div class="ttname"><a href="unionQSPI__INSTRADDR__Type.html">QSPI_INSTRADDR_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00337">qspi.h:337</a></div></div>
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<div class="ttc" id="aunionQSPI__INTFLAG__Type_html_a0f54f299c07c5df0f9f299b832d662eb"><div class="ttname"><a href="unionQSPI__INTFLAG__Type.html#a0f54f299c07c5df0f9f299b832d662eb">QSPI_INTFLAG_Type::ERROR</a></div><div class="ttdeci">__I uint32_t ERROR</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00284">qspi.h:284</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html_a6c27c6138d6479df2cd8494513a381c0"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html#a6c27c6138d6479df2cd8494513a381c0">QSPI_INSTRFRAME_Type::OPTCODEEN</a></div><div class="ttdeci">uint32_t OPTCODEEN</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00385">qspi.h:385</a></div></div>
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<div class="ttc" id="astructQspi_html_a6575f26e79b6630b2f204db527ed6e02"><div class="ttname"><a href="structQspi.html#a6575f26e79b6630b2f204db527ed6e02">Qspi::RXDATA</a></div><div class="ttdeci">__I QSPI_RXDATA_Type RXDATA</div><div class="ttdoc">Offset: 0x0C (R/ 32) Receive Data.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00510">qspi.h:510</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLB__Type_html_ab2963d007c9dc7aa23eea3209f519a13"><div class="ttname"><a href="unionQSPI__CTRLB__Type.html#ab2963d007c9dc7aa23eea3209f519a13">QSPI_CTRLB_Type::DLYBCT</a></div><div class="ttdeci">uint32_t DLYBCT</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00079">qspi.h:79</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html">QSPI_INSTRFRAME_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00379">qspi.h:379</a></div></div>
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<div class="ttc" id="aunionQSPI__INTFLAG__Type_html_a1f3e1e85e417bf929650b0f01ef37c80"><div class="ttname"><a href="unionQSPI__INTFLAG__Type.html#a1f3e1e85e417bf929650b0f01ef37c80">QSPI_INTFLAG_Type::TXC</a></div><div class="ttdeci">__I uint32_t TXC</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00283">qspi.h:283</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLB__Type_html_aed3b90e61dcef23674f2b060fc6ac7a0"><div class="ttname"><a href="unionQSPI__CTRLB__Type.html#aed3b90e61dcef23674f2b060fc6ac7a0">QSPI_CTRLB_Type::DLYCS</a></div><div class="ttdeci">uint32_t DLYCS</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00080">qspi.h:80</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html_ab97b3b1aa98ff1c17a5269a3bcf04774"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html#ab97b3b1aa98ff1c17a5269a3bcf04774">QSPI_INSTRFRAME_Type::TFRTYPE</a></div><div class="ttdeci">uint32_t TFRTYPE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00390">qspi.h:390</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html_a7c66c0225ebd04b6fe659b8ac437feb1"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html#a7c66c0225ebd04b6fe659b8ac437feb1">QSPI_INSTRFRAME_Type::OPTCODELEN</a></div><div class="ttdeci">uint32_t OPTCODELEN</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00387">qspi.h:387</a></div></div>
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<div class="ttc" id="aunionQSPI__RXDATA__Type_html_af8af6e25ff115308ebeb9bab37848455"><div class="ttname"><a href="unionQSPI__RXDATA__Type.html#af8af6e25ff115308ebeb9bab37848455">QSPI_RXDATA_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00176">qspi.h:176</a></div></div>
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<div class="ttc" id="aunionQSPI__RXDATA__Type_html_ac60e9581b211e70b39ad4ab1f6566049"><div class="ttname"><a href="unionQSPI__RXDATA__Type.html#ac60e9581b211e70b39ad4ab1f6566049">QSPI_RXDATA_Type::DATA</a></div><div class="ttdeci">uint32_t DATA</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00173">qspi.h:173</a></div></div>
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<div class="ttc" id="aunionQSPI__BAUD__Type_html_a43b94ea36888e3dc000f4303fc308a84"><div class="ttname"><a href="unionQSPI__BAUD__Type.html#a43b94ea36888e3dc000f4303fc308a84">QSPI_BAUD_Type::BAUD</a></div><div class="ttdeci">uint32_t BAUD</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00146">qspi.h:146</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLB__Type_html_a5d4f4af7969a6eff3fe6db9c0eff9601"><div class="ttname"><a href="unionQSPI__CTRLB__Type.html#a5d4f4af7969a6eff3fe6db9c0eff9601">QSPI_CTRLB_Type::DATALEN</a></div><div class="ttdeci">uint32_t DATALEN</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00077">qspi.h:77</a></div></div>
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<div class="ttc" id="astructQspi_html_a1ca888f8481c2f74f17202f86da43bb4"><div class="ttname"><a href="structQspi.html#a1ca888f8481c2f74f17202f86da43bb4">Qspi::INSTRADDR</a></div><div class="ttdeci">__IO QSPI_INSTRADDR_Type INSTRADDR</div><div class="ttdoc">Offset: 0x30 (R/W 32) Instruction Address.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00517">qspi.h:517</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html_aba0ceb37c44ea2b53a216333ec6d4b09"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html#aba0ceb37c44ea2b53a216333ec6d4b09">QSPI_INSTRFRAME_Type::INSTREN</a></div><div class="ttdeci">uint32_t INSTREN</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00383">qspi.h:383</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRADDR__Type_html_aeaa5706347b9a351be7d8487eb034f9c"><div class="ttname"><a href="unionQSPI__INSTRADDR__Type.html#aeaa5706347b9a351be7d8487eb034f9c">QSPI_INSTRADDR_Type::ADDR</a></div><div class="ttdeci">uint32_t ADDR</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00339">qspi.h:339</a></div></div>
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<div class="ttc" id="aunionQSPI__INTFLAG__Type_html"><div class="ttname"><a href="unionQSPI__INTFLAG__Type.html">QSPI_INTFLAG_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00279">qspi.h:279</a></div></div>
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<div class="ttc" id="aunionQSPI__STATUS__Type_html"><div class="ttname"><a href="unionQSPI__STATUS__Type.html">QSPI_STATUS_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00314">qspi.h:314</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html_a1470de99b6c195d41fd42bd265483e07"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html#a1470de99b6c195d41fd42bd265483e07">QSPI_INSTRFRAME_Type::DDREN</a></div><div class="ttdeci">uint32_t DDREN</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00392">qspi.h:392</a></div></div>
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<div class="ttc" id="astructQspi_html_a337729f71a0cefe9e7846257d114ec33"><div class="ttname"><a href="structQspi.html#a337729f71a0cefe9e7846257d114ec33">Qspi::TXDATA</a></div><div class="ttdeci">__O QSPI_TXDATA_Type TXDATA</div><div class="ttdoc">Offset: 0x10 ( /W 32) Transmit Data.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00511">qspi.h:511</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLA__Type_html_ab372145e424a0b9f1642f60db196a22e"><div class="ttname"><a href="unionQSPI__CTRLA__Type.html#ab372145e424a0b9f1642f60db196a22e">QSPI_CTRLA_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00052">qspi.h:52</a></div></div>
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<div class="ttc" id="aunionQSPI__TXDATA__Type_html_a4a243118dc07f06e2fe435281b31631e"><div class="ttname"><a href="unionQSPI__TXDATA__Type.html#a4a243118dc07f06e2fe435281b31631e">QSPI_TXDATA_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00195">qspi.h:195</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLA__Type_html_aaaf46f72299c34d5891124f614041b1d"><div class="ttname"><a href="unionQSPI__CTRLA__Type.html#aaaf46f72299c34d5891124f614041b1d">QSPI_CTRLA_Type::SWRST</a></div><div class="ttdeci">uint32_t SWRST</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00046">qspi.h:46</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLB__Type_html"><div class="ttname"><a href="unionQSPI__CTRLB__Type.html">QSPI_CTRLB_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00069">qspi.h:69</a></div></div>
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<div class="ttc" id="aunionQSPI__SCRAMBCTRL__Type_html_abbdc62da58889b56a0046e387dcc61d9"><div class="ttname"><a href="unionQSPI__SCRAMBCTRL__Type.html#abbdc62da58889b56a0046e387dcc61d9">QSPI_SCRAMBCTRL_Type::RANDOMDIS</a></div><div class="ttdeci">uint32_t RANDOMDIS</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00470">qspi.h:470</a></div></div>
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<div class="ttc" id="astructQspi_html_a8ffd9fd736eb1904a3bac44c74d38e86"><div class="ttname"><a href="structQspi.html#a8ffd9fd736eb1904a3bac44c74d38e86">Qspi::BAUD</a></div><div class="ttdeci">__IO QSPI_BAUD_Type BAUD</div><div class="ttdoc">Offset: 0x08 (R/W 32) Baud Rate.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00509">qspi.h:509</a></div></div>
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<div class="ttc" id="aunionQSPI__BAUD__Type_html"><div class="ttname"><a href="unionQSPI__BAUD__Type.html">QSPI_BAUD_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00141">qspi.h:141</a></div></div>
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<div class="ttc" id="aunionQSPI__INTFLAG__Type_html_a307d69bd98ee2ae1e1dd069007fd4e4e"><div class="ttname"><a href="unionQSPI__INTFLAG__Type.html#a307d69bd98ee2ae1e1dd069007fd4e4e">QSPI_INTFLAG_Type::DRE</a></div><div class="ttdeci">__I uint32_t DRE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00282">qspi.h:282</a></div></div>
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<div class="ttc" id="aunionQSPI__TXDATA__Type_html"><div class="ttname"><a href="unionQSPI__TXDATA__Type.html">QSPI_TXDATA_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00190">qspi.h:190</a></div></div>
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<div class="ttc" id="aunionQSPI__STATUS__Type_html_ad0f2f07cfdeb7f190fdae3b9ec102f67"><div class="ttname"><a href="unionQSPI__STATUS__Type.html#ad0f2f07cfdeb7f190fdae3b9ec102f67">QSPI_STATUS_Type::ENABLE</a></div><div class="ttdeci">uint32_t ENABLE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00317">qspi.h:317</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLB__Type_html_a35329ec65e15a45e4024ff0a98e67264"><div class="ttname"><a href="unionQSPI__CTRLB__Type.html#a35329ec65e15a45e4024ff0a98e67264">QSPI_CTRLB_Type::LOOPEN</a></div><div class="ttdeci">uint32_t LOOPEN</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00072">qspi.h:72</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLA__Type_html_ae872a6aac9d29d5685228a3adfc8d04c"><div class="ttname"><a href="unionQSPI__CTRLA__Type.html#ae872a6aac9d29d5685228a3adfc8d04c">QSPI_CTRLA_Type::ENABLE</a></div><div class="ttdeci">uint32_t ENABLE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00047">qspi.h:47</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLB__Type_html_a1d43cda21360188eb04fa9a339aa544c"><div class="ttname"><a href="unionQSPI__CTRLB__Type.html#a1d43cda21360188eb04fa9a339aa544c">QSPI_CTRLB_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00082">qspi.h:82</a></div></div>
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<div class="ttc" id="astructQspi_html_a028aaca0f980cadda025f73b78702bdd"><div class="ttname"><a href="structQspi.html#a028aaca0f980cadda025f73b78702bdd">Qspi::INSTRCTRL</a></div><div class="ttdeci">__IO QSPI_INSTRCTRL_Type INSTRCTRL</div><div class="ttdoc">Offset: 0x34 (R/W 32) Instruction Code.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00518">qspi.h:518</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLA__Type_html_ae7ec0782952fbc3348b26e0560f08845"><div class="ttname"><a href="unionQSPI__CTRLA__Type.html#ae7ec0782952fbc3348b26e0560f08845">QSPI_CTRLA_Type::LASTXFER</a></div><div class="ttdeci">uint32_t LASTXFER</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00049">qspi.h:49</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html_abbcb827971433af94254a9c7eb9c11bd"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html#abbcb827971433af94254a9c7eb9c11bd">QSPI_INSTRFRAME_Type::CRMODE</a></div><div class="ttdeci">uint32_t CRMODE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00391">qspi.h:391</a></div></div>
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<div class="ttc" id="aunionQSPI__BAUD__Type_html_a0fc65a43295c1df795b6e794b8c04d80"><div class="ttname"><a href="unionQSPI__BAUD__Type.html#a0fc65a43295c1df795b6e794b8c04d80">QSPI_BAUD_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00150">qspi.h:150</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENSET__Type_html_a3eb8216a8ed325db6a6c8a748150717a"><div class="ttname"><a href="unionQSPI__INTENSET__Type.html#a3eb8216a8ed325db6a6c8a748150717a">QSPI_INTENSET_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00256">qspi.h:256</a></div></div>
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<div class="ttc" id="astructQspi_html_ad82456fa96981795d4d4dc4c737fe477"><div class="ttname"><a href="structQspi.html#ad82456fa96981795d4d4dc4c737fe477">Qspi::CTRLB</a></div><div class="ttdeci">__IO QSPI_CTRLB_Type CTRLB</div><div class="ttdoc">Offset: 0x04 (R/W 32) Control B.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00508">qspi.h:508</a></div></div>
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<div class="ttc" id="aunionQSPI__SCRAMBKEY__Type_html_ae6a5ec1d96755202750e371951cd3c5f"><div class="ttname"><a href="unionQSPI__SCRAMBKEY__Type.html#ae6a5ec1d96755202750e371951cd3c5f">QSPI_SCRAMBKEY_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00492">qspi.h:492</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRADDR__Type_html_affbc8d4e4c51354523c0fb7088403eb0"><div class="ttname"><a href="unionQSPI__INSTRADDR__Type.html#affbc8d4e4c51354523c0fb7088403eb0">QSPI_INSTRADDR_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00341">qspi.h:341</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENSET__Type_html_a7a0e65ab51f1e2a81aea30ba5773900a"><div class="ttname"><a href="unionQSPI__INTENSET__Type.html#a7a0e65ab51f1e2a81aea30ba5773900a">QSPI_INTENSET_Type::RXC</a></div><div class="ttdeci">uint32_t RXC</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00246">qspi.h:246</a></div></div>
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<div class="ttc" id="aunionQSPI__CTRLB__Type_html_a9e1fb6cb01d99e5e2926afd364ae7622"><div class="ttname"><a href="unionQSPI__CTRLB__Type.html#a9e1fb6cb01d99e5e2926afd364ae7622">QSPI_CTRLB_Type::SMEMREG</a></div><div class="ttdeci">uint32_t SMEMREG</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00074">qspi.h:74</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRCTRL__Type_html"><div class="ttname"><a href="unionQSPI__INSTRCTRL__Type.html">QSPI_INSTRCTRL_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00355">qspi.h:355</a></div></div>
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<div class="ttc" id="astructQspi_html_a1c55f219ca8463e412b8a92bd8250747"><div class="ttname"><a href="structQspi.html#a1c55f219ca8463e412b8a92bd8250747">Qspi::SCRAMBKEY</a></div><div class="ttdeci">__O QSPI_SCRAMBKEY_Type SCRAMBKEY</div><div class="ttdoc">Offset: 0x44 ( /W 32) Scrambling Key.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00522">qspi.h:522</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html_aa5f775fcab7e4c40869e065951f95291"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html#aa5f775fcab7e4c40869e065951f95291">QSPI_INSTRFRAME_Type::DUMMYLEN</a></div><div class="ttdeci">uint32_t DUMMYLEN</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00393">qspi.h:393</a></div></div>
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<div class="ttc" id="aunionQSPI__BAUD__Type_html_a1fff893bd4e78a90f2ed61a48132173f"><div class="ttname"><a href="unionQSPI__BAUD__Type.html#a1fff893bd4e78a90f2ed61a48132173f">QSPI_BAUD_Type::CPOL</a></div><div class="ttdeci">uint32_t CPOL</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00143">qspi.h:143</a></div></div>
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<div class="ttc" id="aunionQSPI__BAUD__Type_html_ae4ea5e341e2d5d447848963b97fb1f07"><div class="ttname"><a href="unionQSPI__BAUD__Type.html#ae4ea5e341e2d5d447848963b97fb1f07">QSPI_BAUD_Type::DLYBS</a></div><div class="ttdeci">uint32_t DLYBS</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00147">qspi.h:147</a></div></div>
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<div class="ttc" id="astructQspi_html_ad55fe0189a3683730f5cc1b3db933dec"><div class="ttname"><a href="structQspi.html#ad55fe0189a3683730f5cc1b3db933dec">Qspi::SCRAMBCTRL</a></div><div class="ttdeci">__IO QSPI_SCRAMBCTRL_Type SCRAMBCTRL</div><div class="ttdoc">Offset: 0x40 (R/W 32) Scrambling Mode.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00521">qspi.h:521</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRCTRL__Type_html_a4cdbcc3b434cd974e65fcc699405001d"><div class="ttname"><a href="unionQSPI__INSTRCTRL__Type.html#a4cdbcc3b434cd974e65fcc699405001d">QSPI_INSTRCTRL_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00362">qspi.h:362</a></div></div>
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<div class="ttc" id="astructQspi_html_a13817f23c84d3f9db5acaf239d6f4bf6"><div class="ttname"><a href="structQspi.html#a13817f23c84d3f9db5acaf239d6f4bf6">Qspi::STATUS</a></div><div class="ttdeci">__I QSPI_STATUS_Type STATUS</div><div class="ttdoc">Offset: 0x20 (R/ 32) Status Register.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00515">qspi.h:515</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENCLR__Type_html_a43364fbb0a002e6ec67d6f4add99264c"><div class="ttname"><a href="unionQSPI__INTENCLR__Type.html#a43364fbb0a002e6ec67d6f4add99264c">QSPI_INTENCLR_Type::DRE</a></div><div class="ttdeci">uint32_t DRE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00212">qspi.h:212</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENCLR__Type_html_af7fd69f6df15870be2385284008aea70"><div class="ttname"><a href="unionQSPI__INTENCLR__Type.html#af7fd69f6df15870be2385284008aea70">QSPI_INTENCLR_Type::CSRISE</a></div><div class="ttdeci">uint32_t CSRISE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00216">qspi.h:216</a></div></div>
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<div class="ttc" id="aunionQSPI__INTFLAG__Type_html_a80d501d18d0dfa44ed1dc4a0d3cb5117"><div class="ttname"><a href="unionQSPI__INTFLAG__Type.html#a80d501d18d0dfa44ed1dc4a0d3cb5117">QSPI_INTFLAG_Type::RXC</a></div><div class="ttdeci">__I uint32_t RXC</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00281">qspi.h:281</a></div></div>
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<div class="ttc" id="aunionQSPI__SCRAMBCTRL__Type_html_ad5dcc58c8e20dc1c93c9275502c3d09d"><div class="ttname"><a href="unionQSPI__SCRAMBCTRL__Type.html#ad5dcc58c8e20dc1c93c9275502c3d09d">QSPI_SCRAMBCTRL_Type::ENABLE</a></div><div class="ttdeci">uint32_t ENABLE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00469">qspi.h:469</a></div></div>
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<div class="ttc" id="astructQspi_html"><div class="ttname"><a href="structQspi.html">Qspi</a></div><div class="ttdoc">QSPI APB hardware registers.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00506">qspi.h:506</a></div></div>
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<div class="ttc" id="aunionQSPI__SCRAMBCTRL__Type_html"><div class="ttname"><a href="unionQSPI__SCRAMBCTRL__Type.html">QSPI_SCRAMBCTRL_Type</a></div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00467">qspi.h:467</a></div></div>
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<div class="ttc" id="asame54n19a_8h_html_a0d957f1433aaf5d70e4dc2b68288442d"><div class="ttname"><a href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a></div><div class="ttdeci">volatile const uint8_t RoReg8</div><div class="ttdef"><b>Definition:</b> <a href="same54n19a_8h_source.html#l00053">same54n19a.h:53</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRCTRL__Type_html_a1a7769aa0471f5cef5a1cc7a45953783"><div class="ttname"><a href="unionQSPI__INSTRCTRL__Type.html#a1a7769aa0471f5cef5a1cc7a45953783">QSPI_INSTRCTRL_Type::OPTCODE</a></div><div class="ttdeci">uint32_t OPTCODE</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00359">qspi.h:359</a></div></div>
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<div class="ttc" id="aunionQSPI__BAUD__Type_html_a9ce4956564c40a25a9df46c5954e4f6f"><div class="ttname"><a href="unionQSPI__BAUD__Type.html#a9ce4956564c40a25a9df46c5954e4f6f">QSPI_BAUD_Type::CPHA</a></div><div class="ttdeci">uint32_t CPHA</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00144">qspi.h:144</a></div></div>
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<div class="ttc" id="aunionQSPI__TXDATA__Type_html_a9bee83ef09844cc99cb5bac60e32e0c9"><div class="ttname"><a href="unionQSPI__TXDATA__Type.html#a9bee83ef09844cc99cb5bac60e32e0c9">QSPI_TXDATA_Type::DATA</a></div><div class="ttdeci">uint32_t DATA</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00192">qspi.h:192</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRFRAME__Type_html_a7b56cbadd3b07a83807a60d0f84b7010"><div class="ttname"><a href="unionQSPI__INSTRFRAME__Type.html#a7b56cbadd3b07a83807a60d0f84b7010">QSPI_INSTRFRAME_Type::DATAEN</a></div><div class="ttdeci">uint32_t DATAEN</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00386">qspi.h:386</a></div></div>
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<div class="ttc" id="aunionQSPI__SCRAMBCTRL__Type_html_a052962dacf4c4eec5acb9812e9e84c9a"><div class="ttname"><a href="unionQSPI__SCRAMBCTRL__Type.html#a052962dacf4c4eec5acb9812e9e84c9a">QSPI_SCRAMBCTRL_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00473">qspi.h:473</a></div></div>
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<div class="ttc" id="astructQspi_html_aec5e882df9b5ddf5a4398ab89ad4f70c"><div class="ttname"><a href="structQspi.html#aec5e882df9b5ddf5a4398ab89ad4f70c">Qspi::INTFLAG</a></div><div class="ttdeci">__IO QSPI_INTFLAG_Type INTFLAG</div><div class="ttdoc">Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear.</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00514">qspi.h:514</a></div></div>
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<div class="ttc" id="aunionQSPI__INTFLAG__Type_html_a2f7d3aecf7c0fd69f725ce28acca5dae"><div class="ttname"><a href="unionQSPI__INTFLAG__Type.html#a2f7d3aecf7c0fd69f725ce28acca5dae">QSPI_INTFLAG_Type::reg</a></div><div class="ttdeci">uint32_t reg</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00291">qspi.h:291</a></div></div>
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<div class="ttc" id="aunionQSPI__SCRAMBKEY__Type_html_a3ad1c3c8a178b733ac83375faa3f9ab4"><div class="ttname"><a href="unionQSPI__SCRAMBKEY__Type.html#a3ad1c3c8a178b733ac83375faa3f9ab4">QSPI_SCRAMBKEY_Type::KEY</a></div><div class="ttdeci">uint32_t KEY</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00490">qspi.h:490</a></div></div>
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<div class="ttc" id="aunionQSPI__INTFLAG__Type_html_a3923a82733e6127e615da2dd8f593ac9"><div class="ttname"><a href="unionQSPI__INTFLAG__Type.html#a3923a82733e6127e615da2dd8f593ac9">QSPI_INTFLAG_Type::uint32_t</a></div><div class="ttdeci">__I uint32_t</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00285">qspi.h:285</a></div></div>
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<div class="ttc" id="aunionQSPI__INTENSET__Type_html_ad00a5f3343ee143b50a8000c879ca109"><div class="ttname"><a href="unionQSPI__INTENSET__Type.html#ad00a5f3343ee143b50a8000c879ca109">QSPI_INTENSET_Type::INSTREND</a></div><div class="ttdeci">uint32_t INSTREND</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00253">qspi.h:253</a></div></div>
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<div class="ttc" id="aunionQSPI__INSTRCTRL__Type_html_a356bb6a5c99c9d96c896d7000e61bdc3"><div class="ttname"><a href="unionQSPI__INSTRCTRL__Type.html#a356bb6a5c99c9d96c896d7000e61bdc3">QSPI_INSTRCTRL_Type::INSTR</a></div><div class="ttdeci">uint32_t INSTR</div><div class="ttdef"><b>Definition:</b> <a href="component_2qspi_8h_source.html#l00357">qspi.h:357</a></div></div>
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