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299 lines
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<a href="#define-members">Macros</a> </div>
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<div class="title">can0.h File Reference</div> </div>
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</div><!--header-->
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<div class="contents">
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<p>Instance description for CAN0.
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<a href="#details">More...</a></p>
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<p><a href="can0_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a449efb29c6abed35e2aa0e93d14e84ad"><td class="memItemLeft" align="right" valign="top"><a id="a449efb29c6abed35e2aa0e93d14e84ad"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a449efb29c6abed35e2aa0e93d14e84ad">REG_CAN0_CREL</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x42000000UL)</td></tr>
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<tr class="memdesc:a449efb29c6abed35e2aa0e93d14e84ad"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Core Release <br /></td></tr>
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<tr class="separator:a449efb29c6abed35e2aa0e93d14e84ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af85411a25615dd0b3831fe74a5173e17"><td class="memItemLeft" align="right" valign="top"><a id="af85411a25615dd0b3831fe74a5173e17"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#af85411a25615dd0b3831fe74a5173e17">REG_CAN0_ENDN</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x42000004UL)</td></tr>
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<tr class="memdesc:af85411a25615dd0b3831fe74a5173e17"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Endian <br /></td></tr>
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<tr class="separator:af85411a25615dd0b3831fe74a5173e17"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac595795560be949de07d82f41764a319"><td class="memItemLeft" align="right" valign="top"><a id="ac595795560be949de07d82f41764a319"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#ac595795560be949de07d82f41764a319">REG_CAN0_MRCFG</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000008UL)</td></tr>
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<tr class="memdesc:ac595795560be949de07d82f41764a319"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Message RAM Configuration <br /></td></tr>
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<tr class="separator:ac595795560be949de07d82f41764a319"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abb0e5f859a165cc9a373511623420f8c"><td class="memItemLeft" align="right" valign="top"><a id="abb0e5f859a165cc9a373511623420f8c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#abb0e5f859a165cc9a373511623420f8c">REG_CAN0_DBTP</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4200000CUL)</td></tr>
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<tr class="memdesc:abb0e5f859a165cc9a373511623420f8c"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Fast Bit Timing and Prescaler <br /></td></tr>
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<tr class="separator:abb0e5f859a165cc9a373511623420f8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae029a3656c7e567002eb4fbc936f209d"><td class="memItemLeft" align="right" valign="top"><a id="ae029a3656c7e567002eb4fbc936f209d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#ae029a3656c7e567002eb4fbc936f209d">REG_CAN0_TEST</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000010UL)</td></tr>
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<tr class="memdesc:ae029a3656c7e567002eb4fbc936f209d"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Test <br /></td></tr>
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<tr class="separator:ae029a3656c7e567002eb4fbc936f209d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a78b1dd73d667635e4e713782f354b17f"><td class="memItemLeft" align="right" valign="top"><a id="a78b1dd73d667635e4e713782f354b17f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a78b1dd73d667635e4e713782f354b17f">REG_CAN0_RWD</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000014UL)</td></tr>
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<tr class="memdesc:a78b1dd73d667635e4e713782f354b17f"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) RAM Watchdog <br /></td></tr>
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<tr class="separator:a78b1dd73d667635e4e713782f354b17f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a904004cddcc5fe5143a2126fbd0d7b1d"><td class="memItemLeft" align="right" valign="top"><a id="a904004cddcc5fe5143a2126fbd0d7b1d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a904004cddcc5fe5143a2126fbd0d7b1d">REG_CAN0_CCCR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000018UL)</td></tr>
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<tr class="memdesc:a904004cddcc5fe5143a2126fbd0d7b1d"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) CC Control <br /></td></tr>
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<tr class="separator:a904004cddcc5fe5143a2126fbd0d7b1d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6269e25f48b8c7d2d2ce1f88d32de23b"><td class="memItemLeft" align="right" valign="top"><a id="a6269e25f48b8c7d2d2ce1f88d32de23b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a6269e25f48b8c7d2d2ce1f88d32de23b">REG_CAN0_NBTP</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4200001CUL)</td></tr>
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<tr class="memdesc:a6269e25f48b8c7d2d2ce1f88d32de23b"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Nominal Bit Timing and Prescaler <br /></td></tr>
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<tr class="separator:a6269e25f48b8c7d2d2ce1f88d32de23b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a98dbec03d5a5522f5c4db9b173daa5ea"><td class="memItemLeft" align="right" valign="top"><a id="a98dbec03d5a5522f5c4db9b173daa5ea"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a98dbec03d5a5522f5c4db9b173daa5ea">REG_CAN0_TSCC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000020UL)</td></tr>
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<tr class="memdesc:a98dbec03d5a5522f5c4db9b173daa5ea"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Timestamp Counter Configuration <br /></td></tr>
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<tr class="separator:a98dbec03d5a5522f5c4db9b173daa5ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae69d1aae93a642d34d916ab18a2ab9ea"><td class="memItemLeft" align="right" valign="top"><a id="ae69d1aae93a642d34d916ab18a2ab9ea"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#ae69d1aae93a642d34d916ab18a2ab9ea">REG_CAN0_TSCV</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x42000024UL)</td></tr>
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<tr class="memdesc:ae69d1aae93a642d34d916ab18a2ab9ea"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Timestamp Counter Value <br /></td></tr>
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<tr class="separator:ae69d1aae93a642d34d916ab18a2ab9ea"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a503df71a059bf085515d292ea3cfe78b"><td class="memItemLeft" align="right" valign="top"><a id="a503df71a059bf085515d292ea3cfe78b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a503df71a059bf085515d292ea3cfe78b">REG_CAN0_TOCC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000028UL)</td></tr>
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<tr class="memdesc:a503df71a059bf085515d292ea3cfe78b"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Timeout Counter Configuration <br /></td></tr>
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<tr class="separator:a503df71a059bf085515d292ea3cfe78b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3b620bcd156becd408e1fe7dec46c716"><td class="memItemLeft" align="right" valign="top"><a id="a3b620bcd156becd408e1fe7dec46c716"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a3b620bcd156becd408e1fe7dec46c716">REG_CAN0_TOCV</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4200002CUL)</td></tr>
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<tr class="memdesc:a3b620bcd156becd408e1fe7dec46c716"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Timeout Counter Value <br /></td></tr>
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<tr class="separator:a3b620bcd156becd408e1fe7dec46c716"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad9b7daaf9b7b03d5be1b979194742784"><td class="memItemLeft" align="right" valign="top"><a id="ad9b7daaf9b7b03d5be1b979194742784"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#ad9b7daaf9b7b03d5be1b979194742784">REG_CAN0_ECR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x42000040UL)</td></tr>
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<tr class="memdesc:ad9b7daaf9b7b03d5be1b979194742784"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Error Counter <br /></td></tr>
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<tr class="separator:ad9b7daaf9b7b03d5be1b979194742784"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a5ec38192586ce82891ff8658ba1871"><td class="memItemLeft" align="right" valign="top"><a id="a0a5ec38192586ce82891ff8658ba1871"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a0a5ec38192586ce82891ff8658ba1871">REG_CAN0_PSR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x42000044UL)</td></tr>
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<tr class="memdesc:a0a5ec38192586ce82891ff8658ba1871"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Protocol Status <br /></td></tr>
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<tr class="separator:a0a5ec38192586ce82891ff8658ba1871"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7a5c155bd6ada1b4273ee9722058e583"><td class="memItemLeft" align="right" valign="top"><a id="a7a5c155bd6ada1b4273ee9722058e583"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a7a5c155bd6ada1b4273ee9722058e583">REG_CAN0_TDCR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000048UL)</td></tr>
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<tr class="memdesc:a7a5c155bd6ada1b4273ee9722058e583"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Extended ID Filter Configuration <br /></td></tr>
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<tr class="separator:a7a5c155bd6ada1b4273ee9722058e583"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a65795d772174c6878246c57ae2b4cc"><td class="memItemLeft" align="right" valign="top"><a id="a0a65795d772174c6878246c57ae2b4cc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a0a65795d772174c6878246c57ae2b4cc">REG_CAN0_IR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000050UL)</td></tr>
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<tr class="memdesc:a0a65795d772174c6878246c57ae2b4cc"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Interrupt <br /></td></tr>
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<tr class="separator:a0a65795d772174c6878246c57ae2b4cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a212d9ba27b17d94fa6c1b0606ca0dd50"><td class="memItemLeft" align="right" valign="top"><a id="a212d9ba27b17d94fa6c1b0606ca0dd50"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a212d9ba27b17d94fa6c1b0606ca0dd50">REG_CAN0_IE</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000054UL)</td></tr>
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<tr class="memdesc:a212d9ba27b17d94fa6c1b0606ca0dd50"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Interrupt Enable <br /></td></tr>
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<tr class="separator:a212d9ba27b17d94fa6c1b0606ca0dd50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a69fe9af8871de113d98c88869f09f699"><td class="memItemLeft" align="right" valign="top"><a id="a69fe9af8871de113d98c88869f09f699"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a69fe9af8871de113d98c88869f09f699">REG_CAN0_ILS</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000058UL)</td></tr>
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<tr class="memdesc:a69fe9af8871de113d98c88869f09f699"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Interrupt Line Select <br /></td></tr>
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<tr class="separator:a69fe9af8871de113d98c88869f09f699"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a35ccc25e65d5ba96731d837c80aaa69e"><td class="memItemLeft" align="right" valign="top"><a id="a35ccc25e65d5ba96731d837c80aaa69e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a35ccc25e65d5ba96731d837c80aaa69e">REG_CAN0_ILE</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4200005CUL)</td></tr>
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<tr class="memdesc:a35ccc25e65d5ba96731d837c80aaa69e"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Interrupt Line Enable <br /></td></tr>
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<tr class="separator:a35ccc25e65d5ba96731d837c80aaa69e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8154a5854c66d8ce3072f9b3daee8794"><td class="memItemLeft" align="right" valign="top"><a id="a8154a5854c66d8ce3072f9b3daee8794"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a8154a5854c66d8ce3072f9b3daee8794">REG_CAN0_GFC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000080UL)</td></tr>
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<tr class="memdesc:a8154a5854c66d8ce3072f9b3daee8794"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Global Filter Configuration <br /></td></tr>
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<tr class="separator:a8154a5854c66d8ce3072f9b3daee8794"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8433ec4eb43a86bdeefec641448bc426"><td class="memItemLeft" align="right" valign="top"><a id="a8433ec4eb43a86bdeefec641448bc426"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a8433ec4eb43a86bdeefec641448bc426">REG_CAN0_SIDFC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000084UL)</td></tr>
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<tr class="memdesc:a8433ec4eb43a86bdeefec641448bc426"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Standard ID Filter Configuration <br /></td></tr>
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<tr class="separator:a8433ec4eb43a86bdeefec641448bc426"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7b77bac0b6d81dcd4f2a476c8a97e115"><td class="memItemLeft" align="right" valign="top"><a id="a7b77bac0b6d81dcd4f2a476c8a97e115"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a7b77bac0b6d81dcd4f2a476c8a97e115">REG_CAN0_XIDFC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000088UL)</td></tr>
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<tr class="memdesc:a7b77bac0b6d81dcd4f2a476c8a97e115"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Extended ID Filter Configuration <br /></td></tr>
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<tr class="separator:a7b77bac0b6d81dcd4f2a476c8a97e115"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6ff316ef5816c3ad50e083816547bf9a"><td class="memItemLeft" align="right" valign="top"><a id="a6ff316ef5816c3ad50e083816547bf9a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a6ff316ef5816c3ad50e083816547bf9a">REG_CAN0_XIDAM</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000090UL)</td></tr>
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<tr class="memdesc:a6ff316ef5816c3ad50e083816547bf9a"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Extended ID AND Mask <br /></td></tr>
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<tr class="separator:a6ff316ef5816c3ad50e083816547bf9a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acef49af23336ffb2049f9c1cd4565a9e"><td class="memItemLeft" align="right" valign="top"><a id="acef49af23336ffb2049f9c1cd4565a9e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#acef49af23336ffb2049f9c1cd4565a9e">REG_CAN0_HPMS</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x42000094UL)</td></tr>
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<tr class="memdesc:acef49af23336ffb2049f9c1cd4565a9e"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) High Priority Message Status <br /></td></tr>
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<tr class="separator:acef49af23336ffb2049f9c1cd4565a9e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6d9c9cc51367f5c178dfb4595722968d"><td class="memItemLeft" align="right" valign="top"><a id="a6d9c9cc51367f5c178dfb4595722968d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a6d9c9cc51367f5c178dfb4595722968d">REG_CAN0_NDAT1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x42000098UL)</td></tr>
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<tr class="memdesc:a6d9c9cc51367f5c178dfb4595722968d"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) New Data 1 <br /></td></tr>
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<tr class="separator:a6d9c9cc51367f5c178dfb4595722968d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a20dd31879065f711f986da74408c237d"><td class="memItemLeft" align="right" valign="top"><a id="a20dd31879065f711f986da74408c237d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a20dd31879065f711f986da74408c237d">REG_CAN0_NDAT2</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4200009CUL)</td></tr>
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<tr class="memdesc:a20dd31879065f711f986da74408c237d"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) New Data 2 <br /></td></tr>
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<tr class="separator:a20dd31879065f711f986da74408c237d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a18bed93e3bb4d03c9336985fdf39e727"><td class="memItemLeft" align="right" valign="top"><a id="a18bed93e3bb4d03c9336985fdf39e727"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a18bed93e3bb4d03c9336985fdf39e727">REG_CAN0_RXF0C</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000A0UL)</td></tr>
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<tr class="memdesc:a18bed93e3bb4d03c9336985fdf39e727"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Rx FIFO 0 Configuration <br /></td></tr>
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<tr class="separator:a18bed93e3bb4d03c9336985fdf39e727"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acbb93b36e76f7bb9b3a47c05c4755d68"><td class="memItemLeft" align="right" valign="top"><a id="acbb93b36e76f7bb9b3a47c05c4755d68"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#acbb93b36e76f7bb9b3a47c05c4755d68">REG_CAN0_RXF0S</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420000A4UL)</td></tr>
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<tr class="memdesc:acbb93b36e76f7bb9b3a47c05c4755d68"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Rx FIFO 0 Status <br /></td></tr>
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<tr class="separator:acbb93b36e76f7bb9b3a47c05c4755d68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adb84d9f3bcc150d0d528b487ffdaddfa"><td class="memItemLeft" align="right" valign="top"><a id="adb84d9f3bcc150d0d528b487ffdaddfa"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#adb84d9f3bcc150d0d528b487ffdaddfa">REG_CAN0_RXF0A</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000A8UL)</td></tr>
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<tr class="memdesc:adb84d9f3bcc150d0d528b487ffdaddfa"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Rx FIFO 0 Acknowledge <br /></td></tr>
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<tr class="separator:adb84d9f3bcc150d0d528b487ffdaddfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8b8324a6470af3586cac6213f066a56d"><td class="memItemLeft" align="right" valign="top"><a id="a8b8324a6470af3586cac6213f066a56d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a8b8324a6470af3586cac6213f066a56d">REG_CAN0_RXBC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000ACUL)</td></tr>
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<tr class="memdesc:a8b8324a6470af3586cac6213f066a56d"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Rx Buffer Configuration <br /></td></tr>
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<tr class="separator:a8b8324a6470af3586cac6213f066a56d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4c9a625a26cd01e57dad56a40ba2afd9"><td class="memItemLeft" align="right" valign="top"><a id="a4c9a625a26cd01e57dad56a40ba2afd9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a4c9a625a26cd01e57dad56a40ba2afd9">REG_CAN0_RXF1C</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000B0UL)</td></tr>
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<tr class="memdesc:a4c9a625a26cd01e57dad56a40ba2afd9"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Rx FIFO 1 Configuration <br /></td></tr>
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<tr class="separator:a4c9a625a26cd01e57dad56a40ba2afd9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a50d2a9c26237c4bbe57eeddbe8cf1b9f"><td class="memItemLeft" align="right" valign="top"><a id="a50d2a9c26237c4bbe57eeddbe8cf1b9f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a50d2a9c26237c4bbe57eeddbe8cf1b9f">REG_CAN0_RXF1S</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420000B4UL)</td></tr>
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<tr class="memdesc:a50d2a9c26237c4bbe57eeddbe8cf1b9f"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Rx FIFO 1 Status <br /></td></tr>
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<tr class="separator:a50d2a9c26237c4bbe57eeddbe8cf1b9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6c2e21ab20809fffc82ee036bff485a0"><td class="memItemLeft" align="right" valign="top"><a id="a6c2e21ab20809fffc82ee036bff485a0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a6c2e21ab20809fffc82ee036bff485a0">REG_CAN0_RXF1A</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000B8UL)</td></tr>
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<tr class="memdesc:a6c2e21ab20809fffc82ee036bff485a0"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Rx FIFO 1 Acknowledge <br /></td></tr>
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<tr class="separator:a6c2e21ab20809fffc82ee036bff485a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a64522c510e7e11fd348cce55971abd59"><td class="memItemLeft" align="right" valign="top"><a id="a64522c510e7e11fd348cce55971abd59"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a64522c510e7e11fd348cce55971abd59">REG_CAN0_RXESC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000BCUL)</td></tr>
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<tr class="memdesc:a64522c510e7e11fd348cce55971abd59"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Rx Buffer / FIFO Element Size Configuration <br /></td></tr>
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<tr class="separator:a64522c510e7e11fd348cce55971abd59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acd43dc2ce51efdb97e96eb92e84f7193"><td class="memItemLeft" align="right" valign="top"><a id="acd43dc2ce51efdb97e96eb92e84f7193"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#acd43dc2ce51efdb97e96eb92e84f7193">REG_CAN0_TXBC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000C0UL)</td></tr>
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<tr class="memdesc:acd43dc2ce51efdb97e96eb92e84f7193"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx Buffer Configuration <br /></td></tr>
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<tr class="separator:acd43dc2ce51efdb97e96eb92e84f7193"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8560ea3aebd28604c8368ba4ea421786"><td class="memItemLeft" align="right" valign="top"><a id="a8560ea3aebd28604c8368ba4ea421786"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a8560ea3aebd28604c8368ba4ea421786">REG_CAN0_TXFQS</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420000C4UL)</td></tr>
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<tr class="memdesc:a8560ea3aebd28604c8368ba4ea421786"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx FIFO / Queue Status <br /></td></tr>
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<tr class="separator:a8560ea3aebd28604c8368ba4ea421786"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2ebbcdab4c92bf3efcc7f59e6f0eb739"><td class="memItemLeft" align="right" valign="top"><a id="a2ebbcdab4c92bf3efcc7f59e6f0eb739"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a2ebbcdab4c92bf3efcc7f59e6f0eb739">REG_CAN0_TXESC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000C8UL)</td></tr>
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<tr class="memdesc:a2ebbcdab4c92bf3efcc7f59e6f0eb739"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx Buffer Element Size Configuration <br /></td></tr>
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<tr class="separator:a2ebbcdab4c92bf3efcc7f59e6f0eb739"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7d010450c605245bb095641e1d5a08c7"><td class="memItemLeft" align="right" valign="top"><a id="a7d010450c605245bb095641e1d5a08c7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a7d010450c605245bb095641e1d5a08c7">REG_CAN0_TXBRP</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420000CCUL)</td></tr>
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<tr class="memdesc:a7d010450c605245bb095641e1d5a08c7"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx Buffer Request Pending <br /></td></tr>
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<tr class="separator:a7d010450c605245bb095641e1d5a08c7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a703ec9b292dd6425448e9dfd8ad0240d"><td class="memItemLeft" align="right" valign="top"><a id="a703ec9b292dd6425448e9dfd8ad0240d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a703ec9b292dd6425448e9dfd8ad0240d">REG_CAN0_TXBAR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000D0UL)</td></tr>
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<tr class="memdesc:a703ec9b292dd6425448e9dfd8ad0240d"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx Buffer Add Request <br /></td></tr>
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<tr class="separator:a703ec9b292dd6425448e9dfd8ad0240d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a95e0fa7fc64efb36df006d3cd9ca20fd"><td class="memItemLeft" align="right" valign="top"><a id="a95e0fa7fc64efb36df006d3cd9ca20fd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a95e0fa7fc64efb36df006d3cd9ca20fd">REG_CAN0_TXBCR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000D4UL)</td></tr>
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<tr class="memdesc:a95e0fa7fc64efb36df006d3cd9ca20fd"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx Buffer Cancellation Request <br /></td></tr>
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<tr class="separator:a95e0fa7fc64efb36df006d3cd9ca20fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a54148a226eb3925a4a994c4e218afa90"><td class="memItemLeft" align="right" valign="top"><a id="a54148a226eb3925a4a994c4e218afa90"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a54148a226eb3925a4a994c4e218afa90">REG_CAN0_TXBTO</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420000D8UL)</td></tr>
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<tr class="memdesc:a54148a226eb3925a4a994c4e218afa90"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx Buffer Transmission Occurred <br /></td></tr>
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<tr class="separator:a54148a226eb3925a4a994c4e218afa90"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4b91469a069e06269301dc348b7f01d5"><td class="memItemLeft" align="right" valign="top"><a id="a4b91469a069e06269301dc348b7f01d5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a4b91469a069e06269301dc348b7f01d5">REG_CAN0_TXBCF</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420000DCUL)</td></tr>
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<tr class="memdesc:a4b91469a069e06269301dc348b7f01d5"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx Buffer Cancellation Finished <br /></td></tr>
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<tr class="separator:a4b91469a069e06269301dc348b7f01d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2bec8f6811eda9d184039a7a87452e85"><td class="memItemLeft" align="right" valign="top"><a id="a2bec8f6811eda9d184039a7a87452e85"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a2bec8f6811eda9d184039a7a87452e85">REG_CAN0_TXBTIE</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000E0UL)</td></tr>
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<tr class="memdesc:a2bec8f6811eda9d184039a7a87452e85"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx Buffer Transmission Interrupt Enable <br /></td></tr>
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<tr class="separator:a2bec8f6811eda9d184039a7a87452e85"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae88f1a1bc2e2dcb1668132ed13df03a0"><td class="memItemLeft" align="right" valign="top"><a id="ae88f1a1bc2e2dcb1668132ed13df03a0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#ae88f1a1bc2e2dcb1668132ed13df03a0">REG_CAN0_TXBCIE</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000E4UL)</td></tr>
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<tr class="memdesc:ae88f1a1bc2e2dcb1668132ed13df03a0"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx Buffer Cancellation Finished Interrupt Enable <br /></td></tr>
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<tr class="separator:ae88f1a1bc2e2dcb1668132ed13df03a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a38d320a7baf11fc13de21e41494b9432"><td class="memItemLeft" align="right" valign="top"><a id="a38d320a7baf11fc13de21e41494b9432"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a38d320a7baf11fc13de21e41494b9432">REG_CAN0_TXEFC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000F0UL)</td></tr>
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<tr class="memdesc:a38d320a7baf11fc13de21e41494b9432"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx Event FIFO Configuration <br /></td></tr>
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<tr class="separator:a38d320a7baf11fc13de21e41494b9432"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a649645ed86a43cb92a0407a128cddb94"><td class="memItemLeft" align="right" valign="top"><a id="a649645ed86a43cb92a0407a128cddb94"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a649645ed86a43cb92a0407a128cddb94">REG_CAN0_TXEFS</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x420000F4UL)</td></tr>
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<tr class="memdesc:a649645ed86a43cb92a0407a128cddb94"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx Event FIFO Status <br /></td></tr>
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<tr class="separator:a649645ed86a43cb92a0407a128cddb94"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3a197a7618d54c5d81484ceab851f2ee"><td class="memItemLeft" align="right" valign="top"><a id="a3a197a7618d54c5d81484ceab851f2ee"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="can0_8h.html#a3a197a7618d54c5d81484ceab851f2ee">REG_CAN0_TXEFA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x420000F8UL)</td></tr>
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<tr class="memdesc:a3a197a7618d54c5d81484ceab851f2ee"><td class="mdescLeft"> </td><td class="mdescRight">(CAN0) Tx Event FIFO Acknowledge <br /></td></tr>
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<tr class="separator:a3a197a7618d54c5d81484ceab851f2ee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abfdf97332c3fe4482b3cc272e105c72b"><td class="memItemLeft" align="right" valign="top"><a id="abfdf97332c3fe4482b3cc272e105c72b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CAN0_CLK_AHB_ID</b>   17</td></tr>
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<tr class="separator:abfdf97332c3fe4482b3cc272e105c72b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad4c52f1972e973b2c9fdbe54a815a619"><td class="memItemLeft" align="right" valign="top"><a id="ad4c52f1972e973b2c9fdbe54a815a619"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CAN0_DMAC_ID_DEBUG</b>   20</td></tr>
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<tr class="separator:ad4c52f1972e973b2c9fdbe54a815a619"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3af07215584a04290599fb7cf3a550cf"><td class="memItemLeft" align="right" valign="top"><a id="a3af07215584a04290599fb7cf3a550cf"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CAN0_GCLK_ID</b>   27</td></tr>
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<tr class="separator:a3af07215584a04290599fb7cf3a550cf"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab97b8779b3b09e9921f31d8cabd813b3"><td class="memItemLeft" align="right" valign="top"><a id="ab97b8779b3b09e9921f31d8cabd813b3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CAN0_MSG_RAM_ADDR</b>   0x20000000</td></tr>
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<tr class="separator:ab97b8779b3b09e9921f31d8cabd813b3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1ec3589951105c7c17d5bb0b8c25b1e2"><td class="memItemLeft" align="right" valign="top"><a id="a1ec3589951105c7c17d5bb0b8c25b1e2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>CAN0_QOS_RESET_VAL</b>   1</td></tr>
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<tr class="separator:a1ec3589951105c7c17d5bb0b8c25b1e2"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for CAN0. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="can0_8h_source.html">can0.h</a>.</p>
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