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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">adc1.h</div> </div>
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<div class="contents">
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<a href="adc1_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_ADC1_INSTANCE_</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_ADC1_INSTANCE_</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for ADC1 peripheral ========== */</span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_ADC1_CTRLA (0x43002000) </span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_ADC1_EVCTRL (0x43002002) </span></div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_ADC1_DBGCTRL (0x43002003) </span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_ADC1_INPUTCTRL (0x43002004) </span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_ADC1_CTRLB (0x43002006) </span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_ADC1_REFCTRL (0x43002008) </span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_ADC1_AVGCTRL (0x4300200A) </span></div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_ADC1_SAMPCTRL (0x4300200B) </span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_ADC1_WINLT (0x4300200C) </span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_ADC1_WINUT (0x4300200E) </span></div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_ADC1_GAINCORR (0x43002010) </span></div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_ADC1_OFFSETCORR (0x43002012) </span></div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_ADC1_SWTRIG (0x43002014) </span></div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_ADC1_INTENCLR (0x4300202C) </span></div>
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<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_ADC1_INTENSET (0x4300202D) </span></div>
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<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_ADC1_INTFLAG (0x4300202E) </span></div>
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<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_ADC1_STATUS (0x4300202F) </span></div>
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<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_ADC1_SYNCBUSY (0x43002030) </span></div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_ADC1_DSEQDATA (0x43002034) </span></div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_ADC1_DSEQCTRL (0x43002038) </span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_ADC1_DSEQSTAT (0x4300203C) </span></div>
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<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_ADC1_RESULT (0x43002040) </span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define REG_ADC1_RESS (0x43002044) </span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define REG_ADC1_CALIB (0x43002048) </span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#else</span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"><a class="line" href="adc1_8h.html#a889bb4afda6f19016be53f942d9dcaa7"> 60</a></span> <span class="preprocessor">#define REG_ADC1_CTRLA (*(RwReg16*)0x43002000UL) </span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"><a class="line" href="adc1_8h.html#a8d8a85da254fa6254195ec9590c7b90c"> 61</a></span> <span class="preprocessor">#define REG_ADC1_EVCTRL (*(RwReg8 *)0x43002002UL) </span></div>
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<div class="line"><a name="l00062"></a><span class="lineno"><a class="line" href="adc1_8h.html#a27832ea3120141700dff4462b11a45bf"> 62</a></span> <span class="preprocessor">#define REG_ADC1_DBGCTRL (*(RwReg8 *)0x43002003UL) </span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"><a class="line" href="adc1_8h.html#ab87e5bf0001e98a97dc2b818b13f60d2"> 63</a></span> <span class="preprocessor">#define REG_ADC1_INPUTCTRL (*(RwReg16*)0x43002004UL) </span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"><a class="line" href="adc1_8h.html#a83295a9be8f972c0fb1d88c4e4981bb7"> 64</a></span> <span class="preprocessor">#define REG_ADC1_CTRLB (*(RwReg16*)0x43002006UL) </span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="adc1_8h.html#a0955264b6ddf8ba672544fbe4ae006ae"> 65</a></span> <span class="preprocessor">#define REG_ADC1_REFCTRL (*(RwReg8 *)0x43002008UL) </span></div>
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<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="adc1_8h.html#a513d8fd03493a42685bb94d7efc4805f"> 66</a></span> <span class="preprocessor">#define REG_ADC1_AVGCTRL (*(RwReg8 *)0x4300200AUL) </span></div>
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<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="adc1_8h.html#a60c711563b4e055a18e89ddbc234222a"> 67</a></span> <span class="preprocessor">#define REG_ADC1_SAMPCTRL (*(RwReg8 *)0x4300200BUL) </span></div>
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<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="adc1_8h.html#ad8ca474fabf2ec762ada61c55acbe14f"> 68</a></span> <span class="preprocessor">#define REG_ADC1_WINLT (*(RwReg16*)0x4300200CUL) </span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="adc1_8h.html#a8c1f48f8ab952dd8b725c4d225c54ccf"> 69</a></span> <span class="preprocessor">#define REG_ADC1_WINUT (*(RwReg16*)0x4300200EUL) </span></div>
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<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="adc1_8h.html#a8f200e75abed6b2df5bb8a525179cbd8"> 70</a></span> <span class="preprocessor">#define REG_ADC1_GAINCORR (*(RwReg16*)0x43002010UL) </span></div>
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<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="adc1_8h.html#a681c424b05b5d2602f21ca924e6d2c05"> 71</a></span> <span class="preprocessor">#define REG_ADC1_OFFSETCORR (*(RwReg16*)0x43002012UL) </span></div>
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<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="adc1_8h.html#a5925f329a44958467668fc3b65d94454"> 72</a></span> <span class="preprocessor">#define REG_ADC1_SWTRIG (*(RwReg8 *)0x43002014UL) </span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="adc1_8h.html#ab0808e68ce2115779f62d8a27f4d5482"> 73</a></span> <span class="preprocessor">#define REG_ADC1_INTENCLR (*(RwReg8 *)0x4300202CUL) </span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="adc1_8h.html#a2462454fb3d48f8af9277c0d535223ec"> 74</a></span> <span class="preprocessor">#define REG_ADC1_INTENSET (*(RwReg8 *)0x4300202DUL) </span></div>
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<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="adc1_8h.html#a72cbb9a06ebed167d2d093451364c983"> 75</a></span> <span class="preprocessor">#define REG_ADC1_INTFLAG (*(RwReg8 *)0x4300202EUL) </span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="adc1_8h.html#a9ab116d19eca9b554fd39520cf34de34"> 76</a></span> <span class="preprocessor">#define REG_ADC1_STATUS (*(RoReg8 *)0x4300202FUL) </span></div>
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<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="adc1_8h.html#a956ac5ca7327440f1214b92502179c87"> 77</a></span> <span class="preprocessor">#define REG_ADC1_SYNCBUSY (*(RoReg *)0x43002030UL) </span></div>
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<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="adc1_8h.html#a7023a0f2e1d714e4d3481355dec02ab0"> 78</a></span> <span class="preprocessor">#define REG_ADC1_DSEQDATA (*(WoReg *)0x43002034UL) </span></div>
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<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="adc1_8h.html#aa1061d5398537fbe439e81ad56bad5f1"> 79</a></span> <span class="preprocessor">#define REG_ADC1_DSEQCTRL (*(RwReg *)0x43002038UL) </span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="adc1_8h.html#a91cc5991ee8fa9df4d8feff7b187b903"> 80</a></span> <span class="preprocessor">#define REG_ADC1_DSEQSTAT (*(RoReg *)0x4300203CUL) </span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="adc1_8h.html#ab26c130fe7a9aaa2b2468f22b6eebb38"> 81</a></span> <span class="preprocessor">#define REG_ADC1_RESULT (*(RoReg16*)0x43002040UL) </span></div>
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<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="adc1_8h.html#a3f84a3d776fd892f17cd25f486cf9f85"> 82</a></span> <span class="preprocessor">#define REG_ADC1_RESS (*(RoReg16*)0x43002044UL) </span></div>
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<div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="adc1_8h.html#a500784578d055a8a70b2f8743c94472c"> 83</a></span> <span class="preprocessor">#define REG_ADC1_CALIB (*(RwReg16*)0x43002048UL) </span></div>
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<div class="line"><a name="l00084"></a><span class="lineno"> 84</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"> 85</span>  </div>
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<div class="line"><a name="l00086"></a><span class="lineno"> 86</span> <span class="comment">/* ========== Instance parameters for ADC1 peripheral ========== */</span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"> 87</span> <span class="preprocessor">#define ADC1_BANDGAP 27 // MUXPOS value to select BANDGAP</span></div>
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<div class="line"><a name="l00088"></a><span class="lineno"> 88</span> <span class="preprocessor">#define ADC1_CTAT 29 // MUXPOS value to select CTAT</span></div>
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<div class="line"><a name="l00089"></a><span class="lineno"> 89</span> <span class="preprocessor">#define ADC1_DMAC_ID_RESRDY 70 // Index of DMA RESRDY trigger</span></div>
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<div class="line"><a name="l00090"></a><span class="lineno"> 90</span> <span class="preprocessor">#define ADC1_DMAC_ID_SEQ 71 // Index of DMA SEQ trigger</span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"> 91</span> <span class="preprocessor">#define ADC1_EXTCHANNEL_MSB 15 // Number of external channels</span></div>
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<div class="line"><a name="l00092"></a><span class="lineno"> 92</span> <span class="preprocessor">#define ADC1_GCLK_ID 41 // Index of Generic Clock</span></div>
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<div class="line"><a name="l00093"></a><span class="lineno"> 93</span> <span class="preprocessor">#define ADC1_MASTER_SLAVE_MODE 2 // ADC Master/Slave Mode</span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor">#define ADC1_OPAMP2 0 // MUXPOS value to select OPAMP2</span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span> <span class="preprocessor">#define ADC1_OPAMP01 0 // MUXPOS value to select OPAMP01</span></div>
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<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="preprocessor">#define ADC1_PTAT 28 // MUXPOS value to select PTAT</span></div>
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<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="preprocessor">#define ADC1_TOUCH_IMPLEMENTED 0 // TOUCH implemented or not</span></div>
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<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#define ADC1_TOUCH_LINES_NUM 1 // Number of touch lines</span></div>
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<div class="line"><a name="l00099"></a><span class="lineno"> 99</span>  </div>
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<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_ADC1_INSTANCE_ */</span><span class="preprocessor"></span></div>
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