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223 lines
24 KiB
C
223 lines
24 KiB
C
/**
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* \brief Component description for OSC32KCTRL
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-09-28T13:45:00Z */
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#ifndef _SAMD51_OSC32KCTRL_COMPONENT_H_
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#define _SAMD51_OSC32KCTRL_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR OSC32KCTRL */
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/* ************************************************************************** */
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/* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
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#define OSC32KCTRL_INTENCLR_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_INTENCLR) Interrupt Enable Clear Reset Value */
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#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos _U_(0) /**< (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable Position */
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#define OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos) /**< (OSC32KCTRL_INTENCLR) XOSC32K Ready Interrupt Enable Mask */
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#define OSC32KCTRL_INTENCLR_XOSC32KRDY(value) (OSC32KCTRL_INTENCLR_XOSC32KRDY_Msk & ((value) << OSC32KCTRL_INTENCLR_XOSC32KRDY_Pos))
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#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos _U_(2) /**< (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable Position */
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#define OSC32KCTRL_INTENCLR_XOSC32KFAIL_Msk (_U_(0x1) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos) /**< (OSC32KCTRL_INTENCLR) XOSC32K Clock Failure Detector Interrupt Enable Mask */
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#define OSC32KCTRL_INTENCLR_XOSC32KFAIL(value) (OSC32KCTRL_INTENCLR_XOSC32KFAIL_Msk & ((value) << OSC32KCTRL_INTENCLR_XOSC32KFAIL_Pos))
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#define OSC32KCTRL_INTENCLR_Msk _U_(0x00000005) /**< (OSC32KCTRL_INTENCLR) Register Mask */
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/* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
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#define OSC32KCTRL_INTENSET_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_INTENSET) Interrupt Enable Set Reset Value */
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#define OSC32KCTRL_INTENSET_XOSC32KRDY_Pos _U_(0) /**< (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable Position */
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#define OSC32KCTRL_INTENSET_XOSC32KRDY_Msk (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos) /**< (OSC32KCTRL_INTENSET) XOSC32K Ready Interrupt Enable Mask */
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#define OSC32KCTRL_INTENSET_XOSC32KRDY(value) (OSC32KCTRL_INTENSET_XOSC32KRDY_Msk & ((value) << OSC32KCTRL_INTENSET_XOSC32KRDY_Pos))
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#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos _U_(2) /**< (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable Position */
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#define OSC32KCTRL_INTENSET_XOSC32KFAIL_Msk (_U_(0x1) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos) /**< (OSC32KCTRL_INTENSET) XOSC32K Clock Failure Detector Interrupt Enable Mask */
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#define OSC32KCTRL_INTENSET_XOSC32KFAIL(value) (OSC32KCTRL_INTENSET_XOSC32KFAIL_Msk & ((value) << OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos))
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#define OSC32KCTRL_INTENSET_Msk _U_(0x00000005) /**< (OSC32KCTRL_INTENSET) Register Mask */
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/* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
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#define OSC32KCTRL_INTFLAG_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_INTFLAG) Interrupt Flag Status and Clear Reset Value */
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#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos _U_(0) /**< (OSC32KCTRL_INTFLAG) XOSC32K Ready Position */
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#define OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos) /**< (OSC32KCTRL_INTFLAG) XOSC32K Ready Mask */
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#define OSC32KCTRL_INTFLAG_XOSC32KRDY(value) (OSC32KCTRL_INTFLAG_XOSC32KRDY_Msk & ((value) << OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos))
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#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos _U_(2) /**< (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector Position */
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#define OSC32KCTRL_INTFLAG_XOSC32KFAIL_Msk (_U_(0x1) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos) /**< (OSC32KCTRL_INTFLAG) XOSC32K Clock Failure Detector Mask */
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#define OSC32KCTRL_INTFLAG_XOSC32KFAIL(value) (OSC32KCTRL_INTFLAG_XOSC32KFAIL_Msk & ((value) << OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos))
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#define OSC32KCTRL_INTFLAG_Msk _U_(0x00000005) /**< (OSC32KCTRL_INTFLAG) Register Mask */
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/* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) ( R/ 32) Power and Clocks Status -------- */
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#define OSC32KCTRL_STATUS_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_STATUS) Power and Clocks Status Reset Value */
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#define OSC32KCTRL_STATUS_XOSC32KRDY_Pos _U_(0) /**< (OSC32KCTRL_STATUS) XOSC32K Ready Position */
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#define OSC32KCTRL_STATUS_XOSC32KRDY_Msk (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos) /**< (OSC32KCTRL_STATUS) XOSC32K Ready Mask */
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#define OSC32KCTRL_STATUS_XOSC32KRDY(value) (OSC32KCTRL_STATUS_XOSC32KRDY_Msk & ((value) << OSC32KCTRL_STATUS_XOSC32KRDY_Pos))
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#define OSC32KCTRL_STATUS_XOSC32KFAIL_Pos _U_(2) /**< (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector Position */
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#define OSC32KCTRL_STATUS_XOSC32KFAIL_Msk (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos) /**< (OSC32KCTRL_STATUS) XOSC32K Clock Failure Detector Mask */
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#define OSC32KCTRL_STATUS_XOSC32KFAIL(value) (OSC32KCTRL_STATUS_XOSC32KFAIL_Msk & ((value) << OSC32KCTRL_STATUS_XOSC32KFAIL_Pos))
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#define OSC32KCTRL_STATUS_XOSC32KSW_Pos _U_(3) /**< (OSC32KCTRL_STATUS) XOSC32K Clock switch Position */
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#define OSC32KCTRL_STATUS_XOSC32KSW_Msk (_U_(0x1) << OSC32KCTRL_STATUS_XOSC32KSW_Pos) /**< (OSC32KCTRL_STATUS) XOSC32K Clock switch Mask */
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#define OSC32KCTRL_STATUS_XOSC32KSW(value) (OSC32KCTRL_STATUS_XOSC32KSW_Msk & ((value) << OSC32KCTRL_STATUS_XOSC32KSW_Pos))
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#define OSC32KCTRL_STATUS_Msk _U_(0x0000000D) /**< (OSC32KCTRL_STATUS) Register Mask */
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/* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */
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#define OSC32KCTRL_RTCCTRL_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Reset Value */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_Pos _U_(0) /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Position */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_Msk (_U_(0x7) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Mask */
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#define OSC32KCTRL_RTCCTRL_RTCSEL(value) (OSC32KCTRL_RTCCTRL_RTCSEL_Msk & ((value) << OSC32KCTRL_RTCCTRL_RTCSEL_Pos))
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#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val _U_(0x0) /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val _U_(0x1) /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val _U_(0x4) /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val _U_(0x5) /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32kHz internal ULP oscillator Position */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K (OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32kHz internal ULP oscillator Position */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) 1.024kHz from 32.768kHz internal oscillator Position */
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#define OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K (OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val << OSC32KCTRL_RTCCTRL_RTCSEL_Pos) /**< (OSC32KCTRL_RTCCTRL) 32.768kHz from 32.768kHz external crystal oscillator Position */
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#define OSC32KCTRL_RTCCTRL_Msk _U_(0x07) /**< (OSC32KCTRL_RTCCTRL) Register Mask */
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/* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
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#define OSC32KCTRL_XOSC32K_RESETVALUE _U_(0x2080) /**< (OSC32KCTRL_XOSC32K) 32kHz External Crystal Oscillator (XOSC32K) Control Reset Value */
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#define OSC32KCTRL_XOSC32K_ENABLE_Pos _U_(1) /**< (OSC32KCTRL_XOSC32K) Oscillator Enable Position */
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#define OSC32KCTRL_XOSC32K_ENABLE_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_ENABLE_Pos) /**< (OSC32KCTRL_XOSC32K) Oscillator Enable Mask */
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#define OSC32KCTRL_XOSC32K_ENABLE(value) (OSC32KCTRL_XOSC32K_ENABLE_Msk & ((value) << OSC32KCTRL_XOSC32K_ENABLE_Pos))
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#define OSC32KCTRL_XOSC32K_XTALEN_Pos _U_(2) /**< (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable Position */
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#define OSC32KCTRL_XOSC32K_XTALEN_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_XTALEN_Pos) /**< (OSC32KCTRL_XOSC32K) Crystal Oscillator Enable Mask */
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#define OSC32KCTRL_XOSC32K_XTALEN(value) (OSC32KCTRL_XOSC32K_XTALEN_Msk & ((value) << OSC32KCTRL_XOSC32K_XTALEN_Pos))
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#define OSC32KCTRL_XOSC32K_EN32K_Pos _U_(3) /**< (OSC32KCTRL_XOSC32K) 32kHz Output Enable Position */
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#define OSC32KCTRL_XOSC32K_EN32K_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_EN32K_Pos) /**< (OSC32KCTRL_XOSC32K) 32kHz Output Enable Mask */
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#define OSC32KCTRL_XOSC32K_EN32K(value) (OSC32KCTRL_XOSC32K_EN32K_Msk & ((value) << OSC32KCTRL_XOSC32K_EN32K_Pos))
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#define OSC32KCTRL_XOSC32K_EN1K_Pos _U_(4) /**< (OSC32KCTRL_XOSC32K) 1kHz Output Enable Position */
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#define OSC32KCTRL_XOSC32K_EN1K_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_EN1K_Pos) /**< (OSC32KCTRL_XOSC32K) 1kHz Output Enable Mask */
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#define OSC32KCTRL_XOSC32K_EN1K(value) (OSC32KCTRL_XOSC32K_EN1K_Msk & ((value) << OSC32KCTRL_XOSC32K_EN1K_Pos))
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#define OSC32KCTRL_XOSC32K_RUNSTDBY_Pos _U_(6) /**< (OSC32KCTRL_XOSC32K) Run in Standby Position */
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#define OSC32KCTRL_XOSC32K_RUNSTDBY_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) /**< (OSC32KCTRL_XOSC32K) Run in Standby Mask */
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#define OSC32KCTRL_XOSC32K_RUNSTDBY(value) (OSC32KCTRL_XOSC32K_RUNSTDBY_Msk & ((value) << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos))
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#define OSC32KCTRL_XOSC32K_ONDEMAND_Pos _U_(7) /**< (OSC32KCTRL_XOSC32K) On Demand Control Position */
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#define OSC32KCTRL_XOSC32K_ONDEMAND_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) /**< (OSC32KCTRL_XOSC32K) On Demand Control Mask */
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#define OSC32KCTRL_XOSC32K_ONDEMAND(value) (OSC32KCTRL_XOSC32K_ONDEMAND_Msk & ((value) << OSC32KCTRL_XOSC32K_ONDEMAND_Pos))
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#define OSC32KCTRL_XOSC32K_STARTUP_Pos _U_(8) /**< (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time Position */
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#define OSC32KCTRL_XOSC32K_STARTUP_Msk (_U_(0x7) << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) Oscillator Start-Up Time Mask */
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#define OSC32KCTRL_XOSC32K_STARTUP(value) (OSC32KCTRL_XOSC32K_STARTUP_Msk & ((value) << OSC32KCTRL_XOSC32K_STARTUP_Pos))
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048_Val _U_(0x0) /**< (OSC32KCTRL_XOSC32K) 62.6 ms */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096_Val _U_(0x1) /**< (OSC32KCTRL_XOSC32K) 125 ms */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384_Val _U_(0x2) /**< (OSC32KCTRL_XOSC32K) 500 ms */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768_Val _U_(0x3) /**< (OSC32KCTRL_XOSC32K) 1000 ms */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536_Val _U_(0x4) /**< (OSC32KCTRL_XOSC32K) 2000 ms */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072_Val _U_(0x5) /**< (OSC32KCTRL_XOSC32K) 4000 ms */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144_Val _U_(0x6) /**< (OSC32KCTRL_XOSC32K) 8000 ms */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE2048_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 62.6 ms Position */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE4096_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 125 ms Position */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE16384_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 500 ms Position */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE32768_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 1000 ms Position */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE65536_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 2000 ms Position */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE131072_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 4000 ms Position */
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#define OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144 (OSC32KCTRL_XOSC32K_STARTUP_CYCLE262144_Val << OSC32KCTRL_XOSC32K_STARTUP_Pos) /**< (OSC32KCTRL_XOSC32K) 8000 ms Position */
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#define OSC32KCTRL_XOSC32K_WRTLOCK_Pos _U_(12) /**< (OSC32KCTRL_XOSC32K) Write Lock Position */
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#define OSC32KCTRL_XOSC32K_WRTLOCK_Msk (_U_(0x1) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos) /**< (OSC32KCTRL_XOSC32K) Write Lock Mask */
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#define OSC32KCTRL_XOSC32K_WRTLOCK(value) (OSC32KCTRL_XOSC32K_WRTLOCK_Msk & ((value) << OSC32KCTRL_XOSC32K_WRTLOCK_Pos))
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#define OSC32KCTRL_XOSC32K_CGM_Pos _U_(13) /**< (OSC32KCTRL_XOSC32K) Control Gain Mode Position */
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#define OSC32KCTRL_XOSC32K_CGM_Msk (_U_(0x3) << OSC32KCTRL_XOSC32K_CGM_Pos) /**< (OSC32KCTRL_XOSC32K) Control Gain Mode Mask */
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#define OSC32KCTRL_XOSC32K_CGM(value) (OSC32KCTRL_XOSC32K_CGM_Msk & ((value) << OSC32KCTRL_XOSC32K_CGM_Pos))
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#define OSC32KCTRL_XOSC32K_CGM_XT_Val _U_(0x1) /**< (OSC32KCTRL_XOSC32K) Standard mode */
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#define OSC32KCTRL_XOSC32K_CGM_HS_Val _U_(0x2) /**< (OSC32KCTRL_XOSC32K) High Speed mode */
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#define OSC32KCTRL_XOSC32K_CGM_XT (OSC32KCTRL_XOSC32K_CGM_XT_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /**< (OSC32KCTRL_XOSC32K) Standard mode Position */
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#define OSC32KCTRL_XOSC32K_CGM_HS (OSC32KCTRL_XOSC32K_CGM_HS_Val << OSC32KCTRL_XOSC32K_CGM_Pos) /**< (OSC32KCTRL_XOSC32K) High Speed mode Position */
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#define OSC32KCTRL_XOSC32K_Msk _U_(0x77DE) /**< (OSC32KCTRL_XOSC32K) Register Mask */
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/* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */
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#define OSC32KCTRL_CFDCTRL_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Control Reset Value */
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#define OSC32KCTRL_CFDCTRL_CFDEN_Pos _U_(0) /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable Position */
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#define OSC32KCTRL_CFDCTRL_CFDEN_Msk (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDEN_Pos) /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Enable Mask */
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#define OSC32KCTRL_CFDCTRL_CFDEN(value) (OSC32KCTRL_CFDCTRL_CFDEN_Msk & ((value) << OSC32KCTRL_CFDCTRL_CFDEN_Pos))
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#define OSC32KCTRL_CFDCTRL_SWBACK_Pos _U_(1) /**< (OSC32KCTRL_CFDCTRL) Clock Switch Back Position */
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#define OSC32KCTRL_CFDCTRL_SWBACK_Msk (_U_(0x1) << OSC32KCTRL_CFDCTRL_SWBACK_Pos) /**< (OSC32KCTRL_CFDCTRL) Clock Switch Back Mask */
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#define OSC32KCTRL_CFDCTRL_SWBACK(value) (OSC32KCTRL_CFDCTRL_SWBACK_Msk & ((value) << OSC32KCTRL_CFDCTRL_SWBACK_Pos))
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#define OSC32KCTRL_CFDCTRL_CFDPRESC_Pos _U_(2) /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler Position */
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#define OSC32KCTRL_CFDCTRL_CFDPRESC_Msk (_U_(0x1) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos) /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Prescaler Mask */
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#define OSC32KCTRL_CFDCTRL_CFDPRESC(value) (OSC32KCTRL_CFDCTRL_CFDPRESC_Msk & ((value) << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos))
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#define OSC32KCTRL_CFDCTRL_Msk _U_(0x07) /**< (OSC32KCTRL_CFDCTRL) Register Mask */
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/* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */
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#define OSC32KCTRL_EVCTRL_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_EVCTRL) Event Control Reset Value */
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#define OSC32KCTRL_EVCTRL_CFDEO_Pos _U_(0) /**< (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable Position */
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#define OSC32KCTRL_EVCTRL_CFDEO_Msk (_U_(0x1) << OSC32KCTRL_EVCTRL_CFDEO_Pos) /**< (OSC32KCTRL_EVCTRL) Clock Failure Detector Event Output Enable Mask */
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#define OSC32KCTRL_EVCTRL_CFDEO(value) (OSC32KCTRL_EVCTRL_CFDEO_Msk & ((value) << OSC32KCTRL_EVCTRL_CFDEO_Pos))
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#define OSC32KCTRL_EVCTRL_Msk _U_(0x01) /**< (OSC32KCTRL_EVCTRL) Register Mask */
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/* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
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#define OSC32KCTRL_OSCULP32K_RESETVALUE _U_(0x00) /**< (OSC32KCTRL_OSCULP32K) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control Reset Value */
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#define OSC32KCTRL_OSCULP32K_EN32K_Pos _U_(1) /**< (OSC32KCTRL_OSCULP32K) Enable Out 32k Position */
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#define OSC32KCTRL_OSCULP32K_EN32K_Msk (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN32K_Pos) /**< (OSC32KCTRL_OSCULP32K) Enable Out 32k Mask */
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#define OSC32KCTRL_OSCULP32K_EN32K(value) (OSC32KCTRL_OSCULP32K_EN32K_Msk & ((value) << OSC32KCTRL_OSCULP32K_EN32K_Pos))
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#define OSC32KCTRL_OSCULP32K_EN1K_Pos _U_(2) /**< (OSC32KCTRL_OSCULP32K) Enable Out 1k Position */
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#define OSC32KCTRL_OSCULP32K_EN1K_Msk (_U_(0x1) << OSC32KCTRL_OSCULP32K_EN1K_Pos) /**< (OSC32KCTRL_OSCULP32K) Enable Out 1k Mask */
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#define OSC32KCTRL_OSCULP32K_EN1K(value) (OSC32KCTRL_OSCULP32K_EN1K_Msk & ((value) << OSC32KCTRL_OSCULP32K_EN1K_Pos))
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#define OSC32KCTRL_OSCULP32K_CALIB_Pos _U_(8) /**< (OSC32KCTRL_OSCULP32K) Oscillator Calibration Position */
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#define OSC32KCTRL_OSCULP32K_CALIB_Msk (_U_(0x3F) << OSC32KCTRL_OSCULP32K_CALIB_Pos) /**< (OSC32KCTRL_OSCULP32K) Oscillator Calibration Mask */
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#define OSC32KCTRL_OSCULP32K_CALIB(value) (OSC32KCTRL_OSCULP32K_CALIB_Msk & ((value) << OSC32KCTRL_OSCULP32K_CALIB_Pos))
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#define OSC32KCTRL_OSCULP32K_WRTLOCK_Pos _U_(15) /**< (OSC32KCTRL_OSCULP32K) Write Lock Position */
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#define OSC32KCTRL_OSCULP32K_WRTLOCK_Msk (_U_(0x1) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos) /**< (OSC32KCTRL_OSCULP32K) Write Lock Mask */
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#define OSC32KCTRL_OSCULP32K_WRTLOCK(value) (OSC32KCTRL_OSCULP32K_WRTLOCK_Msk & ((value) << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos))
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#define OSC32KCTRL_OSCULP32K_Msk _U_(0x0000BF06) /**< (OSC32KCTRL_OSCULP32K) Register Mask */
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/** \brief OSC32KCTRL register offsets definitions */
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#define OSC32KCTRL_INTENCLR_REG_OFST (0x00) /**< (OSC32KCTRL_INTENCLR) Interrupt Enable Clear Offset */
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#define OSC32KCTRL_INTENSET_REG_OFST (0x04) /**< (OSC32KCTRL_INTENSET) Interrupt Enable Set Offset */
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#define OSC32KCTRL_INTFLAG_REG_OFST (0x08) /**< (OSC32KCTRL_INTFLAG) Interrupt Flag Status and Clear Offset */
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#define OSC32KCTRL_STATUS_REG_OFST (0x0C) /**< (OSC32KCTRL_STATUS) Power and Clocks Status Offset */
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#define OSC32KCTRL_RTCCTRL_REG_OFST (0x10) /**< (OSC32KCTRL_RTCCTRL) RTC Clock Selection Offset */
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#define OSC32KCTRL_XOSC32K_REG_OFST (0x14) /**< (OSC32KCTRL_XOSC32K) 32kHz External Crystal Oscillator (XOSC32K) Control Offset */
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#define OSC32KCTRL_CFDCTRL_REG_OFST (0x16) /**< (OSC32KCTRL_CFDCTRL) Clock Failure Detector Control Offset */
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#define OSC32KCTRL_EVCTRL_REG_OFST (0x17) /**< (OSC32KCTRL_EVCTRL) Event Control Offset */
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#define OSC32KCTRL_OSCULP32K_REG_OFST (0x1C) /**< (OSC32KCTRL_OSCULP32K) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief OSC32KCTRL register API structure */
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typedef struct
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{ /* 32kHz Oscillators Control */
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__IO uint32_t OSC32KCTRL_INTENCLR; /**< Offset: 0x00 (R/W 32) Interrupt Enable Clear */
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__IO uint32_t OSC32KCTRL_INTENSET; /**< Offset: 0x04 (R/W 32) Interrupt Enable Set */
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__IO uint32_t OSC32KCTRL_INTFLAG; /**< Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
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__I uint32_t OSC32KCTRL_STATUS; /**< Offset: 0x0C (R/ 32) Power and Clocks Status */
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__IO uint8_t OSC32KCTRL_RTCCTRL; /**< Offset: 0x10 (R/W 8) RTC Clock Selection */
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__I uint8_t Reserved1[0x03];
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__IO uint16_t OSC32KCTRL_XOSC32K; /**< Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
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__IO uint8_t OSC32KCTRL_CFDCTRL; /**< Offset: 0x16 (R/W 8) Clock Failure Detector Control */
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__IO uint8_t OSC32KCTRL_EVCTRL; /**< Offset: 0x17 (R/W 8) Event Control */
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__I uint8_t Reserved2[0x04];
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__IO uint32_t OSC32KCTRL_OSCULP32K; /**< Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
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} osc32kctrl_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAMD51_OSC32KCTRL_COMPONENT_H_ */
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