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<a name="define_peephole2"></a>
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<a name="define_005fpeephole2"></a>
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<p>
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Previous: <a rel="previous" accesskey="p" href="define_005fpeephole.html#define_005fpeephole">define_peephole</a>,
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Up: <a rel="up" accesskey="u" href="Peephole-Definitions.html#Peephole-Definitions">Peephole Definitions</a>
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<h4 class="subsection">16.18.2 RTL to RTL Peephole Optimizers</h4>
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<p><a name="index-define_005fpeephole2-3716"></a>
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The <code>define_peephole2</code> definition tells the compiler how to
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substitute one sequence of instructions for another sequence,
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what additional scratch registers may be needed and what their
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lifetimes must be.
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<pre class="smallexample"> (define_peephole2
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[<var>insn-pattern-1</var>
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<var>insn-pattern-2</var>
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...]
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"<var>condition</var>"
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[<var>new-insn-pattern-1</var>
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<var>new-insn-pattern-2</var>
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...]
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"<var>preparation-statements</var>")
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</pre>
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<p>The definition is almost identical to <code>define_split</code>
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(see <a href="Insn-Splitting.html#Insn-Splitting">Insn Splitting</a>) except that the pattern to match is not a
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single instruction, but a sequence of instructions.
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<p>It is possible to request additional scratch registers for use in the
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output template. If appropriate registers are not free, the pattern
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will simply not match.
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<p><a name="index-match_005fscratch-3717"></a><a name="index-match_005fdup-3718"></a>Scratch registers are requested with a <code>match_scratch</code> pattern at
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the top level of the input pattern. The allocated register (initially) will
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be dead at the point requested within the original sequence. If the scratch
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is used at more than a single point, a <code>match_dup</code> pattern at the
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top level of the input pattern marks the last position in the input sequence
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at which the register must be available.
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<p>Here is an example from the IA-32 machine description:
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<pre class="smallexample"> (define_peephole2
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[(match_scratch:SI 2 "r")
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(parallel [(set (match_operand:SI 0 "register_operand" "")
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(match_operator:SI 3 "arith_or_logical_operator"
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[(match_dup 0)
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(match_operand:SI 1 "memory_operand" "")]))
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(clobber (reg:CC 17))])]
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"! optimize_size && ! TARGET_READ_MODIFY"
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[(set (match_dup 2) (match_dup 1))
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(parallel [(set (match_dup 0)
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(match_op_dup 3 [(match_dup 0) (match_dup 2)]))
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(clobber (reg:CC 17))])]
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"")
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</pre>
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<p class="noindent">This pattern tries to split a load from its use in the hopes that we'll be
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able to schedule around the memory load latency. It allocates a single
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<code>SImode</code> register of class <code>GENERAL_REGS</code> (<code>"r"</code>) that needs
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to be live only at the point just before the arithmetic.
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<p>A real example requiring extended scratch lifetimes is harder to come by,
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so here's a silly made-up example:
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<pre class="smallexample"> (define_peephole2
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[(match_scratch:SI 4 "r")
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(set (match_operand:SI 0 "" "") (match_operand:SI 1 "" ""))
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(set (match_operand:SI 2 "" "") (match_dup 1))
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(match_dup 4)
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(set (match_operand:SI 3 "" "") (match_dup 1))]
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"/* <span class="roman">determine 1 does not overlap 0 and 2</span> */"
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[(set (match_dup 4) (match_dup 1))
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(set (match_dup 0) (match_dup 4))
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(set (match_dup 2) (match_dup 4))
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(set (match_dup 3) (match_dup 4))]
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"")
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</pre>
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<p class="noindent">If we had not added the <code>(match_dup 4)</code> in the middle of the input
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sequence, it might have been the case that the register we chose at the
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beginning of the sequence is killed by the first or second <code>set</code>.
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