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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/i2s.h File Reference</title>
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">i2s.h File Reference</div> </div>
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</div><!--header-->
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<div class="contents">
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<p>Instance description for I2S.
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<a href="#details">More...</a></p>
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<p><a href="instance_2i2s_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:aca31981572241bdc9eb12c58a1f89fbe"><td class="memItemLeft" align="right" valign="top"><a id="aca31981572241bdc9eb12c58a1f89fbe"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2i2s_8h.html#aca31981572241bdc9eb12c58a1f89fbe">REG_I2S_CTRLA</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43002800UL)</td></tr>
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<tr class="memdesc:aca31981572241bdc9eb12c58a1f89fbe"><td class="mdescLeft"> </td><td class="mdescRight">(I2S) Control A <br /></td></tr>
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<tr class="separator:aca31981572241bdc9eb12c58a1f89fbe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a228eec13e6920756f69c10eddf155d8c"><td class="memItemLeft" align="right" valign="top"><a id="a228eec13e6920756f69c10eddf155d8c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2i2s_8h.html#a228eec13e6920756f69c10eddf155d8c">REG_I2S_CLKCTRL0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43002804UL)</td></tr>
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<tr class="memdesc:a228eec13e6920756f69c10eddf155d8c"><td class="mdescLeft"> </td><td class="mdescRight">(I2S) Clock Unit 0 Control <br /></td></tr>
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<tr class="separator:a228eec13e6920756f69c10eddf155d8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a022c508f34831c0b6647e6fb8279f488"><td class="memItemLeft" align="right" valign="top"><a id="a022c508f34831c0b6647e6fb8279f488"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2i2s_8h.html#a022c508f34831c0b6647e6fb8279f488">REG_I2S_CLKCTRL1</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43002808UL)</td></tr>
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<tr class="memdesc:a022c508f34831c0b6647e6fb8279f488"><td class="mdescLeft"> </td><td class="mdescRight">(I2S) Clock Unit 1 Control <br /></td></tr>
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<tr class="separator:a022c508f34831c0b6647e6fb8279f488"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a59e256ae5f1c86d0e4324b56c6839eda"><td class="memItemLeft" align="right" valign="top"><a id="a59e256ae5f1c86d0e4324b56c6839eda"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2i2s_8h.html#a59e256ae5f1c86d0e4324b56c6839eda">REG_I2S_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4300280CUL)</td></tr>
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<tr class="memdesc:a59e256ae5f1c86d0e4324b56c6839eda"><td class="mdescLeft"> </td><td class="mdescRight">(I2S) Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a59e256ae5f1c86d0e4324b56c6839eda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac5160303de4a47e22b69c18717084d52"><td class="memItemLeft" align="right" valign="top"><a id="ac5160303de4a47e22b69c18717084d52"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2i2s_8h.html#ac5160303de4a47e22b69c18717084d52">REG_I2S_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x43002810UL)</td></tr>
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<tr class="memdesc:ac5160303de4a47e22b69c18717084d52"><td class="mdescLeft"> </td><td class="mdescRight">(I2S) Interrupt Enable Set <br /></td></tr>
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<tr class="separator:ac5160303de4a47e22b69c18717084d52"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acea71d42a9b05139cc900dd20950ebe2"><td class="memItemLeft" align="right" valign="top"><a id="acea71d42a9b05139cc900dd20950ebe2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2i2s_8h.html#acea71d42a9b05139cc900dd20950ebe2">REG_I2S_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x43002814UL)</td></tr>
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<tr class="memdesc:acea71d42a9b05139cc900dd20950ebe2"><td class="mdescLeft"> </td><td class="mdescRight">(I2S) Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:acea71d42a9b05139cc900dd20950ebe2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a56f4fad77f4f20d714c1e8c564122ac0"><td class="memItemLeft" align="right" valign="top"><a id="a56f4fad77f4f20d714c1e8c564122ac0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2i2s_8h.html#a56f4fad77f4f20d714c1e8c564122ac0">REG_I2S_SYNCBUSY</a>   (*(<a class="el" href="same54n19a_8h.html#aebf6e33c2d49a802e06e22a95ea9d0d0">RoReg16</a>*)0x43002818UL)</td></tr>
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<tr class="memdesc:a56f4fad77f4f20d714c1e8c564122ac0"><td class="mdescLeft"> </td><td class="mdescRight">(I2S) Synchronization Status <br /></td></tr>
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<tr class="separator:a56f4fad77f4f20d714c1e8c564122ac0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a99833b16fd9c50b7c7c4f2c69f31c56f"><td class="memItemLeft" align="right" valign="top"><a id="a99833b16fd9c50b7c7c4f2c69f31c56f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2i2s_8h.html#a99833b16fd9c50b7c7c4f2c69f31c56f">REG_I2S_TXCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43002820UL)</td></tr>
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<tr class="memdesc:a99833b16fd9c50b7c7c4f2c69f31c56f"><td class="mdescLeft"> </td><td class="mdescRight">(I2S) Tx Serializer Control <br /></td></tr>
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<tr class="separator:a99833b16fd9c50b7c7c4f2c69f31c56f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8c936b766ec611bed9f6cf852ae2ca2"><td class="memItemLeft" align="right" valign="top"><a id="af8c936b766ec611bed9f6cf852ae2ca2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2i2s_8h.html#af8c936b766ec611bed9f6cf852ae2ca2">REG_I2S_RXCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43002824UL)</td></tr>
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<tr class="memdesc:af8c936b766ec611bed9f6cf852ae2ca2"><td class="mdescLeft"> </td><td class="mdescRight">(I2S) Rx Serializer Control <br /></td></tr>
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<tr class="separator:af8c936b766ec611bed9f6cf852ae2ca2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a315df7813944b58c26fb9052b4c148fa"><td class="memItemLeft" align="right" valign="top"><a id="a315df7813944b58c26fb9052b4c148fa"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2i2s_8h.html#a315df7813944b58c26fb9052b4c148fa">REG_I2S_TXDATA</a>   (*(<a class="el" href="same54n19a_8h.html#ac0f96d4e8018367b38f527007cf0eafd">WoReg</a> *)0x43002830UL)</td></tr>
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<tr class="memdesc:a315df7813944b58c26fb9052b4c148fa"><td class="mdescLeft"> </td><td class="mdescRight">(I2S) Tx Data <br /></td></tr>
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<tr class="separator:a315df7813944b58c26fb9052b4c148fa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a79235085021ec757243ad28e1829d389"><td class="memItemLeft" align="right" valign="top"><a id="a79235085021ec757243ad28e1829d389"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2i2s_8h.html#a79235085021ec757243ad28e1829d389">REG_I2S_RXDATA</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x43002834UL)</td></tr>
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<tr class="memdesc:a79235085021ec757243ad28e1829d389"><td class="mdescLeft"> </td><td class="mdescRight">(I2S) Rx Data <br /></td></tr>
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<tr class="separator:a79235085021ec757243ad28e1829d389"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a53d90fe2d4d8272139c711bc65f4ec6f"><td class="memItemLeft" align="right" valign="top"><a id="a53d90fe2d4d8272139c711bc65f4ec6f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_CLK_NUM</b>   2</td></tr>
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<tr class="separator:a53d90fe2d4d8272139c711bc65f4ec6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afad866d6d76f0beb4a05675d80cd2c6d"><td class="memItemLeft" align="right" valign="top"><a id="afad866d6d76f0beb4a05675d80cd2c6d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_DMAC_ID_RX_0</b>   76</td></tr>
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<tr class="separator:afad866d6d76f0beb4a05675d80cd2c6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae5e595ff155f10d8a5e2aa2567c4f8c3"><td class="memItemLeft" align="right" valign="top"><a id="ae5e595ff155f10d8a5e2aa2567c4f8c3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_DMAC_ID_RX_1</b>   77</td></tr>
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<tr class="separator:ae5e595ff155f10d8a5e2aa2567c4f8c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3bfdd498ef2a4eb3446ce377ce5f5845"><td class="memItemLeft" align="right" valign="top"><a id="a3bfdd498ef2a4eb3446ce377ce5f5845"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_DMAC_ID_RX_LSB</b>   76</td></tr>
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<tr class="memitem:aeeea1615f130ca554ee3ca95348b423f"><td class="memItemLeft" align="right" valign="top"><a id="aeeea1615f130ca554ee3ca95348b423f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_DMAC_ID_RX_MSB</b>   77</td></tr>
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<tr class="memitem:a994f5e26207fa468ccc1efcf4b577bc1"><td class="memItemLeft" align="right" valign="top"><a id="a994f5e26207fa468ccc1efcf4b577bc1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_DMAC_ID_RX_SIZE</b>   2</td></tr>
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<tr class="memitem:adf129b1f89bc06bb7616b2fc2ad00993"><td class="memItemLeft" align="right" valign="top"><a id="adf129b1f89bc06bb7616b2fc2ad00993"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_DMAC_ID_TX_0</b>   78</td></tr>
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<tr class="separator:adf129b1f89bc06bb7616b2fc2ad00993"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a327e115d953c49b8489e63e5cde1cf6d"><td class="memItemLeft" align="right" valign="top"><a id="a327e115d953c49b8489e63e5cde1cf6d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_DMAC_ID_TX_1</b>   79</td></tr>
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<tr class="memitem:a9f6b7669d91e012a72802569c52ee5c1"><td class="memItemLeft" align="right" valign="top"><a id="a9f6b7669d91e012a72802569c52ee5c1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_DMAC_ID_TX_LSB</b>   78</td></tr>
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<tr class="memitem:a3f5d1b629c4e798054b5da4b3c2f3aeb"><td class="memItemLeft" align="right" valign="top"><a id="a3f5d1b629c4e798054b5da4b3c2f3aeb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_DMAC_ID_TX_MSB</b>   79</td></tr>
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<tr class="memitem:aec4b9065efc2eaafc242eb7c3dc86a91"><td class="memItemLeft" align="right" valign="top"><a id="aec4b9065efc2eaafc242eb7c3dc86a91"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_DMAC_ID_TX_SIZE</b>   2</td></tr>
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<tr class="memitem:a4775839e4e1cd5ba27bde56505bdfffa"><td class="memItemLeft" align="right" valign="top"><a id="a4775839e4e1cd5ba27bde56505bdfffa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_GCLK_ID_0</b>   43</td></tr>
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<tr class="memitem:aad46bf3b6696458350a1e9b9220dca77"><td class="memItemLeft" align="right" valign="top"><a id="aad46bf3b6696458350a1e9b9220dca77"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_GCLK_ID_1</b>   44</td></tr>
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<tr class="separator:aad46bf3b6696458350a1e9b9220dca77"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2eb6736592e709bade794212b691841d"><td class="memItemLeft" align="right" valign="top"><a id="a2eb6736592e709bade794212b691841d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_GCLK_ID_LSB</b>   43</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_GCLK_ID_MSB</b>   44</td></tr>
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<tr class="memitem:a1f2f7f66bec4476d7f4a48d47466d64e"><td class="memItemLeft" align="right" valign="top"><a id="a1f2f7f66bec4476d7f4a48d47466d64e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_GCLK_ID_SIZE</b>   2</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_MAX_SLOTS</b>   8</td></tr>
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<tr class="memitem:a30ba3d6fc5152bddad20bbda9cec4ff1"><td class="memItemLeft" align="right" valign="top"><a id="a30ba3d6fc5152bddad20bbda9cec4ff1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_MAX_WL_BITS</b>   32</td></tr>
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<tr class="memitem:a0ac556ec25df9663b3c5cf265d9c0372"><td class="memItemLeft" align="right" valign="top"><a id="a0ac556ec25df9663b3c5cf265d9c0372"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>I2S_SER_NUM</b>   2</td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for I2S. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="instance_2i2s_8h_source.html">i2s.h</a>.</p>
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