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Next: <a rel="next" accesskey="n" href="MIPS-Loongson-Built_002din-Functions.html#MIPS-Loongson-Built_002din-Functions">MIPS Loongson Built-in Functions</a>,
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<h4 class="subsection">6.58.13 MIPS Paired-Single Support</h4>
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<p>The MIPS64 architecture includes a number of instructions that
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operate on pairs of single-precision floating-point values.
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Each pair is packed into a 64-bit floating-point register,
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with one element being designated the “upper half” and
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the other being designated the “lower half”.
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<p>GCC supports paired-single operations using both the generic
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vector extensions (see <a href="Vector-Extensions.html#Vector-Extensions">Vector Extensions</a>) and a collection of
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MIPS-specific built-in functions. Both kinds of support are
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enabled by the <samp><span class="option">-mpaired-single</span></samp> command-line option.
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<p>The vector type associated with paired-single values is usually
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called <code>v2sf</code>. It can be defined in C as follows:
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<pre class="smallexample"> typedef float v2sf __attribute__ ((vector_size (8)));
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</pre>
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<p><code>v2sf</code> values are initialized in the same way as aggregates.
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For example:
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<pre class="smallexample"> v2sf a = {1.5, 9.1};
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v2sf b;
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float e, f;
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b = (v2sf) {e, f};
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</pre>
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<p><em>Note:</em> The CPU's endianness determines which value is stored in
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the upper half of a register and which value is stored in the lower half.
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On little-endian targets, the first value is the lower one and the second
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value is the upper one. The opposite order applies to big-endian targets.
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For example, the code above sets the lower half of <code>a</code> to
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<code>1.5</code> on little-endian targets and <code>9.1</code> on big-endian targets.
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