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100 lines
6.7 KiB
C
100 lines
6.7 KiB
C
/**
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* \file
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*
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* \brief Instance description for DMAC
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_DMAC_INSTANCE_
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#define _SAMD21_DMAC_INSTANCE_
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/* ========== Register definition for DMAC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_DMAC_CTRL (0x41004800U) /**< \brief (DMAC) Control */
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#define REG_DMAC_CRCCTRL (0x41004802U) /**< \brief (DMAC) CRC Control */
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#define REG_DMAC_CRCDATAIN (0x41004804U) /**< \brief (DMAC) CRC Data Input */
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#define REG_DMAC_CRCCHKSUM (0x41004808U) /**< \brief (DMAC) CRC Checksum */
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#define REG_DMAC_CRCSTATUS (0x4100480CU) /**< \brief (DMAC) CRC Status */
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#define REG_DMAC_DBGCTRL (0x4100480DU) /**< \brief (DMAC) Debug Control */
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#define REG_DMAC_QOSCTRL (0x4100480EU) /**< \brief (DMAC) QOS Control */
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#define REG_DMAC_SWTRIGCTRL (0x41004810U) /**< \brief (DMAC) Software Trigger Control */
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#define REG_DMAC_PRICTRL0 (0x41004814U) /**< \brief (DMAC) Priority Control 0 */
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#define REG_DMAC_INTPEND (0x41004820U) /**< \brief (DMAC) Interrupt Pending */
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#define REG_DMAC_INTSTATUS (0x41004824U) /**< \brief (DMAC) Interrupt Status */
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#define REG_DMAC_BUSYCH (0x41004828U) /**< \brief (DMAC) Busy Channels */
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#define REG_DMAC_PENDCH (0x4100482CU) /**< \brief (DMAC) Pending Channels */
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#define REG_DMAC_ACTIVE (0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
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#define REG_DMAC_BASEADDR (0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
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#define REG_DMAC_WRBADDR (0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
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#define REG_DMAC_CHID (0x4100483FU) /**< \brief (DMAC) Channel ID */
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#define REG_DMAC_CHCTRLA (0x41004840U) /**< \brief (DMAC) Channel Control A */
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#define REG_DMAC_CHCTRLB (0x41004844U) /**< \brief (DMAC) Channel Control B */
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#define REG_DMAC_CHINTENCLR (0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
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#define REG_DMAC_CHINTENSET (0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
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#define REG_DMAC_CHINTFLAG (0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
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#define REG_DMAC_CHSTATUS (0x4100484FU) /**< \brief (DMAC) Channel Status */
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#else
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#define REG_DMAC_CTRL (*(RwReg16*)0x41004800U) /**< \brief (DMAC) Control */
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#define REG_DMAC_CRCCTRL (*(RwReg16*)0x41004802U) /**< \brief (DMAC) CRC Control */
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#define REG_DMAC_CRCDATAIN (*(RwReg *)0x41004804U) /**< \brief (DMAC) CRC Data Input */
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#define REG_DMAC_CRCCHKSUM (*(RwReg *)0x41004808U) /**< \brief (DMAC) CRC Checksum */
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#define REG_DMAC_CRCSTATUS (*(RwReg8 *)0x4100480CU) /**< \brief (DMAC) CRC Status */
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#define REG_DMAC_DBGCTRL (*(RwReg8 *)0x4100480DU) /**< \brief (DMAC) Debug Control */
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#define REG_DMAC_QOSCTRL (*(RwReg8 *)0x4100480EU) /**< \brief (DMAC) QOS Control */
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#define REG_DMAC_SWTRIGCTRL (*(RwReg *)0x41004810U) /**< \brief (DMAC) Software Trigger Control */
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#define REG_DMAC_PRICTRL0 (*(RwReg *)0x41004814U) /**< \brief (DMAC) Priority Control 0 */
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#define REG_DMAC_INTPEND (*(RwReg16*)0x41004820U) /**< \brief (DMAC) Interrupt Pending */
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#define REG_DMAC_INTSTATUS (*(RoReg *)0x41004824U) /**< \brief (DMAC) Interrupt Status */
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#define REG_DMAC_BUSYCH (*(RoReg *)0x41004828U) /**< \brief (DMAC) Busy Channels */
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#define REG_DMAC_PENDCH (*(RoReg *)0x4100482CU) /**< \brief (DMAC) Pending Channels */
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#define REG_DMAC_ACTIVE (*(RoReg *)0x41004830U) /**< \brief (DMAC) Active Channel and Levels */
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#define REG_DMAC_BASEADDR (*(RwReg *)0x41004834U) /**< \brief (DMAC) Descriptor Memory Section Base Address */
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#define REG_DMAC_WRBADDR (*(RwReg *)0x41004838U) /**< \brief (DMAC) Write-Back Memory Section Base Address */
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#define REG_DMAC_CHID (*(RwReg8 *)0x4100483FU) /**< \brief (DMAC) Channel ID */
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#define REG_DMAC_CHCTRLA (*(RwReg8 *)0x41004840U) /**< \brief (DMAC) Channel Control A */
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#define REG_DMAC_CHCTRLB (*(RwReg *)0x41004844U) /**< \brief (DMAC) Channel Control B */
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#define REG_DMAC_CHINTENCLR (*(RwReg8 *)0x4100484CU) /**< \brief (DMAC) Channel Interrupt Enable Clear */
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#define REG_DMAC_CHINTENSET (*(RwReg8 *)0x4100484DU) /**< \brief (DMAC) Channel Interrupt Enable Set */
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#define REG_DMAC_CHINTFLAG (*(RwReg8 *)0x4100484EU) /**< \brief (DMAC) Channel Interrupt Flag Status and Clear */
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#define REG_DMAC_CHSTATUS (*(RoReg8 *)0x4100484FU) /**< \brief (DMAC) Channel Status */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for DMAC peripheral ========== */
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#define DMAC_CH_BITS 4 // Number of bits to select channel
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#define DMAC_CH_NUM 12 // Number of channels
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#define DMAC_CLK_AHB_ID 5 // AHB clock index
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#define DMAC_EVIN_NUM 4 // Number of input events
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#define DMAC_EVOUT_NUM 4 // Number of output events
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#define DMAC_LVL_BITS 2 // Number of bit to select level priority
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#define DMAC_LVL_NUM 4 // Enable priority level number
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#define DMAC_TRIG_BITS 6 // Number of bits to select trigger source
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#define DMAC_TRIG_NUM 45 // Number of peripheral triggers
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#endif /* _SAMD21_DMAC_INSTANCE_ */
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