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<div id="projectname">SAME54P20A Test Project
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Dmac Struct Reference</div> </div>
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<p>DMAC APB hardware registers.
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<a href="structDmac.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="component_2dmac_8h_source.html">dmac.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a30a5958da3426b2fa78c55aca13d1cc4"><td class="memItemLeft" align="right" valign="top"><a id="a30a5958da3426b2fa78c55aca13d1cc4"></a>
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__IO <a class="el" href="unionDMAC__CTRL__Type.html">DMAC_CTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#a30a5958da3426b2fa78c55aca13d1cc4">CTRL</a></td></tr>
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<tr class="memdesc:a30a5958da3426b2fa78c55aca13d1cc4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 16) Control. <br /></td></tr>
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<tr class="memitem:a12414ace3ca825d274fa41bc8453578b"><td class="memItemLeft" align="right" valign="top"><a id="a12414ace3ca825d274fa41bc8453578b"></a>
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__IO <a class="el" href="unionDMAC__CRCCTRL__Type.html">DMAC_CRCCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#a12414ace3ca825d274fa41bc8453578b">CRCCTRL</a></td></tr>
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<tr class="memdesc:a12414ace3ca825d274fa41bc8453578b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x02 (R/W 16) CRC Control. <br /></td></tr>
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<tr class="separator:a12414ace3ca825d274fa41bc8453578b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad3a090166a092799acfbc1ee5d4e2754"><td class="memItemLeft" align="right" valign="top"><a id="ad3a090166a092799acfbc1ee5d4e2754"></a>
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__IO <a class="el" href="unionDMAC__CRCDATAIN__Type.html">DMAC_CRCDATAIN_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#ad3a090166a092799acfbc1ee5d4e2754">CRCDATAIN</a></td></tr>
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<tr class="memdesc:ad3a090166a092799acfbc1ee5d4e2754"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 32) CRC Data Input. <br /></td></tr>
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<tr class="memitem:a707e8e96b25fa7bb7b1495253e727e79"><td class="memItemLeft" align="right" valign="top"><a id="a707e8e96b25fa7bb7b1495253e727e79"></a>
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__IO <a class="el" href="unionDMAC__CRCCHKSUM__Type.html">DMAC_CRCCHKSUM_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#a707e8e96b25fa7bb7b1495253e727e79">CRCCHKSUM</a></td></tr>
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<tr class="memdesc:a707e8e96b25fa7bb7b1495253e727e79"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 32) CRC Checksum. <br /></td></tr>
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<tr class="memitem:a71ddfa13f7a06dafff0134b78932d36f"><td class="memItemLeft" align="right" valign="top"><a id="a71ddfa13f7a06dafff0134b78932d36f"></a>
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__IO <a class="el" href="unionDMAC__CRCSTATUS__Type.html">DMAC_CRCSTATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#a71ddfa13f7a06dafff0134b78932d36f">CRCSTATUS</a></td></tr>
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<tr class="memdesc:a71ddfa13f7a06dafff0134b78932d36f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 8) CRC Status. <br /></td></tr>
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<tr class="memitem:a66acc4d744ae23e8209bcb3295d9b435"><td class="memItemLeft" align="right" valign="top"><a id="a66acc4d744ae23e8209bcb3295d9b435"></a>
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__IO <a class="el" href="unionDMAC__DBGCTRL__Type.html">DMAC_DBGCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#a66acc4d744ae23e8209bcb3295d9b435">DBGCTRL</a></td></tr>
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<tr class="memdesc:a66acc4d744ae23e8209bcb3295d9b435"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0D (R/W 8) Debug Control. <br /></td></tr>
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<tr class="separator:a66acc4d744ae23e8209bcb3295d9b435"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5c640a7fa01bcc891c1f5f05b84d9c1a"><td class="memItemLeft" align="right" valign="top"><a id="a5c640a7fa01bcc891c1f5f05b84d9c1a"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x2]</td></tr>
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<tr class="separator:a5c640a7fa01bcc891c1f5f05b84d9c1a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4a9d3fbf0dd93c589a2648fa97f4af50"><td class="memItemLeft" align="right" valign="top"><a id="a4a9d3fbf0dd93c589a2648fa97f4af50"></a>
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__IO <a class="el" href="unionDMAC__SWTRIGCTRL__Type.html">DMAC_SWTRIGCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#a4a9d3fbf0dd93c589a2648fa97f4af50">SWTRIGCTRL</a></td></tr>
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<tr class="memdesc:a4a9d3fbf0dd93c589a2648fa97f4af50"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/W 32) Software Trigger Control. <br /></td></tr>
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<tr class="separator:a4a9d3fbf0dd93c589a2648fa97f4af50"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1888f8c42460b446512edf5f966a19d5"><td class="memItemLeft" align="right" valign="top"><a id="a1888f8c42460b446512edf5f966a19d5"></a>
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__IO <a class="el" href="unionDMAC__PRICTRL0__Type.html">DMAC_PRICTRL0_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#a1888f8c42460b446512edf5f966a19d5">PRICTRL0</a></td></tr>
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<tr class="memdesc:a1888f8c42460b446512edf5f966a19d5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 32) Priority Control 0. <br /></td></tr>
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<tr class="separator:a1888f8c42460b446512edf5f966a19d5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a05eb3880059efc6487943e5daab55d2b"><td class="memItemLeft" align="right" valign="top"><a id="a05eb3880059efc6487943e5daab55d2b"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x8]</td></tr>
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<tr class="separator:a05eb3880059efc6487943e5daab55d2b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a00e7d5ff6840fe92744e11307a67063f"><td class="memItemLeft" align="right" valign="top"><a id="a00e7d5ff6840fe92744e11307a67063f"></a>
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__IO <a class="el" href="unionDMAC__INTPEND__Type.html">DMAC_INTPEND_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#a00e7d5ff6840fe92744e11307a67063f">INTPEND</a></td></tr>
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<tr class="memdesc:a00e7d5ff6840fe92744e11307a67063f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x20 (R/W 16) Interrupt Pending. <br /></td></tr>
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<tr class="separator:a00e7d5ff6840fe92744e11307a67063f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a65c1a3cfa84eccf6ec9d8e762c762185"><td class="memItemLeft" align="right" valign="top"><a id="a65c1a3cfa84eccf6ec9d8e762c762185"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x2]</td></tr>
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<tr class="separator:a65c1a3cfa84eccf6ec9d8e762c762185"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a41c5697f64b65f76f5345f84404e3c95"><td class="memItemLeft" align="right" valign="top"><a id="a41c5697f64b65f76f5345f84404e3c95"></a>
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__I <a class="el" href="unionDMAC__INTSTATUS__Type.html">DMAC_INTSTATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#a41c5697f64b65f76f5345f84404e3c95">INTSTATUS</a></td></tr>
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<tr class="memdesc:a41c5697f64b65f76f5345f84404e3c95"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x24 (R/ 32) Interrupt Status. <br /></td></tr>
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<tr class="separator:a41c5697f64b65f76f5345f84404e3c95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7c3dad33e385bb1d14e714e1f9da9b27"><td class="memItemLeft" align="right" valign="top"><a id="a7c3dad33e385bb1d14e714e1f9da9b27"></a>
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__I <a class="el" href="unionDMAC__BUSYCH__Type.html">DMAC_BUSYCH_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#a7c3dad33e385bb1d14e714e1f9da9b27">BUSYCH</a></td></tr>
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<tr class="memdesc:a7c3dad33e385bb1d14e714e1f9da9b27"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x28 (R/ 32) Busy Channels. <br /></td></tr>
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<tr class="separator:a7c3dad33e385bb1d14e714e1f9da9b27"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4e149b70af1677ccd055ea4d2d9abfe6"><td class="memItemLeft" align="right" valign="top"><a id="a4e149b70af1677ccd055ea4d2d9abfe6"></a>
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__I <a class="el" href="unionDMAC__PENDCH__Type.html">DMAC_PENDCH_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#a4e149b70af1677ccd055ea4d2d9abfe6">PENDCH</a></td></tr>
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<tr class="memdesc:a4e149b70af1677ccd055ea4d2d9abfe6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2C (R/ 32) Pending Channels. <br /></td></tr>
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<tr class="separator:a4e149b70af1677ccd055ea4d2d9abfe6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa42ca9bfcb0e8347ea9a825d6a6867a6"><td class="memItemLeft" align="right" valign="top"><a id="aa42ca9bfcb0e8347ea9a825d6a6867a6"></a>
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__I <a class="el" href="unionDMAC__ACTIVE__Type.html">DMAC_ACTIVE_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#aa42ca9bfcb0e8347ea9a825d6a6867a6">ACTIVE</a></td></tr>
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<tr class="memdesc:aa42ca9bfcb0e8347ea9a825d6a6867a6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 (R/ 32) Active Channel and Levels. <br /></td></tr>
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<tr class="separator:aa42ca9bfcb0e8347ea9a825d6a6867a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acf439afa10bb921d80deed2bc2c9aaef"><td class="memItemLeft" align="right" valign="top"><a id="acf439afa10bb921d80deed2bc2c9aaef"></a>
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__IO <a class="el" href="unionDMAC__BASEADDR__Type.html">DMAC_BASEADDR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#acf439afa10bb921d80deed2bc2c9aaef">BASEADDR</a></td></tr>
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<tr class="memdesc:acf439afa10bb921d80deed2bc2c9aaef"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address. <br /></td></tr>
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<tr class="separator:acf439afa10bb921d80deed2bc2c9aaef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a08d749c7922d2792f766ae26a4c5d0a4"><td class="memItemLeft" align="right" valign="top"><a id="a08d749c7922d2792f766ae26a4c5d0a4"></a>
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__IO <a class="el" href="unionDMAC__WRBADDR__Type.html">DMAC_WRBADDR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#a08d749c7922d2792f766ae26a4c5d0a4">WRBADDR</a></td></tr>
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<tr class="memdesc:a08d749c7922d2792f766ae26a4c5d0a4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address. <br /></td></tr>
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<tr class="separator:a08d749c7922d2792f766ae26a4c5d0a4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9b2b8e0d657675e4bf28ae0608562c5f"><td class="memItemLeft" align="right" valign="top"><a id="a9b2b8e0d657675e4bf28ae0608562c5f"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved4</b> [0x4]</td></tr>
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<tr class="separator:a9b2b8e0d657675e4bf28ae0608562c5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa52c9a6bb2447864c9952186164e96ab"><td class="memItemLeft" align="right" valign="top"><a id="aa52c9a6bb2447864c9952186164e96ab"></a>
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<a class="el" href="structDmacChannel.html">DmacChannel</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structDmac.html#aa52c9a6bb2447864c9952186164e96ab">Channel</a> [32]</td></tr>
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<tr class="memdesc:aa52c9a6bb2447864c9952186164e96ab"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x40 <a class="el" href="structDmacChannel.html" title="DmacChannel hardware registers.">DmacChannel</a> groups [CH_NUM]. <br /></td></tr>
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<tr class="separator:aa52c9a6bb2447864c9952186164e96ab"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>DMAC APB hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="component_2dmac_8h_source.html#l01369">1369</a> of file <a class="el" href="component_2dmac_8h_source.html">dmac.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2dmac_8h_source.html">dmac.h</a></li>
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</ul>
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Generated by <a href="http://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.8.20
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</small></address>
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