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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/sercom3.h File Reference</title>
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<p>Instance description for SERCOM3.
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a8e2db59c83938ec568a4386540bceaa4">REG_SERCOM3_I2CS_LENGTH</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x41014022UL)</td></tr>
<tr class="memdesc:a8e2db59c83938ec568a4386540bceaa4"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) I2CS Length <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a3c285806e6ffd5347c39b97736180c25">REG_SERCOM3_I2CS_ADDR</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41014024UL)</td></tr>
<tr class="memdesc:a3c285806e6ffd5347c39b97736180c25"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) I2CS Address <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a7b2cbafb19ab60e861950464df5eafe6">REG_SERCOM3_I2CS_DATA</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41014028UL)</td></tr>
<tr class="memdesc:a7b2cbafb19ab60e861950464df5eafe6"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) I2CS Data <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a1dd2e08998eea99910a817d3244c8da1">REG_SERCOM3_SPI_CTRLA</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41014000UL)</td></tr>
<tr class="memdesc:a1dd2e08998eea99910a817d3244c8da1"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Control A <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a7f11ebf74794b8f41e19483aa57a4ed3">REG_SERCOM3_SPI_CTRLB</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41014004UL)</td></tr>
<tr class="memdesc:a7f11ebf74794b8f41e19483aa57a4ed3"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Control B <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a9861faa0ebf7f0d2ad5c622ec26a73ae">REG_SERCOM3_SPI_CTRLC</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41014008UL)</td></tr>
<tr class="memdesc:a9861faa0ebf7f0d2ad5c622ec26a73ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Control C <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a95347efc2613d3256a62cac58012cc9e">REG_SERCOM3_SPI_BAUD</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4101400CUL)</td></tr>
<tr class="memdesc:a95347efc2613d3256a62cac58012cc9e"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Baud Rate <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a9b2c9c176782c20437ab136d70b650fa">REG_SERCOM3_SPI_INTENCLR</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41014014UL)</td></tr>
<tr class="memdesc:a9b2c9c176782c20437ab136d70b650fa"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Interrupt Enable Clear <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a94d8d8cb1e4c699c1762b987087a1f5e">REG_SERCOM3_SPI_INTENSET</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41014016UL)</td></tr>
<tr class="memdesc:a94d8d8cb1e4c699c1762b987087a1f5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Interrupt Enable Set <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a41093891771a9b1c156031bb9271ad2d">REG_SERCOM3_SPI_INTFLAG</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41014018UL)</td></tr>
<tr class="memdesc:a41093891771a9b1c156031bb9271ad2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Interrupt Flag Status and Clear <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a450fc2bce6b245d8b5d995fb0c6c1aa8">REG_SERCOM3_SPI_STATUS</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4101401AUL)</td></tr>
<tr class="memdesc:a450fc2bce6b245d8b5d995fb0c6c1aa8"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Status <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a8a0fc24d7d854313b3037658de6a7f52">REG_SERCOM3_SPI_SYNCBUSY</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4101401CUL)</td></tr>
<tr class="memdesc:a8a0fc24d7d854313b3037658de6a7f52"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Synchronization Busy <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#ae350b0657b6810e5542ab96a7cffdd20">REG_SERCOM3_SPI_LENGTH</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x41014022UL)</td></tr>
<tr class="memdesc:ae350b0657b6810e5542ab96a7cffdd20"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Length <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a467b414584fae2a043678c323960a702">REG_SERCOM3_SPI_ADDR</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41014024UL)</td></tr>
<tr class="memdesc:a467b414584fae2a043678c323960a702"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Address <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#adf1a4caf34b6c647bce1c786b846ae8b">REG_SERCOM3_SPI_DATA</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41014028UL)</td></tr>
<tr class="memdesc:adf1a4caf34b6c647bce1c786b846ae8b"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Data <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#ac367905408ec6613eb26e3e8b1631d46">REG_SERCOM3_SPI_DBGCTRL</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41014030UL)</td></tr>
<tr class="memdesc:ac367905408ec6613eb26e3e8b1631d46"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) SPI Debug Control <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a9451e1e65d140f3cd35ba2fb277b9625">REG_SERCOM3_USART_CTRLA</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41014000UL)</td></tr>
<tr class="memdesc:a9451e1e65d140f3cd35ba2fb277b9625"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Control A <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a183ad9d474319ded12496f14b8ded54f">REG_SERCOM3_USART_CTRLB</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41014004UL)</td></tr>
<tr class="memdesc:a183ad9d474319ded12496f14b8ded54f"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Control B <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#afde68294cea8ba521d371097aa38792f">REG_SERCOM3_USART_CTRLC</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41014008UL)</td></tr>
<tr class="memdesc:afde68294cea8ba521d371097aa38792f"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Control C <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a80190755421d9f1d6f7fbf58fd4d1fb3">REG_SERCOM3_USART_BAUD</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4101400CUL)</td></tr>
<tr class="memdesc:a80190755421d9f1d6f7fbf58fd4d1fb3"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Baud Rate <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a4ff77d6ccbfebb17424682902bd4fda9">REG_SERCOM3_USART_RXPL</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4101400EUL)</td></tr>
<tr class="memdesc:a4ff77d6ccbfebb17424682902bd4fda9"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Receive Pulse Length <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a6b172ec763eacb84740e5bd5b53cebd2">REG_SERCOM3_USART_INTENCLR</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41014014UL)</td></tr>
<tr class="memdesc:a6b172ec763eacb84740e5bd5b53cebd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Interrupt Enable Clear <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a9e142f48e30118dbfeff25a97a35e34c">REG_SERCOM3_USART_INTENSET</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41014016UL)</td></tr>
<tr class="memdesc:a9e142f48e30118dbfeff25a97a35e34c"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Interrupt Enable Set <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a11e1c3a7746c82c632149facba377e75">REG_SERCOM3_USART_INTFLAG</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41014018UL)</td></tr>
<tr class="memdesc:a11e1c3a7746c82c632149facba377e75"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Interrupt Flag Status and Clear <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a22fa45843b13228f8552284c001f0b24">REG_SERCOM3_USART_STATUS</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4101401AUL)</td></tr>
<tr class="memdesc:a22fa45843b13228f8552284c001f0b24"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Status <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#ae573a27fa4d208897d3296d458c6a512">REG_SERCOM3_USART_SYNCBUSY</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4101401CUL)</td></tr>
<tr class="memdesc:ae573a27fa4d208897d3296d458c6a512"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Synchronization Busy <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#a6a6a67b3e65f942052c52c3b1ee49c34">REG_SERCOM3_USART_RXERRCNT</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> *)0x41014020UL)</td></tr>
<tr class="memdesc:a6a6a67b3e65f942052c52c3b1ee49c34"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Receive Error Count <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#acf1f6e3f6bd5bc2e10cba285dae5015c">REG_SERCOM3_USART_LENGTH</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x41014022UL)</td></tr>
<tr class="memdesc:acf1f6e3f6bd5bc2e10cba285dae5015c"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Length <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#ab88c08e5ad88c7630252ee170384ff01">REG_SERCOM3_USART_DATA</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x41014028UL)</td></tr>
<tr class="memdesc:ab88c08e5ad88c7630252ee170384ff01"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Data <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="sercom3_8h.html#aa515f19b55d5bbdbfbb113a972f16abc">REG_SERCOM3_USART_DBGCTRL</a>&#160;&#160;&#160;(*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x41014030UL)</td></tr>
<tr class="memdesc:aa515f19b55d5bbdbfbb113a972f16abc"><td class="mdescLeft">&#160;</td><td class="mdescRight">(SERCOM3) USART Debug Control <br /></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_CLK_REDUCTION</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_DMA</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_FIFO_DEPTH_POWER</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_GCLK_ID_CORE</b>&#160;&#160;&#160;24</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_GCLK_ID_SLOW</b>&#160;&#160;&#160;3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_INT_MSB</b>&#160;&#160;&#160;6</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_I2CM</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_I2CS</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_I2CS_AUTO_ACK</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_I2CS_GROUP_CMD</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_I2CS_SDASETUP_CNT_SIZE</b>&#160;&#160;&#160;8</td></tr>
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<tr class="memitem:ae09c48b48223933d5e195d581d1058ba"><td class="memItemLeft" align="right" valign="top"><a id="ae09c48b48223933d5e195d581d1058ba"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_I2CS_SDASETUP_SIZE</b>&#160;&#160;&#160;4</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_I2CS_SUDAT</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_I2C_FASTMP</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a7d742b64eb73e37976eb13e03c82a4d6"><td class="memItemLeft" align="right" valign="top"><a id="a7d742b64eb73e37976eb13e03c82a4d6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_I2C_HSMODE</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_I2C_SCLSM_MODE</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_I2C_SMB_TIMEOUTS</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a12c0db847be651b0f5deeb7942c3336b"><td class="memItemLeft" align="right" valign="top"><a id="a12c0db847be651b0f5deeb7942c3336b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_I2C_TENBIT_ADR</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_PMSB</b>&#160;&#160;&#160;3</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_RETENTION_SUPPORT</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_SE_CNT</b>&#160;&#160;&#160;1</td></tr>
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<tr class="memitem:a5c1187ca07d0b2cdf06ae033497c15ae"><td class="memItemLeft" align="right" valign="top"><a id="a5c1187ca07d0b2cdf06ae033497c15ae"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_SPI</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_SPI_HW_SS_CTRL</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_SPI_ICSPACE_EXT</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_SPI_OZMO</b>&#160;&#160;&#160;0</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_SPI_WAKE_ON_SSL</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_TTBIT_EXTENSION</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_USART</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_USART_AUTOBAUD</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_USART_COLDET</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_USART_FLOW_CTRL</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_USART_IRDA</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_USART_ISO7816</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_USART_RS485</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_USART_SAMPA_EXT</b>&#160;&#160;&#160;1</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>SERCOM3_USART_SAMPR_EXT</b>&#160;&#160;&#160;1</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Instance description for SERCOM3. </p>
<p>Copyright (c) 2019 Microchip Technology Inc.</p>
<p>\asf_license_start </p>
<p class="definition">Definition in file <a class="el" href="sercom3_8h_source.html">sercom3.h</a>.</p>
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