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111 lines
7.3 KiB
C
111 lines
7.3 KiB
C
/**
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* \file
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*
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* \brief Instance description for TCC1
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*
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* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMD21_TCC1_INSTANCE_
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#define _SAMD21_TCC1_INSTANCE_
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/* ========== Register definition for TCC1 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TCC1_CTRLA (0x42002400U) /**< \brief (TCC1) Control A */
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#define REG_TCC1_CTRLBCLR (0x42002404U) /**< \brief (TCC1) Control B Clear */
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#define REG_TCC1_CTRLBSET (0x42002405U) /**< \brief (TCC1) Control B Set */
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#define REG_TCC1_SYNCBUSY (0x42002408U) /**< \brief (TCC1) Synchronization Busy */
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#define REG_TCC1_FCTRLA (0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
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#define REG_TCC1_FCTRLB (0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
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#define REG_TCC1_DRVCTRL (0x42002418U) /**< \brief (TCC1) Driver Control */
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#define REG_TCC1_DBGCTRL (0x4200241EU) /**< \brief (TCC1) Debug Control */
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#define REG_TCC1_EVCTRL (0x42002420U) /**< \brief (TCC1) Event Control */
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#define REG_TCC1_INTENCLR (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
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#define REG_TCC1_INTENSET (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
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#define REG_TCC1_INTFLAG (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
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#define REG_TCC1_STATUS (0x42002430U) /**< \brief (TCC1) Status */
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#define REG_TCC1_COUNT (0x42002434U) /**< \brief (TCC1) Count */
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#define REG_TCC1_PATT (0x42002438U) /**< \brief (TCC1) Pattern */
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#define REG_TCC1_WAVE (0x4200243CU) /**< \brief (TCC1) Waveform Control */
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#define REG_TCC1_PER (0x42002440U) /**< \brief (TCC1) Period */
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#define REG_TCC1_CC0 (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
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#define REG_TCC1_CC1 (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
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#define REG_TCC1_PATTB (0x42002464U) /**< \brief (TCC1) Pattern Buffer */
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#define REG_TCC1_WAVEB (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
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#define REG_TCC1_PERB (0x4200246CU) /**< \brief (TCC1) Period Buffer */
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#define REG_TCC1_CCB0 (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
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#define REG_TCC1_CCB1 (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
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#else
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#define REG_TCC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TCC1) Control A */
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#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */
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#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */
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#define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */
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#define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */
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#define REG_TCC1_FCTRLB (*(RwReg *)0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */
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#define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418U) /**< \brief (TCC1) Driver Control */
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#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */
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#define REG_TCC1_EVCTRL (*(RwReg *)0x42002420U) /**< \brief (TCC1) Event Control */
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#define REG_TCC1_INTENCLR (*(RwReg *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */
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#define REG_TCC1_INTENSET (*(RwReg *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */
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#define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */
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#define REG_TCC1_STATUS (*(RwReg *)0x42002430U) /**< \brief (TCC1) Status */
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#define REG_TCC1_COUNT (*(RwReg *)0x42002434U) /**< \brief (TCC1) Count */
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#define REG_TCC1_PATT (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */
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#define REG_TCC1_WAVE (*(RwReg *)0x4200243CU) /**< \brief (TCC1) Waveform Control */
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#define REG_TCC1_PER (*(RwReg *)0x42002440U) /**< \brief (TCC1) Period */
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#define REG_TCC1_CC0 (*(RwReg *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */
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#define REG_TCC1_CC1 (*(RwReg *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */
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#define REG_TCC1_PATTB (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */
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#define REG_TCC1_WAVEB (*(RwReg *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */
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#define REG_TCC1_PERB (*(RwReg *)0x4200246CU) /**< \brief (TCC1) Period Buffer */
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#define REG_TCC1_CCB0 (*(RwReg *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */
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#define REG_TCC1_CCB1 (*(RwReg *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance parameters for TCC1 peripheral ========== */
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#define TCC1_CC_NUM 2 // Number of Compare/Capture units
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#define TCC1_DITHERING 1 // Dithering feature implemented
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#define TCC1_DMAC_ID_MC_0 19
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#define TCC1_DMAC_ID_MC_1 20
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#define TCC1_DMAC_ID_MC_LSB 19
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#define TCC1_DMAC_ID_MC_MSB 20
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#define TCC1_DMAC_ID_MC_SIZE 2
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#define TCC1_DMAC_ID_OVF 18 // DMA overflow/underflow/retrigger trigger
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#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented
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#define TCC1_EXT 24 // Coding of implemented extended features
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#define TCC1_GCLK_ID 26 // Index of Generic Clock
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#define TCC1_MASTER 1
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#define TCC1_OTMX 0 // Output Matrix feature implemented
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#define TCC1_OW_NUM 4 // Number of Output Waveforms
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#define TCC1_PG 1 // Pattern Generation feature implemented
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#define TCC1_SIZE 24
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#define TCC1_SWAP 0 // DTI outputs swap feature implemented
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#define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave
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#endif /* _SAMD21_TCC1_INSTANCE_ */
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