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111 lines
5.5 KiB
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111 lines
5.5 KiB
HTML
<!DOCTYPE html PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd">
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<html>
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<!-- This manual describes how to install and use the GNU multiple precision
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arithmetic library, version 6.1.0.
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Copyright 1991, 1993-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document under
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<head>
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<title>Assembly Carry Propagation (GNU MP 6.1.0)</title>
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<meta name="description" content="How to install and use the GNU multiple precision arithmetic library, version 6.1.0.">
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<link href="Assembly-Coding.html#Assembly-Coding" rel="up" title="Assembly Coding">
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<a name="Assembly-Carry-Propagation"></a>
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<div class="header">
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<p>
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Next: <a href="Assembly-Cache-Handling.html#Assembly-Cache-Handling" accesskey="n" rel="next">Assembly Cache Handling</a>, Previous: <a href="Assembly-Basics.html#Assembly-Basics" accesskey="p" rel="prev">Assembly Basics</a>, Up: <a href="Assembly-Coding.html#Assembly-Coding" accesskey="u" rel="up">Assembly Coding</a> [<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="Carry-Propagation"></a>
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<h4 class="subsection">15.8.3 Carry Propagation</h4>
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<a name="index-Assembly-carry-propagation"></a>
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<p>The problem that presents most challenges in GMP is propagating carries from
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one limb to the next. In functions like <code>mpn_addmul_1</code> and
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<code>mpn_add_n</code>, carries are the only dependencies between limb operations.
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</p>
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<p>On processors with carry flags, a straightforward CISC style <code>adc</code> is
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generally best. AMD K6 <code>mpn_addmul_1</code> however is an example of an
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unusual set of circumstances where a branch works out better.
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</p>
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<p>On RISC processors generally an add and compare for overflow is used. This
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sort of thing can be seen in <samp>mpn/generic/aors_n.c</samp>. Some carry
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propagation schemes require 4 instructions, meaning at least 4 cycles per
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limb, but other schemes may use just 1 or 2. On wide superscalar processors
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performance may be completely determined by the number of dependent
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instructions between carry-in and carry-out for each limb.
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</p>
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<p>On vector processors good use can be made of the fact that a carry bit only
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very rarely propagates more than one limb. When adding a single bit to a
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limb, there’s only a carry out if that limb was <code>0xFF…FF</code> which on
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random data will be only 1 in <em>2^mp_bits_per_limb</em>. <samp>mpn/cray/add_n.c</samp> is an example of this, it adds
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all limbs in parallel, adds one set of carry bits in parallel and then only
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rarely needs to fall through to a loop propagating further carries.
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</p>
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<p>On the x86s, GCC (as of version 2.95.2) doesn’t generate particularly good code
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for the RISC style idioms that are necessary to handle carry bits in
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C. Often conditional jumps are generated where <code>adc</code> or <code>sbb</code> forms
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would be better. And so unfortunately almost any loop involving carry bits
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needs to be coded in assembly for best results.
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</p>
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<hr>
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<div class="header">
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<p>
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Next: <a href="Assembly-Cache-Handling.html#Assembly-Cache-Handling" accesskey="n" rel="next">Assembly Cache Handling</a>, Previous: <a href="Assembly-Basics.html#Assembly-Basics" accesskey="p" rel="prev">Assembly Basics</a>, Up: <a href="Assembly-Coding.html#Assembly-Coding" accesskey="u" rel="up">Assembly Coding</a> [<a href="Concept-Index.html#Concept-Index" title="Index" rel="index">Index</a>]</p>
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</body>
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