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<title>Values in Registers (GNU Compiler Collection (GCC) Internals)</title>
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<link href="index.html#SEC_Contents" rel="contents" title="Table of Contents">
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<link href="Leaf-Functions.html#Leaf-Functions" rel="next" title="Leaf Functions">
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<a name="Values-in-Registers"></a>
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<div class="header">
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<p>
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Next: <a href="Leaf-Functions.html#Leaf-Functions" accesskey="n" rel="next">Leaf Functions</a>, Previous: <a href="Allocation-Order.html#Allocation-Order" accesskey="p" rel="prev">Allocation Order</a>, Up: <a href="Registers.html#Registers" accesskey="u" rel="up">Registers</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="How-Values-Fit-in-Registers"></a>
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<h4 class="subsection">18.7.3 How Values Fit in Registers</h4>
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<p>This section discusses the macros that describe which kinds of values
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(specifically, which machine modes) each register can hold, and how many
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consecutive registers are needed for a given mode.
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</p>
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<dl>
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<dt><a name="index-TARGET_005fHARD_005fREGNO_005fNREGS"></a>Target Hook: <em>unsigned int</em> <strong>TARGET_HARD_REGNO_NREGS</strong> <em>(unsigned int <var>regno</var>, machine_mode <var>mode</var>)</em></dt>
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<dd><p>This hook returns the number of consecutive hard registers, starting
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at register number <var>regno</var>, required to hold a value of mode
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<var>mode</var>. This hook must never return zero, even if a register
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cannot hold the requested mode - indicate that with
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<code>TARGET_HARD_REGNO_MODE_OK</code> and/or
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<code>TARGET_CAN_CHANGE_MODE_CLASS</code> instead.
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</p>
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<p>The default definition returns the number of words in <var>mode</var>.
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</p></dd></dl>
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<dl>
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<dt><a name="index-HARD_005fREGNO_005fNREGS_005fHAS_005fPADDING"></a>Macro: <strong>HARD_REGNO_NREGS_HAS_PADDING</strong> <em>(<var>regno</var>, <var>mode</var>)</em></dt>
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<dd><p>A C expression that is nonzero if a value of mode <var>mode</var>, stored
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in memory, ends with padding that causes it to take up more space than
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in registers starting at register number <var>regno</var> (as determined by
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multiplying GCC’s notion of the size of the register when containing
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this mode by the number of registers returned by
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<code>TARGET_HARD_REGNO_NREGS</code>). By default this is zero.
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</p>
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<p>For example, if a floating-point value is stored in three 32-bit
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registers but takes up 128 bits in memory, then this would be
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nonzero.
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</p>
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<p>This macros only needs to be defined if there are cases where
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<code>subreg_get_info</code>
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would otherwise wrongly determine that a <code>subreg</code> can be
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represented by an offset to the register number, when in fact such a
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<code>subreg</code> would contain some of the padding not stored in
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registers and so not be representable.
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</p></dd></dl>
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<dl>
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<dt><a name="index-HARD_005fREGNO_005fNREGS_005fWITH_005fPADDING"></a>Macro: <strong>HARD_REGNO_NREGS_WITH_PADDING</strong> <em>(<var>regno</var>, <var>mode</var>)</em></dt>
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<dd><p>For values of <var>regno</var> and <var>mode</var> for which
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<code>HARD_REGNO_NREGS_HAS_PADDING</code> returns nonzero, a C expression
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returning the greater number of registers required to hold the value
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including any padding. In the example above, the value would be four.
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</p></dd></dl>
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<dl>
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<dt><a name="index-REGMODE_005fNATURAL_005fSIZE-2"></a>Macro: <strong>REGMODE_NATURAL_SIZE</strong> <em>(<var>mode</var>)</em></dt>
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<dd><p>Define this macro if the natural size of registers that hold values
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of mode <var>mode</var> is not the word size. It is a C expression that
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should give the natural size in bytes for the specified mode. It is
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used by the register allocator to try to optimize its results. This
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happens for example on SPARC 64-bit where the natural size of
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floating-point registers is still 32-bit.
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</p></dd></dl>
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<dl>
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<dt><a name="index-TARGET_005fHARD_005fREGNO_005fMODE_005fOK"></a>Target Hook: <em>bool</em> <strong>TARGET_HARD_REGNO_MODE_OK</strong> <em>(unsigned int <var>regno</var>, machine_mode <var>mode</var>)</em></dt>
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<dd><p>This hook returns true if it is permissible to store a value
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of mode <var>mode</var> in hard register number <var>regno</var> (or in several
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registers starting with that one). The default definition returns true
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unconditionally.
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</p>
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<p>You need not include code to check for the numbers of fixed registers,
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because the allocation mechanism considers them to be always occupied.
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</p>
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<a name="index-register-pairs"></a>
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<p>On some machines, double-precision values must be kept in even/odd
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register pairs. You can implement that by defining this hook to reject
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odd register numbers for such modes.
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</p>
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<p>The minimum requirement for a mode to be OK in a register is that the
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‘<samp>mov<var>mode</var></samp>’ instruction pattern support moves between the
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register and other hard register in the same class and that moving a
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value into the register and back out not alter it.
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</p>
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<p>Since the same instruction used to move <code>word_mode</code> will work for
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all narrower integer modes, it is not necessary on any machine for
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this hook to distinguish between these modes, provided you define
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patterns ‘<samp>movhi</samp>’, etc., to take advantage of this. This is
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useful because of the interaction between <code>TARGET_HARD_REGNO_MODE_OK</code>
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and <code>TARGET_MODES_TIEABLE_P</code>; it is very desirable for all integer
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modes to be tieable.
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</p>
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<p>Many machines have special registers for floating point arithmetic.
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Often people assume that floating point machine modes are allowed only
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in floating point registers. This is not true. Any registers that
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can hold integers can safely <em>hold</em> a floating point machine
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mode, whether or not floating arithmetic can be done on it in those
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registers. Integer move instructions can be used to move the values.
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</p>
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<p>On some machines, though, the converse is true: fixed-point machine
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modes may not go in floating registers. This is true if the floating
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registers normalize any value stored in them, because storing a
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non-floating value there would garble it. In this case,
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<code>TARGET_HARD_REGNO_MODE_OK</code> should reject fixed-point machine modes in
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floating registers. But if the floating registers do not automatically
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normalize, if you can store any bit pattern in one and retrieve it
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unchanged without a trap, then any machine mode may go in a floating
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register, so you can define this hook to say so.
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</p>
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<p>The primary significance of special floating registers is rather that
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they are the registers acceptable in floating point arithmetic
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instructions. However, this is of no concern to
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<code>TARGET_HARD_REGNO_MODE_OK</code>. You handle it by writing the proper
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constraints for those instructions.
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</p>
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<p>On some machines, the floating registers are especially slow to access,
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so that it is better to store a value in a stack frame than in such a
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register if floating point arithmetic is not being done. As long as the
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floating registers are not in class <code>GENERAL_REGS</code>, they will not
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be used unless some pattern’s constraint asks for one.
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</p></dd></dl>
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<dl>
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<dt><a name="index-HARD_005fREGNO_005fRENAME_005fOK"></a>Macro: <strong>HARD_REGNO_RENAME_OK</strong> <em>(<var>from</var>, <var>to</var>)</em></dt>
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<dd><p>A C expression that is nonzero if it is OK to rename a hard register
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<var>from</var> to another hard register <var>to</var>.
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</p>
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<p>One common use of this macro is to prevent renaming of a register to
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another register that is not saved by a prologue in an interrupt
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handler.
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</p>
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<p>The default is always nonzero.
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</p></dd></dl>
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<dl>
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<dt><a name="index-TARGET_005fMODES_005fTIEABLE_005fP"></a>Target Hook: <em>bool</em> <strong>TARGET_MODES_TIEABLE_P</strong> <em>(machine_mode <var>mode1</var>, machine_mode <var>mode2</var>)</em></dt>
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<dd><p>This hook returns true if a value of mode <var>mode1</var> is accessible
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in mode <var>mode2</var> without copying.
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</p>
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<p>If <code>TARGET_HARD_REGNO_MODE_OK (<var>r</var>, <var>mode1</var>)</code> and
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<code>TARGET_HARD_REGNO_MODE_OK (<var>r</var>, <var>mode2</var>)</code> are always
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the same for any <var>r</var>, then
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<code>TARGET_MODES_TIEABLE_P (<var>mode1</var>, <var>mode2</var>)</code>
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should be true. If they differ for any <var>r</var>, you should define
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this hook to return false unless some other mechanism ensures the
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accessibility of the value in a narrower mode.
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</p>
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<p>You should define this hook to return true in as many cases as
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possible since doing so will allow GCC to perform better register
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allocation. The default definition returns true unconditionally.
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</p></dd></dl>
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<dl>
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<dt><a name="index-TARGET_005fHARD_005fREGNO_005fSCRATCH_005fOK"></a>Target Hook: <em>bool</em> <strong>TARGET_HARD_REGNO_SCRATCH_OK</strong> <em>(unsigned int <var>regno</var>)</em></dt>
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<dd><p>This target hook should return <code>true</code> if it is OK to use a hard register
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<var>regno</var> as scratch reg in peephole2.
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</p>
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<p>One common use of this macro is to prevent using of a register that
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is not saved by a prologue in an interrupt handler.
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</p>
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<p>The default version of this hook always returns <code>true</code>.
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</p></dd></dl>
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<dl>
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<dt><a name="index-AVOID_005fCCMODE_005fCOPIES"></a>Macro: <strong>AVOID_CCMODE_COPIES</strong></dt>
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<dd><p>Define this macro if the compiler should avoid copies to/from <code>CCmode</code>
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registers. You should only define this macro if support for copying to/from
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<code>CCmode</code> is incomplete.
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</p></dd></dl>
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<hr>
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<div class="header">
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<p>
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Next: <a href="Leaf-Functions.html#Leaf-Functions" accesskey="n" rel="next">Leaf Functions</a>, Previous: <a href="Allocation-Order.html#Allocation-Order" accesskey="p" rel="prev">Allocation Order</a>, Up: <a href="Registers.html#Registers" accesskey="u" rel="up">Registers</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="Option-Index.html#Option-Index" title="Index" rel="index">Index</a>]</p>
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