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<title>M32R-Opts (Using as)</title>
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<a name="M32R_002dOpts"></a>
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<div class="header">
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<p>
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Next: <a href="M32R_002dDirectives.html#M32R_002dDirectives" accesskey="n" rel="next">M32R-Directives</a>, Up: <a href="M32R_002dDependent.html#M32R_002dDependent" accesskey="u" rel="up">M32R-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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</div>
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<hr>
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<a name="M32R-Options"></a>
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<h4 class="subsection">9.20.1 M32R Options</h4>
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<a name="index-options_002c-M32R"></a>
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<a name="index-M32R-options"></a>
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<p>The Renesas M32R version of <code>as</code> has a few machine
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dependent options:
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</p>
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<dl compact="compact">
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<dt><code>-m32rx</code></dt>
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<dd><a name="index-_002dm32rx-option_002c-M32RX"></a>
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<a name="index-architecture-options_002c-M32RX"></a>
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<a name="index-M32R-architecture-options"></a>
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<p><code>as</code> can assemble code for several different members of the
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Renesas M32R family. Normally the default is to assemble code for
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the M32R microprocessor. This option may be used to change the default
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to the M32RX microprocessor, which adds some more instructions to the
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basic M32R instruction set, and some additional parameters to some of
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the original instructions.
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</p>
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</dd>
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<dt><code>-m32r2</code></dt>
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<dd><a name="index-_002dm32rx-option_002c-M32R2"></a>
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<a name="index-architecture-options_002c-M32R2"></a>
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<a name="index-M32R-architecture-options-1"></a>
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<p>This option changes the target processor to the M32R2
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microprocessor.
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</p>
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</dd>
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<dt><code>-m32r</code></dt>
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<dd><a name="index-_002dm32r-option_002c-M32R"></a>
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<a name="index-architecture-options_002c-M32R"></a>
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<a name="index-M32R-architecture-options-2"></a>
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<p>This option can be used to restore the assembler’s default behaviour of
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assembling for the M32R microprocessor. This can be useful if the
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default has been changed by a previous command-line option.
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</p>
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</dd>
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<dt><code>-little</code></dt>
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<dd><a name="index-_002dlittle-option_002c-M32R"></a>
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<p>This option tells the assembler to produce little-endian code and
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data. The default is dependent upon how the toolchain was
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configured.
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</p>
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</dd>
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<dt><code>-EL</code></dt>
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<dd><a name="index-_002dEL-option_002c-M32R"></a>
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<p>This is a synonym for <em>-little</em>.
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</p>
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</dd>
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<dt><code>-big</code></dt>
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<dd><a name="index-_002dbig-option_002c-M32R"></a>
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<p>This option tells the assembler to produce big-endian code and
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data.
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</p>
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</dd>
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<dt><code>-EB</code></dt>
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<dd><a name="index-_002dEB-option_002c-M32R"></a>
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<p>This is a synonym for <em>-big</em>.
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</p>
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</dd>
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<dt><code>-KPIC</code></dt>
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<dd><a name="index-_002dKPIC-option_002c-M32R"></a>
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<a name="index-PIC-code-generation-for-M32R"></a>
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<p>This option specifies that the output of the assembler should be
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marked as position-independent code (PIC).
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</p>
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</dd>
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<dt><code>-parallel</code></dt>
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<dd><a name="index-_002dparallel-option_002c-M32RX"></a>
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<p>This option tells the assembler to attempts to combine two sequential
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instructions into a single, parallel instruction, where it is legal to
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do so.
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</p>
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</dd>
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<dt><code>-no-parallel</code></dt>
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<dd><a name="index-_002dno_002dparallel-option_002c-M32RX"></a>
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<p>This option disables a previously enabled <em>-parallel</em> option.
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</p>
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</dd>
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<dt><code>-no-bitinst</code></dt>
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<dd><a name="index-_002dno_002dbitinst_002c-M32R2"></a>
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<p>This option disables the support for the extended bit-field
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instructions provided by the M32R2. If this support needs to be
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re-enabled the <em>-bitinst</em> switch can be used to restore it.
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</p>
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</dd>
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<dt><code>-O</code></dt>
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<dd><a name="index-_002dO-option_002c-M32RX"></a>
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<p>This option tells the assembler to attempt to optimize the
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instructions that it produces. This includes filling delay slots and
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converting sequential instructions into parallel ones. This option
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implies <em>-parallel</em>.
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</p>
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</dd>
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<dt><code>-warn-explicit-parallel-conflicts</code></dt>
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<dd><a name="index-_002dwarn_002dexplicit_002dparallel_002dconflicts-option_002c-M32RX"></a>
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<p>Instructs <code>as</code> to produce warning messages when
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questionable parallel instructions are encountered. This option is
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enabled by default, but <code>gcc</code> disables it when it invokes
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<code>as</code> directly. Questionable instructions are those whose
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behaviour would be different if they were executed sequentially. For
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example the code fragment ‘<samp>mv r1, r2 || mv r3, r1</samp>’ produces a
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different result from ‘<samp>mv r1, r2 \n mv r3, r1</samp>’ since the former
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moves r1 into r3 and then r2 into r1, whereas the later moves r2 into r1
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and r3.
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</p>
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</dd>
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<dt><code>-Wp</code></dt>
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<dd><a name="index-_002dWp-option_002c-M32RX"></a>
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<p>This is a shorter synonym for the <em>-warn-explicit-parallel-conflicts</em>
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option.
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</p>
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</dd>
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<dt><code>-no-warn-explicit-parallel-conflicts</code></dt>
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<dd><a name="index-_002dno_002dwarn_002dexplicit_002dparallel_002dconflicts-option_002c-M32RX"></a>
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<p>Instructs <code>as</code> not to produce warning messages when
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questionable parallel instructions are encountered.
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</p>
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</dd>
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<dt><code>-Wnp</code></dt>
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<dd><a name="index-_002dWnp-option_002c-M32RX"></a>
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<p>This is a shorter synonym for the <em>-no-warn-explicit-parallel-conflicts</em>
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option.
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</p>
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</dd>
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<dt><code>-ignore-parallel-conflicts</code></dt>
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<dd><a name="index-_002dignore_002dparallel_002dconflicts-option_002c-M32RX"></a>
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<p>This option tells the assembler’s to stop checking parallel
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instructions for constraint violations. This ability is provided for
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hardware vendors testing chip designs and should not be used under
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normal circumstances.
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</p>
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</dd>
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<dt><code>-no-ignore-parallel-conflicts</code></dt>
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<dd><a name="index-_002dno_002dignore_002dparallel_002dconflicts-option_002c-M32RX"></a>
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<p>This option restores the assembler’s default behaviour of checking
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parallel instructions to detect constraint violations.
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</p>
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</dd>
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<dt><code>-Ip</code></dt>
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<dd><a name="index-_002dIp-option_002c-M32RX"></a>
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<p>This is a shorter synonym for the <em>-ignore-parallel-conflicts</em>
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option.
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</p>
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</dd>
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<dt><code>-nIp</code></dt>
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<dd><a name="index-_002dnIp-option_002c-M32RX"></a>
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<p>This is a shorter synonym for the <em>-no-ignore-parallel-conflicts</em>
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option.
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</p>
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</dd>
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<dt><code>-warn-unmatched-high</code></dt>
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<dd><a name="index-_002dwarn_002dunmatched_002dhigh-option_002c-M32R"></a>
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<p>This option tells the assembler to produce a warning message if a
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<code>.high</code> pseudo op is encountered without a matching <code>.low</code>
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pseudo op. The presence of such an unmatched pseudo op usually
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indicates a programming error.
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</p>
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</dd>
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<dt><code>-no-warn-unmatched-high</code></dt>
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<dd><a name="index-_002dno_002dwarn_002dunmatched_002dhigh-option_002c-M32R"></a>
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<p>Disables a previously enabled <em>-warn-unmatched-high</em> option.
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</p>
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</dd>
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<dt><code>-Wuh</code></dt>
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<dd><a name="index-_002dWuh-option_002c-M32RX"></a>
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<p>This is a shorter synonym for the <em>-warn-unmatched-high</em> option.
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</p>
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</dd>
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<dt><code>-Wnuh</code></dt>
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<dd><a name="index-_002dWnuh-option_002c-M32RX"></a>
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<p>This is a shorter synonym for the <em>-no-warn-unmatched-high</em> option.
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</p>
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</dd>
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</dl>
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<hr>
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<div class="header">
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<p>
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Next: <a href="M32R_002dDirectives.html#M32R_002dDirectives" accesskey="n" rel="next">M32R-Directives</a>, Up: <a href="M32R_002dDependent.html#M32R_002dDependent" accesskey="u" rel="up">M32R-Dependent</a> [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>][<a href="AS-Index.html#AS-Index" title="Index" rel="index">Index</a>]</p>
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