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419 lines
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419 lines
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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/sercom4.h File Reference</title>
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<div id="projectname">SAME54P20A Test Project
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<a href="#define-members">Macros</a> </div>
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<div class="title">sercom4.h File Reference</div> </div>
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</div><!--header-->
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<div class="contents">
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<p>Instance description for SERCOM4.
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<a href="#details">More...</a></p>
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<p><a href="sercom4_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a550f3213a3631f445a54564ed317b4a7"><td class="memItemLeft" align="right" valign="top"><a id="a550f3213a3631f445a54564ed317b4a7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a550f3213a3631f445a54564ed317b4a7">REG_SERCOM4_I2CM_CTRLA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000000UL)</td></tr>
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<tr class="memdesc:a550f3213a3631f445a54564ed317b4a7"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CM Control A <br /></td></tr>
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<tr class="separator:a550f3213a3631f445a54564ed317b4a7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af9eb4408c5d25ede4647ff23a2502be6"><td class="memItemLeft" align="right" valign="top"><a id="af9eb4408c5d25ede4647ff23a2502be6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#af9eb4408c5d25ede4647ff23a2502be6">REG_SERCOM4_I2CM_CTRLB</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000004UL)</td></tr>
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<tr class="memdesc:af9eb4408c5d25ede4647ff23a2502be6"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CM Control B <br /></td></tr>
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<tr class="separator:af9eb4408c5d25ede4647ff23a2502be6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a40e3ec09c7a902ae7cbb87cfaec84f89"><td class="memItemLeft" align="right" valign="top"><a id="a40e3ec09c7a902ae7cbb87cfaec84f89"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a40e3ec09c7a902ae7cbb87cfaec84f89">REG_SERCOM4_I2CM_CTRLC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000008UL)</td></tr>
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<tr class="memdesc:a40e3ec09c7a902ae7cbb87cfaec84f89"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CM Control C <br /></td></tr>
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<tr class="separator:a40e3ec09c7a902ae7cbb87cfaec84f89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2ad881e875b3133fb623f5983485296d"><td class="memItemLeft" align="right" valign="top"><a id="a2ad881e875b3133fb623f5983485296d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a2ad881e875b3133fb623f5983485296d">REG_SERCOM4_I2CM_BAUD</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4300000CUL)</td></tr>
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<tr class="memdesc:a2ad881e875b3133fb623f5983485296d"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CM Baud Rate <br /></td></tr>
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<tr class="separator:a2ad881e875b3133fb623f5983485296d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a61a97abaffd4ef3887cc73f7e91a2b58"><td class="memItemLeft" align="right" valign="top"><a id="a61a97abaffd4ef3887cc73f7e91a2b58"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a61a97abaffd4ef3887cc73f7e91a2b58">REG_SERCOM4_I2CM_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000014UL)</td></tr>
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<tr class="memdesc:a61a97abaffd4ef3887cc73f7e91a2b58"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CM Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a61a97abaffd4ef3887cc73f7e91a2b58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a777f1a8763d887c585a2bbd513b4013d"><td class="memItemLeft" align="right" valign="top"><a id="a777f1a8763d887c585a2bbd513b4013d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a777f1a8763d887c585a2bbd513b4013d">REG_SERCOM4_I2CM_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000016UL)</td></tr>
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<tr class="memdesc:a777f1a8763d887c585a2bbd513b4013d"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CM Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a777f1a8763d887c585a2bbd513b4013d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a010320e7844c6a7b23225e447878b526"><td class="memItemLeft" align="right" valign="top"><a id="a010320e7844c6a7b23225e447878b526"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a010320e7844c6a7b23225e447878b526">REG_SERCOM4_I2CM_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000018UL)</td></tr>
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<tr class="memdesc:a010320e7844c6a7b23225e447878b526"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CM Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:a010320e7844c6a7b23225e447878b526"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1931d47b691df4ce9232af4f1c6ff20c"><td class="memItemLeft" align="right" valign="top"><a id="a1931d47b691df4ce9232af4f1c6ff20c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a1931d47b691df4ce9232af4f1c6ff20c">REG_SERCOM4_I2CM_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4300001AUL)</td></tr>
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<tr class="memdesc:a1931d47b691df4ce9232af4f1c6ff20c"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CM Status <br /></td></tr>
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<tr class="separator:a1931d47b691df4ce9232af4f1c6ff20c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae07a44dfbfa607bb9db6a1b43737aba1"><td class="memItemLeft" align="right" valign="top"><a id="ae07a44dfbfa607bb9db6a1b43737aba1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#ae07a44dfbfa607bb9db6a1b43737aba1">REG_SERCOM4_I2CM_SYNCBUSY</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4300001CUL)</td></tr>
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<tr class="memdesc:ae07a44dfbfa607bb9db6a1b43737aba1"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CM Synchronization Busy <br /></td></tr>
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<tr class="separator:ae07a44dfbfa607bb9db6a1b43737aba1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae1a703b5b946bcdbaf469edf0183d4ab"><td class="memItemLeft" align="right" valign="top"><a id="ae1a703b5b946bcdbaf469edf0183d4ab"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#ae1a703b5b946bcdbaf469edf0183d4ab">REG_SERCOM4_I2CM_ADDR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000024UL)</td></tr>
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<tr class="memdesc:ae1a703b5b946bcdbaf469edf0183d4ab"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CM Address <br /></td></tr>
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<tr class="separator:ae1a703b5b946bcdbaf469edf0183d4ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9e0001a42612c67a6b697abe11a57b63"><td class="memItemLeft" align="right" valign="top"><a id="a9e0001a42612c67a6b697abe11a57b63"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a9e0001a42612c67a6b697abe11a57b63">REG_SERCOM4_I2CM_DATA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000028UL)</td></tr>
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<tr class="memdesc:a9e0001a42612c67a6b697abe11a57b63"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CM Data <br /></td></tr>
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<tr class="separator:a9e0001a42612c67a6b697abe11a57b63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a316159b4a7e50ffe5309de5a5e1a0b39"><td class="memItemLeft" align="right" valign="top"><a id="a316159b4a7e50ffe5309de5a5e1a0b39"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a316159b4a7e50ffe5309de5a5e1a0b39">REG_SERCOM4_I2CM_DBGCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000030UL)</td></tr>
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<tr class="memdesc:a316159b4a7e50ffe5309de5a5e1a0b39"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CM Debug Control <br /></td></tr>
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<tr class="separator:a316159b4a7e50ffe5309de5a5e1a0b39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afdedbeed55c9f320bc73bc39771ac3b0"><td class="memItemLeft" align="right" valign="top"><a id="afdedbeed55c9f320bc73bc39771ac3b0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#afdedbeed55c9f320bc73bc39771ac3b0">REG_SERCOM4_I2CS_CTRLA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000000UL)</td></tr>
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<tr class="memdesc:afdedbeed55c9f320bc73bc39771ac3b0"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CS Control A <br /></td></tr>
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<tr class="separator:afdedbeed55c9f320bc73bc39771ac3b0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae1525725545d15fc7f9d5ff7c7b94cfa"><td class="memItemLeft" align="right" valign="top"><a id="ae1525725545d15fc7f9d5ff7c7b94cfa"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#ae1525725545d15fc7f9d5ff7c7b94cfa">REG_SERCOM4_I2CS_CTRLB</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000004UL)</td></tr>
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<tr class="memdesc:ae1525725545d15fc7f9d5ff7c7b94cfa"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CS Control B <br /></td></tr>
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<tr class="separator:ae1525725545d15fc7f9d5ff7c7b94cfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a075610852707603038abb3354a5696dc"><td class="memItemLeft" align="right" valign="top"><a id="a075610852707603038abb3354a5696dc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a075610852707603038abb3354a5696dc">REG_SERCOM4_I2CS_CTRLC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000008UL)</td></tr>
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<tr class="memdesc:a075610852707603038abb3354a5696dc"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CS Control C <br /></td></tr>
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<tr class="separator:a075610852707603038abb3354a5696dc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a643ab316d2945f17ed767706ffef71d6"><td class="memItemLeft" align="right" valign="top"><a id="a643ab316d2945f17ed767706ffef71d6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a643ab316d2945f17ed767706ffef71d6">REG_SERCOM4_I2CS_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000014UL)</td></tr>
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<tr class="memdesc:a643ab316d2945f17ed767706ffef71d6"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CS Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a643ab316d2945f17ed767706ffef71d6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7e5bdf43340a06e0bc47e015c7d013be"><td class="memItemLeft" align="right" valign="top"><a id="a7e5bdf43340a06e0bc47e015c7d013be"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a7e5bdf43340a06e0bc47e015c7d013be">REG_SERCOM4_I2CS_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000016UL)</td></tr>
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<tr class="memdesc:a7e5bdf43340a06e0bc47e015c7d013be"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CS Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a7e5bdf43340a06e0bc47e015c7d013be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af73cec47743212ed53697e039266f244"><td class="memItemLeft" align="right" valign="top"><a id="af73cec47743212ed53697e039266f244"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#af73cec47743212ed53697e039266f244">REG_SERCOM4_I2CS_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000018UL)</td></tr>
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<tr class="memdesc:af73cec47743212ed53697e039266f244"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CS Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:af73cec47743212ed53697e039266f244"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d12547c5467b2d2608c571c4bee3975"><td class="memItemLeft" align="right" valign="top"><a id="a2d12547c5467b2d2608c571c4bee3975"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a2d12547c5467b2d2608c571c4bee3975">REG_SERCOM4_I2CS_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4300001AUL)</td></tr>
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<tr class="memdesc:a2d12547c5467b2d2608c571c4bee3975"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CS Status <br /></td></tr>
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<tr class="separator:a2d12547c5467b2d2608c571c4bee3975"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a33dad4a8d9debcf16bfcab31c2e89e62"><td class="memItemLeft" align="right" valign="top"><a id="a33dad4a8d9debcf16bfcab31c2e89e62"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a33dad4a8d9debcf16bfcab31c2e89e62">REG_SERCOM4_I2CS_SYNCBUSY</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4300001CUL)</td></tr>
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<tr class="memdesc:a33dad4a8d9debcf16bfcab31c2e89e62"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CS Synchronization Busy <br /></td></tr>
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<tr class="separator:a33dad4a8d9debcf16bfcab31c2e89e62"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab8d4bf1ec3f4d1c89e12ffa6e04c2201"><td class="memItemLeft" align="right" valign="top"><a id="ab8d4bf1ec3f4d1c89e12ffa6e04c2201"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#ab8d4bf1ec3f4d1c89e12ffa6e04c2201">REG_SERCOM4_I2CS_LENGTH</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x43000022UL)</td></tr>
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<tr class="memdesc:ab8d4bf1ec3f4d1c89e12ffa6e04c2201"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CS Length <br /></td></tr>
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<tr class="separator:ab8d4bf1ec3f4d1c89e12ffa6e04c2201"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a43a836e2a2764285506616139125f273"><td class="memItemLeft" align="right" valign="top"><a id="a43a836e2a2764285506616139125f273"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a43a836e2a2764285506616139125f273">REG_SERCOM4_I2CS_ADDR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000024UL)</td></tr>
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<tr class="memdesc:a43a836e2a2764285506616139125f273"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CS Address <br /></td></tr>
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<tr class="separator:a43a836e2a2764285506616139125f273"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aecaad25ad8cfa946b245cfcd5a7cb654"><td class="memItemLeft" align="right" valign="top"><a id="aecaad25ad8cfa946b245cfcd5a7cb654"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#aecaad25ad8cfa946b245cfcd5a7cb654">REG_SERCOM4_I2CS_DATA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000028UL)</td></tr>
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<tr class="memdesc:aecaad25ad8cfa946b245cfcd5a7cb654"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) I2CS Data <br /></td></tr>
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<tr class="separator:aecaad25ad8cfa946b245cfcd5a7cb654"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4853cae6bdf04371f2ee804cae01ff8f"><td class="memItemLeft" align="right" valign="top"><a id="a4853cae6bdf04371f2ee804cae01ff8f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a4853cae6bdf04371f2ee804cae01ff8f">REG_SERCOM4_SPI_CTRLA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000000UL)</td></tr>
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<tr class="memdesc:a4853cae6bdf04371f2ee804cae01ff8f"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Control A <br /></td></tr>
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<tr class="separator:a4853cae6bdf04371f2ee804cae01ff8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac92b41a54e723ac6d183f96ba49336a3"><td class="memItemLeft" align="right" valign="top"><a id="ac92b41a54e723ac6d183f96ba49336a3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#ac92b41a54e723ac6d183f96ba49336a3">REG_SERCOM4_SPI_CTRLB</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000004UL)</td></tr>
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<tr class="memdesc:ac92b41a54e723ac6d183f96ba49336a3"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Control B <br /></td></tr>
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<tr class="separator:ac92b41a54e723ac6d183f96ba49336a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaa7a08e7579fbcc2fb53351a3933117c"><td class="memItemLeft" align="right" valign="top"><a id="aaa7a08e7579fbcc2fb53351a3933117c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#aaa7a08e7579fbcc2fb53351a3933117c">REG_SERCOM4_SPI_CTRLC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000008UL)</td></tr>
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<tr class="memdesc:aaa7a08e7579fbcc2fb53351a3933117c"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Control C <br /></td></tr>
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<tr class="separator:aaa7a08e7579fbcc2fb53351a3933117c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6270d019e5df72220d97e89b8f4e27b9"><td class="memItemLeft" align="right" valign="top"><a id="a6270d019e5df72220d97e89b8f4e27b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a6270d019e5df72220d97e89b8f4e27b9">REG_SERCOM4_SPI_BAUD</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4300000CUL)</td></tr>
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<tr class="memdesc:a6270d019e5df72220d97e89b8f4e27b9"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Baud Rate <br /></td></tr>
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<tr class="separator:a6270d019e5df72220d97e89b8f4e27b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a359cec85b7c846125ff8dd4810997bfe"><td class="memItemLeft" align="right" valign="top"><a id="a359cec85b7c846125ff8dd4810997bfe"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a359cec85b7c846125ff8dd4810997bfe">REG_SERCOM4_SPI_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000014UL)</td></tr>
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<tr class="memdesc:a359cec85b7c846125ff8dd4810997bfe"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a359cec85b7c846125ff8dd4810997bfe"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7d2f36819ac2afa9df7461e3d2ae40aa"><td class="memItemLeft" align="right" valign="top"><a id="a7d2f36819ac2afa9df7461e3d2ae40aa"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a7d2f36819ac2afa9df7461e3d2ae40aa">REG_SERCOM4_SPI_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000016UL)</td></tr>
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<tr class="memdesc:a7d2f36819ac2afa9df7461e3d2ae40aa"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a7d2f36819ac2afa9df7461e3d2ae40aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2dba5b46dd449a3e311fe76cc4cb5e86"><td class="memItemLeft" align="right" valign="top"><a id="a2dba5b46dd449a3e311fe76cc4cb5e86"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a2dba5b46dd449a3e311fe76cc4cb5e86">REG_SERCOM4_SPI_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000018UL)</td></tr>
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<tr class="memdesc:a2dba5b46dd449a3e311fe76cc4cb5e86"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:a2dba5b46dd449a3e311fe76cc4cb5e86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad7d69154a4648de95c3eaf101759907b"><td class="memItemLeft" align="right" valign="top"><a id="ad7d69154a4648de95c3eaf101759907b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#ad7d69154a4648de95c3eaf101759907b">REG_SERCOM4_SPI_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4300001AUL)</td></tr>
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<tr class="memdesc:ad7d69154a4648de95c3eaf101759907b"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Status <br /></td></tr>
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<tr class="separator:ad7d69154a4648de95c3eaf101759907b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a99b6576e47cec04bd50208de10e30817"><td class="memItemLeft" align="right" valign="top"><a id="a99b6576e47cec04bd50208de10e30817"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a99b6576e47cec04bd50208de10e30817">REG_SERCOM4_SPI_SYNCBUSY</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4300001CUL)</td></tr>
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<tr class="memdesc:a99b6576e47cec04bd50208de10e30817"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Synchronization Busy <br /></td></tr>
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<tr class="separator:a99b6576e47cec04bd50208de10e30817"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab15c6538b197a15c3bfa640cff465698"><td class="memItemLeft" align="right" valign="top"><a id="ab15c6538b197a15c3bfa640cff465698"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#ab15c6538b197a15c3bfa640cff465698">REG_SERCOM4_SPI_LENGTH</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x43000022UL)</td></tr>
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<tr class="memdesc:ab15c6538b197a15c3bfa640cff465698"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Length <br /></td></tr>
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<tr class="separator:ab15c6538b197a15c3bfa640cff465698"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a213f4cf7cbef27b723a6c31ab37c7732"><td class="memItemLeft" align="right" valign="top"><a id="a213f4cf7cbef27b723a6c31ab37c7732"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a213f4cf7cbef27b723a6c31ab37c7732">REG_SERCOM4_SPI_ADDR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000024UL)</td></tr>
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<tr class="memdesc:a213f4cf7cbef27b723a6c31ab37c7732"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Address <br /></td></tr>
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<tr class="separator:a213f4cf7cbef27b723a6c31ab37c7732"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad34eed9d64d09397438cfc8a554b5384"><td class="memItemLeft" align="right" valign="top"><a id="ad34eed9d64d09397438cfc8a554b5384"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#ad34eed9d64d09397438cfc8a554b5384">REG_SERCOM4_SPI_DATA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000028UL)</td></tr>
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<tr class="memdesc:ad34eed9d64d09397438cfc8a554b5384"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Data <br /></td></tr>
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<tr class="separator:ad34eed9d64d09397438cfc8a554b5384"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abfb9999da10d5112b1e5ac3437eaf844"><td class="memItemLeft" align="right" valign="top"><a id="abfb9999da10d5112b1e5ac3437eaf844"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#abfb9999da10d5112b1e5ac3437eaf844">REG_SERCOM4_SPI_DBGCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000030UL)</td></tr>
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<tr class="memdesc:abfb9999da10d5112b1e5ac3437eaf844"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) SPI Debug Control <br /></td></tr>
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<tr class="separator:abfb9999da10d5112b1e5ac3437eaf844"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afcce57a4632235518671d7febdb37f4a"><td class="memItemLeft" align="right" valign="top"><a id="afcce57a4632235518671d7febdb37f4a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#afcce57a4632235518671d7febdb37f4a">REG_SERCOM4_USART_CTRLA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000000UL)</td></tr>
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<tr class="memdesc:afcce57a4632235518671d7febdb37f4a"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Control A <br /></td></tr>
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<tr class="separator:afcce57a4632235518671d7febdb37f4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3ec0da15fd3a7c0da544c7f2ab82ac34"><td class="memItemLeft" align="right" valign="top"><a id="a3ec0da15fd3a7c0da544c7f2ab82ac34"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a3ec0da15fd3a7c0da544c7f2ab82ac34">REG_SERCOM4_USART_CTRLB</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000004UL)</td></tr>
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<tr class="memdesc:a3ec0da15fd3a7c0da544c7f2ab82ac34"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Control B <br /></td></tr>
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<tr class="separator:a3ec0da15fd3a7c0da544c7f2ab82ac34"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a81bf32fd75058060e88c9058ab226622"><td class="memItemLeft" align="right" valign="top"><a id="a81bf32fd75058060e88c9058ab226622"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a81bf32fd75058060e88c9058ab226622">REG_SERCOM4_USART_CTRLC</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000008UL)</td></tr>
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<tr class="memdesc:a81bf32fd75058060e88c9058ab226622"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Control C <br /></td></tr>
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<tr class="separator:a81bf32fd75058060e88c9058ab226622"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a01f1cef1997977e01d81e4b3094a8fe6"><td class="memItemLeft" align="right" valign="top"><a id="a01f1cef1997977e01d81e4b3094a8fe6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a01f1cef1997977e01d81e4b3094a8fe6">REG_SERCOM4_USART_BAUD</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4300000CUL)</td></tr>
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<tr class="memdesc:a01f1cef1997977e01d81e4b3094a8fe6"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Baud Rate <br /></td></tr>
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<tr class="separator:a01f1cef1997977e01d81e4b3094a8fe6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad99f8d050693f7ea0f59d78f08e8144b"><td class="memItemLeft" align="right" valign="top"><a id="ad99f8d050693f7ea0f59d78f08e8144b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#ad99f8d050693f7ea0f59d78f08e8144b">REG_SERCOM4_USART_RXPL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4300000EUL)</td></tr>
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<tr class="memdesc:ad99f8d050693f7ea0f59d78f08e8144b"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Receive Pulse Length <br /></td></tr>
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<tr class="separator:ad99f8d050693f7ea0f59d78f08e8144b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a85c40fbdd0c0fea44937399dda7939a6"><td class="memItemLeft" align="right" valign="top"><a id="a85c40fbdd0c0fea44937399dda7939a6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a85c40fbdd0c0fea44937399dda7939a6">REG_SERCOM4_USART_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000014UL)</td></tr>
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<tr class="memdesc:a85c40fbdd0c0fea44937399dda7939a6"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Interrupt Enable Clear <br /></td></tr>
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<tr class="separator:a85c40fbdd0c0fea44937399dda7939a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8624b409deed002c02321b260551b2be"><td class="memItemLeft" align="right" valign="top"><a id="a8624b409deed002c02321b260551b2be"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a8624b409deed002c02321b260551b2be">REG_SERCOM4_USART_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000016UL)</td></tr>
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<tr class="memdesc:a8624b409deed002c02321b260551b2be"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Interrupt Enable Set <br /></td></tr>
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<tr class="separator:a8624b409deed002c02321b260551b2be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a04e64eb9ec90a62dbafbdce7e99afc40"><td class="memItemLeft" align="right" valign="top"><a id="a04e64eb9ec90a62dbafbdce7e99afc40"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a04e64eb9ec90a62dbafbdce7e99afc40">REG_SERCOM4_USART_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000018UL)</td></tr>
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<tr class="memdesc:a04e64eb9ec90a62dbafbdce7e99afc40"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Interrupt Flag Status and Clear <br /></td></tr>
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<tr class="separator:a04e64eb9ec90a62dbafbdce7e99afc40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac364fefb585dcfd9595a08d475be6517"><td class="memItemLeft" align="right" valign="top"><a id="ac364fefb585dcfd9595a08d475be6517"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#ac364fefb585dcfd9595a08d475be6517">REG_SERCOM4_USART_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4300001AUL)</td></tr>
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<tr class="memdesc:ac364fefb585dcfd9595a08d475be6517"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Status <br /></td></tr>
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<tr class="separator:ac364fefb585dcfd9595a08d475be6517"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7c8254dfd0d0af23d85625cc7b600f5f"><td class="memItemLeft" align="right" valign="top"><a id="a7c8254dfd0d0af23d85625cc7b600f5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a7c8254dfd0d0af23d85625cc7b600f5f">REG_SERCOM4_USART_SYNCBUSY</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4300001CUL)</td></tr>
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<tr class="memdesc:a7c8254dfd0d0af23d85625cc7b600f5f"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Synchronization Busy <br /></td></tr>
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<tr class="separator:a7c8254dfd0d0af23d85625cc7b600f5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3de12ed48ee61b142229ad402e88ecc7"><td class="memItemLeft" align="right" valign="top"><a id="a3de12ed48ee61b142229ad402e88ecc7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a3de12ed48ee61b142229ad402e88ecc7">REG_SERCOM4_USART_RXERRCNT</a>   (*(<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> *)0x43000020UL)</td></tr>
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<tr class="memdesc:a3de12ed48ee61b142229ad402e88ecc7"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Receive Error Count <br /></td></tr>
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<tr class="separator:a3de12ed48ee61b142229ad402e88ecc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6235ef1ed7e9e32ab3a0d7768373a25a"><td class="memItemLeft" align="right" valign="top"><a id="a6235ef1ed7e9e32ab3a0d7768373a25a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a6235ef1ed7e9e32ab3a0d7768373a25a">REG_SERCOM4_USART_LENGTH</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x43000022UL)</td></tr>
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<tr class="memdesc:a6235ef1ed7e9e32ab3a0d7768373a25a"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Length <br /></td></tr>
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<tr class="separator:a6235ef1ed7e9e32ab3a0d7768373a25a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac125cae6fdeb2e6b7505c651a588cf58"><td class="memItemLeft" align="right" valign="top"><a id="ac125cae6fdeb2e6b7505c651a588cf58"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#ac125cae6fdeb2e6b7505c651a588cf58">REG_SERCOM4_USART_DATA</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x43000028UL)</td></tr>
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<tr class="memdesc:ac125cae6fdeb2e6b7505c651a588cf58"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Data <br /></td></tr>
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<tr class="separator:ac125cae6fdeb2e6b7505c651a588cf58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a107780189d18aefe14a1aeb133948f82"><td class="memItemLeft" align="right" valign="top"><a id="a107780189d18aefe14a1aeb133948f82"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sercom4_8h.html#a107780189d18aefe14a1aeb133948f82">REG_SERCOM4_USART_DBGCTRL</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x43000030UL)</td></tr>
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<tr class="memdesc:a107780189d18aefe14a1aeb133948f82"><td class="mdescLeft"> </td><td class="mdescRight">(SERCOM4) USART Debug Control <br /></td></tr>
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<tr class="separator:a107780189d18aefe14a1aeb133948f82"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abea9cb7ff010a3f0d04f64ecb1706cfa"><td class="memItemLeft" align="right" valign="top"><a id="abea9cb7ff010a3f0d04f64ecb1706cfa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_CLK_REDUCTION</b>   1</td></tr>
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<tr class="separator:abea9cb7ff010a3f0d04f64ecb1706cfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acc39ddea2ef8f7e7a2c8724845c8b565"><td class="memItemLeft" align="right" valign="top"><a id="acc39ddea2ef8f7e7a2c8724845c8b565"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_DLY_COMPENSATION</b>   1</td></tr>
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<tr class="separator:acc39ddea2ef8f7e7a2c8724845c8b565"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3a6755b24ed57d57ceedf6a33c3b345c"><td class="memItemLeft" align="right" valign="top"><a id="a3a6755b24ed57d57ceedf6a33c3b345c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_DMA</b>   1</td></tr>
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<tr class="separator:a3a6755b24ed57d57ceedf6a33c3b345c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7de8cf9e95745263a230853b13188522"><td class="memItemLeft" align="right" valign="top"><a id="a7de8cf9e95745263a230853b13188522"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_DMAC_ID_RX</b>   12</td></tr>
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<tr class="separator:a7de8cf9e95745263a230853b13188522"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeedc76f0fc42937b376b147db4319b37"><td class="memItemLeft" align="right" valign="top"><a id="aeedc76f0fc42937b376b147db4319b37"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_DMAC_ID_TX</b>   13</td></tr>
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<tr class="separator:aeedc76f0fc42937b376b147db4319b37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a333a6f02ebb8cbecbf375981799be173"><td class="memItemLeft" align="right" valign="top"><a id="a333a6f02ebb8cbecbf375981799be173"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_FIFO_DEPTH_POWER</b>   1</td></tr>
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<tr class="separator:a333a6f02ebb8cbecbf375981799be173"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af27a2ab6455dbca9d200890065a3b67b"><td class="memItemLeft" align="right" valign="top"><a id="af27a2ab6455dbca9d200890065a3b67b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_GCLK_ID_CORE</b>   34</td></tr>
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<tr class="separator:af27a2ab6455dbca9d200890065a3b67b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aee549568058d41a67429e4297920514d"><td class="memItemLeft" align="right" valign="top"><a id="aee549568058d41a67429e4297920514d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_GCLK_ID_SLOW</b>   3</td></tr>
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<tr class="separator:aee549568058d41a67429e4297920514d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a63c00f65941efe610ead92da1340c07b"><td class="memItemLeft" align="right" valign="top"><a id="a63c00f65941efe610ead92da1340c07b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_INT_MSB</b>   6</td></tr>
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<tr class="separator:a63c00f65941efe610ead92da1340c07b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2aa872c213a1063b8878aeb0182719b9"><td class="memItemLeft" align="right" valign="top"><a id="a2aa872c213a1063b8878aeb0182719b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_I2CM</b>   1</td></tr>
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<tr class="separator:a2aa872c213a1063b8878aeb0182719b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af64193b9ad4159a14ea14b273d0d5d6f"><td class="memItemLeft" align="right" valign="top"><a id="af64193b9ad4159a14ea14b273d0d5d6f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_I2CS</b>   1</td></tr>
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<tr class="separator:af64193b9ad4159a14ea14b273d0d5d6f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a32994e3c539debc01d5d5b305d96b59e"><td class="memItemLeft" align="right" valign="top"><a id="a32994e3c539debc01d5d5b305d96b59e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_I2CS_AUTO_ACK</b>   1</td></tr>
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<tr class="separator:a32994e3c539debc01d5d5b305d96b59e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae1e523c692fc86a2a1a086258b297701"><td class="memItemLeft" align="right" valign="top"><a id="ae1e523c692fc86a2a1a086258b297701"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_I2CS_GROUP_CMD</b>   1</td></tr>
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<tr class="separator:ae1e523c692fc86a2a1a086258b297701"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4f09bd047a6cb3c8c07a893e83df4581"><td class="memItemLeft" align="right" valign="top"><a id="a4f09bd047a6cb3c8c07a893e83df4581"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_I2CS_SDASETUP_CNT_SIZE</b>   8</td></tr>
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<tr class="separator:a4f09bd047a6cb3c8c07a893e83df4581"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6e1f14e1da247d74d7621ea80cd90f3c"><td class="memItemLeft" align="right" valign="top"><a id="a6e1f14e1da247d74d7621ea80cd90f3c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_I2CS_SDASETUP_SIZE</b>   4</td></tr>
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<tr class="separator:a6e1f14e1da247d74d7621ea80cd90f3c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4703ad01a8186073f0c4ebe3e2f6941c"><td class="memItemLeft" align="right" valign="top"><a id="a4703ad01a8186073f0c4ebe3e2f6941c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_I2CS_SUDAT</b>   1</td></tr>
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<tr class="separator:a4703ad01a8186073f0c4ebe3e2f6941c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a3f4afbf779409aa4a771a6827360fd"><td class="memItemLeft" align="right" valign="top"><a id="a0a3f4afbf779409aa4a771a6827360fd"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_I2C_FASTMP</b>   1</td></tr>
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<tr class="separator:a0a3f4afbf779409aa4a771a6827360fd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d8799c3394009b83cf612e56f2cd2ef"><td class="memItemLeft" align="right" valign="top"><a id="a2d8799c3394009b83cf612e56f2cd2ef"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_I2C_HSMODE</b>   1</td></tr>
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<tr class="separator:a2d8799c3394009b83cf612e56f2cd2ef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adb11cba076f1abaaf8792c4e7a141e8f"><td class="memItemLeft" align="right" valign="top"><a id="adb11cba076f1abaaf8792c4e7a141e8f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_I2C_SCLSM_MODE</b>   1</td></tr>
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<tr class="separator:adb11cba076f1abaaf8792c4e7a141e8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a23c628cb3d3103e9a85cc5ef946ce098"><td class="memItemLeft" align="right" valign="top"><a id="a23c628cb3d3103e9a85cc5ef946ce098"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_I2C_SMB_TIMEOUTS</b>   1</td></tr>
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<tr class="separator:a23c628cb3d3103e9a85cc5ef946ce098"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac76f38fad8bbd949845fa666f025e600"><td class="memItemLeft" align="right" valign="top"><a id="ac76f38fad8bbd949845fa666f025e600"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_I2C_TENBIT_ADR</b>   1</td></tr>
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<tr class="separator:ac76f38fad8bbd949845fa666f025e600"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6f78feff60962ce0dc9a5570795dcbb7"><td class="memItemLeft" align="right" valign="top"><a id="a6f78feff60962ce0dc9a5570795dcbb7"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_PMSB</b>   3</td></tr>
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<tr class="separator:a6f78feff60962ce0dc9a5570795dcbb7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a380a12928c32a56e0942eab3131ce7c5"><td class="memItemLeft" align="right" valign="top"><a id="a380a12928c32a56e0942eab3131ce7c5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_RETENTION_SUPPORT</b>   0</td></tr>
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<tr class="separator:a380a12928c32a56e0942eab3131ce7c5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0a026eb189b5ea514c17dd9dc8249149"><td class="memItemLeft" align="right" valign="top"><a id="a0a026eb189b5ea514c17dd9dc8249149"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_SE_CNT</b>   1</td></tr>
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<tr class="separator:a0a026eb189b5ea514c17dd9dc8249149"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa0e249fad2584973688708a8b993ba96"><td class="memItemLeft" align="right" valign="top"><a id="aa0e249fad2584973688708a8b993ba96"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_SPI</b>   1</td></tr>
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<tr class="separator:aa0e249fad2584973688708a8b993ba96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac1f92099c340c892550f5f7b94568ada"><td class="memItemLeft" align="right" valign="top"><a id="ac1f92099c340c892550f5f7b94568ada"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_SPI_HW_SS_CTRL</b>   1</td></tr>
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<tr class="separator:ac1f92099c340c892550f5f7b94568ada"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aba27a006fbed0ea3bdfa4eff6cf12a68"><td class="memItemLeft" align="right" valign="top"><a id="aba27a006fbed0ea3bdfa4eff6cf12a68"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_SPI_ICSPACE_EXT</b>   1</td></tr>
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<tr class="separator:aba27a006fbed0ea3bdfa4eff6cf12a68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a06fbb5ac49d8660557ade87761112e95"><td class="memItemLeft" align="right" valign="top"><a id="a06fbb5ac49d8660557ade87761112e95"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_SPI_OZMO</b>   0</td></tr>
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<tr class="separator:a06fbb5ac49d8660557ade87761112e95"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab55cd6ac1c16c8731557a3f53a20188d"><td class="memItemLeft" align="right" valign="top"><a id="ab55cd6ac1c16c8731557a3f53a20188d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_SPI_WAKE_ON_SSL</b>   1</td></tr>
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<tr class="separator:ab55cd6ac1c16c8731557a3f53a20188d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a24ed5a970af1a9b4150aa8488944ecc9"><td class="memItemLeft" align="right" valign="top"><a id="a24ed5a970af1a9b4150aa8488944ecc9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_TTBIT_EXTENSION</b>   1</td></tr>
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<tr class="separator:a24ed5a970af1a9b4150aa8488944ecc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abc03ba9e7191b6a4ebad5c58a9a6462d"><td class="memItemLeft" align="right" valign="top"><a id="abc03ba9e7191b6a4ebad5c58a9a6462d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_USART</b>   1</td></tr>
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<tr class="separator:abc03ba9e7191b6a4ebad5c58a9a6462d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2dd15e288383831954c4bbffdc8d84a0"><td class="memItemLeft" align="right" valign="top"><a id="a2dd15e288383831954c4bbffdc8d84a0"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_USART_AUTOBAUD</b>   1</td></tr>
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<tr class="separator:a2dd15e288383831954c4bbffdc8d84a0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a753e542243c44e6866a03c936522553e"><td class="memItemLeft" align="right" valign="top"><a id="a753e542243c44e6866a03c936522553e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_USART_COLDET</b>   1</td></tr>
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<tr class="separator:a753e542243c44e6866a03c936522553e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a382375e98f35a08a5a4ed7ae579bb62a"><td class="memItemLeft" align="right" valign="top"><a id="a382375e98f35a08a5a4ed7ae579bb62a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_USART_FLOW_CTRL</b>   1</td></tr>
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<tr class="separator:a382375e98f35a08a5a4ed7ae579bb62a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4968a7161e70453bc6cf683e989fca60"><td class="memItemLeft" align="right" valign="top"><a id="a4968a7161e70453bc6cf683e989fca60"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_USART_FRAC_BAUD</b>   1</td></tr>
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<tr class="separator:a4968a7161e70453bc6cf683e989fca60"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adb82ac3872ff0465334788063b879148"><td class="memItemLeft" align="right" valign="top"><a id="adb82ac3872ff0465334788063b879148"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_USART_IRDA</b>   1</td></tr>
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<tr class="separator:adb82ac3872ff0465334788063b879148"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa8620dd01e71f7f1046e9ee2234e26f5"><td class="memItemLeft" align="right" valign="top"><a id="aa8620dd01e71f7f1046e9ee2234e26f5"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_USART_ISO7816</b>   1</td></tr>
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<tr class="separator:aa8620dd01e71f7f1046e9ee2234e26f5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa33c62779358948caad115eb02cce6f6"><td class="memItemLeft" align="right" valign="top"><a id="aa33c62779358948caad115eb02cce6f6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_USART_LIN_MASTER</b>   1</td></tr>
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<tr class="separator:aa33c62779358948caad115eb02cce6f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a787d1a914fa53e32fc32dca085b54f10"><td class="memItemLeft" align="right" valign="top"><a id="a787d1a914fa53e32fc32dca085b54f10"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_USART_RS485</b>   1</td></tr>
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<tr class="separator:a787d1a914fa53e32fc32dca085b54f10"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac07f5317e8e14b6d517c7d6cd119aa08"><td class="memItemLeft" align="right" valign="top"><a id="ac07f5317e8e14b6d517c7d6cd119aa08"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_USART_SAMPA_EXT</b>   1</td></tr>
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<tr class="separator:ac07f5317e8e14b6d517c7d6cd119aa08"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad2224e2316e5d58cac308da2fb8435d8"><td class="memItemLeft" align="right" valign="top"><a id="ad2224e2316e5d58cac308da2fb8435d8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SERCOM4_USART_SAMPR_EXT</b>   1</td></tr>
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<tr class="separator:ad2224e2316e5d58cac308da2fb8435d8"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for SERCOM4. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="sercom4_8h_source.html">sercom4.h</a>.</p>
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