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629 lines
42 KiB
C
629 lines
42 KiB
C
/**
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* \brief Header file for ATSAME70J19B
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-03-04T11:02:47Z */
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#ifndef _SAME70J19B_H_
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#define _SAME70J19B_H_
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// Header version uses Semantic Versioning 2.0.0 (https://semver.org/)
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#define HEADER_FORMAT_VERSION "2.0.0"
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#define HEADER_FORMAT_VERSION_MAJOR (2)
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#define HEADER_FORMAT_VERSION_MINOR (0)
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/** \addtogroup SAME70J19B_definitions SAME70J19B definitions
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This file defines all structures and symbols for SAME70J19B:
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- registers and bitfields
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- peripheral base address
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- peripheral ID
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- PIO definitions
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* @{
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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# include <stdint.h>
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#if !defined(SKIP_INTEGER_LITERALS)
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# if defined(_U_) || defined(_L_) || defined(_UL_)
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# error "Integer Literals macros already defined elsewhere"
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# endif
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/* Macros that deal with adding suffixes to integer literal constants for C/C++ */
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# define _U_(x) (x ## U) /**< C code: Unsigned integer literal constant value */
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# define _L_(x) (x ## L) /**< C code: Long integer literal constant value */
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# define _UL_(x) (x ## UL) /**< C code: Unsigned Long integer literal constant value */
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#else /* Assembler */
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# define _U_(x) x /**< Assembler: Unsigned integer literal constant value */
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# define _L_(x) x /**< Assembler: Long integer literal constant value */
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# define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* SKIP_INTEGER_LITERALS */
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/** @} end of Atmel Global Defines */
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/* ************************************************************************** */
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/* CMSIS DEFINITIONS FOR SAME70J19B */
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/* ************************************************************************** */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** Interrupt Number Definition */
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typedef enum IRQn
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{
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/****** CORTEX-M7 Processor Exceptions Numbers ******************************/
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Reset_IRQn = -15, /**< -15 Reset Vector, invoked on Power up and warm reset */
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NonMaskableInt_IRQn = -14, /**< -14 Non maskable Interrupt, cannot be stopped or preempted */
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HardFault_IRQn = -13, /**< -13 Hard Fault, all classes of Fault */
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MemoryManagement_IRQn = -12, /**< -12 Memory Management, MPU mismatch, including Access Violation and No Match */
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BusFault_IRQn = -11, /**< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
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UsageFault_IRQn = -10, /**< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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SVCall_IRQn = -5, /**< -5 System Service Call via SVC instruction */
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DebugMonitor_IRQn = -4, /**< -4 Debug Monitor */
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PendSV_IRQn = -2, /**< -2 Pendable request for system service */
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SysTick_IRQn = -1, /**< -1 System Tick Timer */
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/****** SAME70J19B specific Interrupt Numbers ***********************************/
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SUPC_IRQn = 0, /**< 0 Supply Controller (SUPC) */
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RSTC_IRQn = 1, /**< 1 Reset Controller (RSTC) */
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RTC_IRQn = 2, /**< 2 Real-time Clock (RTC) */
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RTT_IRQn = 3, /**< 3 Real-time Timer (RTT) */
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WDT_IRQn = 4, /**< 4 Watchdog Timer (WDT) */
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PMC_IRQn = 5, /**< 5 Power Management Controller (PMC) */
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EFC_IRQn = 6, /**< 6 Embedded Flash Controller (EFC) */
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UART0_IRQn = 7, /**< 7 Universal Asynchronous Receiver Transmitter (UART0) */
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UART1_IRQn = 8, /**< 8 Universal Asynchronous Receiver Transmitter (UART1) */
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PIOA_IRQn = 10, /**< 10 Parallel Input/Output Controller (PIOA) */
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PIOB_IRQn = 11, /**< 11 Parallel Input/Output Controller (PIOB) */
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USART0_IRQn = 13, /**< 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */
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USART1_IRQn = 14, /**< 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */
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PIOD_IRQn = 16, /**< 16 Parallel Input/Output Controller (PIOD) */
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TWIHS0_IRQn = 19, /**< 19 Two-wire Interface High Speed (TWIHS0) */
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TWIHS1_IRQn = 20, /**< 20 Two-wire Interface High Speed (TWIHS1) */
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SSC_IRQn = 22, /**< 22 Synchronous Serial Controller (SSC) */
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TC0_CH0_IRQn = 23, /**< 23 Timer/Counter 0 Channel 0 (TC0) */
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TC0_CH1_IRQn = 24, /**< 24 Timer/Counter 0 Channel 1 (TC0) */
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TC0_CH2_IRQn = 25, /**< 25 Timer/Counter 0 Channel 2 (TC0) */
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TC1_CH0_IRQn = 26, /**< 26 Timer/Counter 1 Channel 0 (TC1) */
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TC1_CH1_IRQn = 27, /**< 27 Timer/Counter 1 Channel 1 (TC1) */
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TC1_CH2_IRQn = 28, /**< 28 Timer/Counter 1 Channel 2 (TC1) */
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AFEC0_IRQn = 29, /**< 29 Analog Front-End Controller (AFEC0) */
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DACC_IRQn = 30, /**< 30 Digital-to-Analog Converter Controller (DACC) */
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PWM0_IRQn = 31, /**< 31 Pulse Width Modulation Controller (PWM0) */
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ICM_IRQn = 32, /**< 32 Integrity Check Monitor (ICM) */
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ACC_IRQn = 33, /**< 33 Analog Comparator Controller (ACC) */
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USBHS_IRQn = 34, /**< 34 USB High-Speed Interface (USBHS) */
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MCAN0_INT0_IRQn = 35, /**< 35 Controller Area Network (MCAN0) */
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MCAN0_INT1_IRQn = 36, /**< 36 Controller Area Network (MCAN0) */
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GMAC_IRQn = 39, /**< 39 Gigabit Ethernet MAC (GMAC) */
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AFEC1_IRQn = 40, /**< 40 Analog Front-End Controller (AFEC1) */
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QSPI_IRQn = 43, /**< 43 Quad Serial Peripheral Interface (QSPI) */
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UART2_IRQn = 44, /**< 44 Universal Asynchronous Receiver Transmitter (UART2) */
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TC2_CH0_IRQn = 47, /**< 47 Timer/Counter 2 Channel 0 (TC2) */
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TC2_CH1_IRQn = 48, /**< 48 Timer/Counter 2 Channel 1 (TC2) */
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TC2_CH2_IRQn = 49, /**< 49 Timer/Counter 2 Channel 2 (TC2) */
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TC3_CH0_IRQn = 50, /**< 50 Timer/Counter 3 Channel 0 (TC3) */
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TC3_CH1_IRQn = 51, /**< 51 Timer/Counter 3 Channel 1 (TC3) */
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TC3_CH2_IRQn = 52, /**< 52 Timer/Counter 3 Channel 2 (TC3) */
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AES_IRQn = 56, /**< 56 Advanced Encryption Standard (AES) */
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TRNG_IRQn = 57, /**< 57 True Random Number Generator (TRNG) */
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XDMAC_IRQn = 58, /**< 58 Extensible DMA Controller (XDMAC) */
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ISI_IRQn = 59, /**< 59 Image Sensor Interface (ISI) */
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PWM1_IRQn = 60, /**< 60 Pulse Width Modulation Controller (PWM1) */
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FPU_IRQn = 61, /**< 61 Floating Point Unit (FPU) */
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RSWDT_IRQn = 63, /**< 63 Reinforced Safety Watchdog Timer (RSWDT) */
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CCW_IRQn = 64, /**< 64 System Control Block (SCB) */
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CCF_IRQn = 65, /**< 65 System Control Block (SCB) */
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GMAC_Q1_IRQn = 66, /**< 66 Gigabit Ethernet MAC (GMAC) */
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GMAC_Q2_IRQn = 67, /**< 67 Gigabit Ethernet MAC (GMAC) */
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IXC_IRQn = 68, /**< 68 Floating Point Unit (FPU) */
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GMAC_Q3_IRQn = 71, /**< 71 Gigabit Ethernet MAC (GMAC) */
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GMAC_Q4_IRQn = 72, /**< 72 Gigabit Ethernet MAC (GMAC) */
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GMAC_Q5_IRQn = 73, /**< 73 Gigabit Ethernet MAC (GMAC) */
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PERIPH_MAX_IRQn = 73 /**< Max peripheral ID */
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} IRQn_Type;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct _DeviceVectors
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{
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/* Stack pointer */
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void* pvStack;
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/* CORTEX-M7 handlers */
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void* pfnReset_Handler; /* -15 Reset Vector, invoked on Power up and warm reset */
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void* pfnNonMaskableInt_Handler; /* -14 Non maskable Interrupt, cannot be stopped or preempted */
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void* pfnHardFault_Handler; /* -13 Hard Fault, all classes of Fault */
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void* pfnMemoryManagement_Handler; /* -12 Memory Management, MPU mismatch, including Access Violation and No Match */
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void* pfnBusFault_Handler; /* -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
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void* pfnUsageFault_Handler; /* -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
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void* pvReservedC9;
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void* pvReservedC8;
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void* pvReservedC7;
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void* pvReservedC6;
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void* pfnSVCall_Handler; /* -5 System Service Call via SVC instruction */
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void* pfnDebugMonitor_Handler; /* -4 Debug Monitor */
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void* pvReservedC3;
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void* pfnPendSV_Handler; /* -2 Pendable request for system service */
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void* pfnSysTick_Handler; /* -1 System Tick Timer */
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/* Peripheral handlers */
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void* pfnSUPC_Handler; /* 0 Supply Controller (SUPC) */
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void* pfnRSTC_Handler; /* 1 Reset Controller (RSTC) */
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void* pfnRTC_Handler; /* 2 Real-time Clock (RTC) */
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void* pfnRTT_Handler; /* 3 Real-time Timer (RTT) */
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void* pfnWDT_Handler; /* 4 Watchdog Timer (WDT) */
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void* pfnPMC_Handler; /* 5 Power Management Controller (PMC) */
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void* pfnEFC_Handler; /* 6 Embedded Flash Controller (EFC) */
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void* pfnUART0_Handler; /* 7 Universal Asynchronous Receiver Transmitter (UART0) */
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void* pfnUART1_Handler; /* 8 Universal Asynchronous Receiver Transmitter (UART1) */
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void* pvReserved9;
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void* pfnPIOA_Handler; /* 10 Parallel Input/Output Controller (PIOA) */
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void* pfnPIOB_Handler; /* 11 Parallel Input/Output Controller (PIOB) */
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void* pvReserved12;
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void* pfnUSART0_Handler; /* 13 Universal Synchronous Asynchronous Receiver Transmitter (USART0) */
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void* pfnUSART1_Handler; /* 14 Universal Synchronous Asynchronous Receiver Transmitter (USART1) */
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void* pvReserved15;
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void* pfnPIOD_Handler; /* 16 Parallel Input/Output Controller (PIOD) */
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void* pvReserved17;
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void* pvReserved18;
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void* pfnTWIHS0_Handler; /* 19 Two-wire Interface High Speed (TWIHS0) */
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void* pfnTWIHS1_Handler; /* 20 Two-wire Interface High Speed (TWIHS1) */
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void* pvReserved21;
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void* pfnSSC_Handler; /* 22 Synchronous Serial Controller (SSC) */
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void* pfnTC0_CH0_Handler; /* 23 Timer/Counter 0 Channel 0 (TC0) */
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void* pfnTC0_CH1_Handler; /* 24 Timer/Counter 0 Channel 1 (TC0) */
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void* pfnTC0_CH2_Handler; /* 25 Timer/Counter 0 Channel 2 (TC0) */
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void* pfnTC1_CH0_Handler; /* 26 Timer/Counter 1 Channel 0 (TC1) */
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void* pfnTC1_CH1_Handler; /* 27 Timer/Counter 1 Channel 1 (TC1) */
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void* pfnTC1_CH2_Handler; /* 28 Timer/Counter 1 Channel 2 (TC1) */
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void* pfnAFEC0_Handler; /* 29 Analog Front-End Controller (AFEC0) */
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void* pfnDACC_Handler; /* 30 Digital-to-Analog Converter Controller (DACC) */
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void* pfnPWM0_Handler; /* 31 Pulse Width Modulation Controller (PWM0) */
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void* pfnICM_Handler; /* 32 Integrity Check Monitor (ICM) */
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void* pfnACC_Handler; /* 33 Analog Comparator Controller (ACC) */
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void* pfnUSBHS_Handler; /* 34 USB High-Speed Interface (USBHS) */
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void* pfnMCAN0_INT0_Handler; /* 35 Controller Area Network (MCAN0) */
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void* pfnMCAN0_INT1_Handler; /* 36 Controller Area Network (MCAN0) */
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void* pvReserved37;
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void* pvReserved38;
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void* pfnGMAC_Handler; /* 39 Gigabit Ethernet MAC (GMAC) */
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void* pfnAFEC1_Handler; /* 40 Analog Front-End Controller (AFEC1) */
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void* pvReserved41;
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void* pvReserved42;
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void* pfnQSPI_Handler; /* 43 Quad Serial Peripheral Interface (QSPI) */
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void* pfnUART2_Handler; /* 44 Universal Asynchronous Receiver Transmitter (UART2) */
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void* pvReserved45;
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void* pvReserved46;
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void* pfnTC2_CH0_Handler; /* 47 Timer/Counter 2 Channel 0 (TC2) */
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void* pfnTC2_CH1_Handler; /* 48 Timer/Counter 2 Channel 1 (TC2) */
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void* pfnTC2_CH2_Handler; /* 49 Timer/Counter 2 Channel 2 (TC2) */
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void* pfnTC3_CH0_Handler; /* 50 Timer/Counter 3 Channel 0 (TC3) */
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void* pfnTC3_CH1_Handler; /* 51 Timer/Counter 3 Channel 1 (TC3) */
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void* pfnTC3_CH2_Handler; /* 52 Timer/Counter 3 Channel 2 (TC3) */
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void* pvReserved53;
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void* pvReserved54;
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void* pvReserved55;
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void* pfnAES_Handler; /* 56 Advanced Encryption Standard (AES) */
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void* pfnTRNG_Handler; /* 57 True Random Number Generator (TRNG) */
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void* pfnXDMAC_Handler; /* 58 Extensible DMA Controller (XDMAC) */
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void* pfnISI_Handler; /* 59 Image Sensor Interface (ISI) */
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void* pfnPWM1_Handler; /* 60 Pulse Width Modulation Controller (PWM1) */
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void* pfnFPU_Handler; /* 61 Floating Point Unit (FPU) */
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void* pvReserved62;
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void* pfnRSWDT_Handler; /* 63 Reinforced Safety Watchdog Timer (RSWDT) */
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void* pfnCCW_Handler; /* 64 System Control Block (SCB) */
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void* pfnCCF_Handler; /* 65 System Control Block (SCB) */
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void* pfnGMAC_Q1_Handler; /* 66 Gigabit Ethernet MAC (GMAC) */
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void* pfnGMAC_Q2_Handler; /* 67 Gigabit Ethernet MAC (GMAC) */
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void* pfnIXC_Handler; /* 68 Floating Point Unit (FPU) */
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void* pvReserved69;
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void* pvReserved70;
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void* pfnGMAC_Q3_Handler; /* 71 Gigabit Ethernet MAC (GMAC) */
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void* pfnGMAC_Q4_Handler; /* 72 Gigabit Ethernet MAC (GMAC) */
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void* pfnGMAC_Q5_Handler; /* 73 Gigabit Ethernet MAC (GMAC) */
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} DeviceVectors;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#if !defined DONT_USE_PREDEFINED_CORE_HANDLERS
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/* CORTEX-M7 exception handlers */
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void Reset_Handler ( void );
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void NonMaskableInt_Handler ( void );
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void HardFault_Handler ( void );
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void MemoryManagement_Handler ( void );
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void BusFault_Handler ( void );
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void UsageFault_Handler ( void );
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void SVCall_Handler ( void );
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void DebugMonitor_Handler ( void );
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void PendSV_Handler ( void );
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void SysTick_Handler ( void );
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#endif /* DONT_USE_PREDEFINED_CORE_HANDLERS */
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#if !defined DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
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/* Peripherals interrupt handlers */
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void SUPC_Handler ( void );
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void RSTC_Handler ( void );
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void RTC_Handler ( void );
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void RTT_Handler ( void );
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void WDT_Handler ( void );
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void PMC_Handler ( void );
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void EFC_Handler ( void );
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void UART0_Handler ( void );
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void UART1_Handler ( void );
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void PIOA_Handler ( void );
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void PIOB_Handler ( void );
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void USART0_Handler ( void );
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void USART1_Handler ( void );
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void PIOD_Handler ( void );
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void TWIHS0_Handler ( void );
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void TWIHS1_Handler ( void );
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void SSC_Handler ( void );
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void TC0_CH0_Handler ( void );
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void TC0_CH1_Handler ( void );
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void TC0_CH2_Handler ( void );
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void TC1_CH0_Handler ( void );
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void TC1_CH1_Handler ( void );
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void TC1_CH2_Handler ( void );
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void AFEC0_Handler ( void );
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void DACC_Handler ( void );
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void PWM0_Handler ( void );
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void ICM_Handler ( void );
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void ACC_Handler ( void );
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void USBHS_Handler ( void );
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void MCAN0_INT0_Handler ( void );
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void MCAN0_INT1_Handler ( void );
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void GMAC_Handler ( void );
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void AFEC1_Handler ( void );
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void QSPI_Handler ( void );
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void UART2_Handler ( void );
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void TC2_CH0_Handler ( void );
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void TC2_CH1_Handler ( void );
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void TC2_CH2_Handler ( void );
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void TC3_CH0_Handler ( void );
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void TC3_CH1_Handler ( void );
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void TC3_CH2_Handler ( void );
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void AES_Handler ( void );
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void TRNG_Handler ( void );
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void XDMAC_Handler ( void );
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void ISI_Handler ( void );
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void PWM1_Handler ( void );
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void FPU_Handler ( void );
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void RSWDT_Handler ( void );
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void CCW_Handler ( void );
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void CCF_Handler ( void );
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void GMAC_Q1_Handler ( void );
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void GMAC_Q2_Handler ( void );
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void IXC_Handler ( void );
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void GMAC_Q3_Handler ( void );
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void GMAC_Q4_Handler ( void );
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void GMAC_Q5_Handler ( void );
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#endif /* DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS */
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/** \brief Configuration of the CORTEX-M7 Processor and Core Peripherals */
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#define __CM7_REV 0x0101 /**< CM7 Core Revision */
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#define __NVIC_PRIO_BITS 3 /**< Number of Bits used for Priority Levels */
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#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
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#define __MPU_PRESENT 1 /**< MPU present or not */
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#define __VTOR_PRESENT 1 /**< Vector Table Offset Register present or not */
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#define __FPU_PRESENT 1 /**< FPU present or not */
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#define __FPU_DP 1 /**< Double Precision FPU */
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#define __ICACHE_PRESENT 1 /**< Instruction Cache present */
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#define __DCACHE_PRESENT 1 /**< Data Cache present */
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#define __ITCM_PRESENT 1 /**< Instruction TCM present */
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#define __DTCM_PRESENT 1 /**< Data TCM present */
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#define __DEBUG_LVL 1
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#define __TRACE_LVL 1
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#define __ARCH_ARM 1
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#define __ARCH_ARM_CORTEX_M 1
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/*
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* \brief CMSIS includes
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*/
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#include "core_cm7.h"
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#if defined USE_CMSIS_INIT
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#include "system_same70.h"
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#endif /* USE_CMSIS_INIT */
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/** \defgroup SAME70J19B_api Peripheral Software API
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* @{
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*/
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/* ************************************************************************** */
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/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME70J19B */
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/* ************************************************************************** */
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#include "component/acc.h"
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#include "component/aes.h"
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#include "component/afec.h"
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#include "component/chipid.h"
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#include "component/dacc.h"
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#include "component/efc.h"
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#include "component/gmac.h"
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#include "component/gpbr.h"
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#include "component/icm.h"
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#include "component/isi.h"
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#include "component/matrix.h"
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#include "component/mcan.h"
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#include "component/pio.h"
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#include "component/pmc.h"
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#include "component/pwm.h"
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#include "component/qspi.h"
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#include "component/rstc.h"
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#include "component/rswdt.h"
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#include "component/rtc.h"
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#include "component/rtt.h"
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#include "component/ssc.h"
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#include "component/supc.h"
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#include "component/tc.h"
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#include "component/trng.h"
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#include "component/twihs.h"
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#include "component/uart.h"
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#include "component/usart.h"
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#include "component/usbhs.h"
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#include "component/utmi.h"
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#include "component/wdt.h"
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#include "component/xdmac.h"
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/** @} end of Peripheral Software API */
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/** \addtogroup SAME70J19B_id Peripheral Ids Definitions
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* @{
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*/
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/* ************************************************************************** */
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/* PERIPHERAL ID DEFINITIONS FOR SAME70J19B */
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/* ************************************************************************** */
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#define ID_SUPC ( 0) /**< \brief Supply Controller (SUPC) */
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#define ID_RSTC ( 1) /**< \brief Reset Controller (RSTC) */
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#define ID_RTC ( 2) /**< \brief Real-time Clock (RTC) */
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#define ID_RTT ( 3) /**< \brief Real-time Timer (RTT) */
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#define ID_WDT ( 4) /**< \brief Watchdog Timer (WDT) */
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#define ID_PMC ( 5) /**< \brief Power Management Controller (PMC) */
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#define ID_EFC ( 6) /**< \brief Embedded Flash Controller (EFC) */
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#define ID_UART0 ( 7) /**< \brief Universal Asynchronous Receiver Transmitter (UART0) */
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#define ID_UART1 ( 8) /**< \brief Universal Asynchronous Receiver Transmitter (UART1) */
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#define ID_PIOA ( 10) /**< \brief Parallel Input/Output Controller (PIOA) */
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#define ID_PIOB ( 11) /**< \brief Parallel Input/Output Controller (PIOB) */
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#define ID_USART0 ( 13) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART0) */
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#define ID_USART1 ( 14) /**< \brief Universal Synchronous Asynchronous Receiver Transmitter (USART1) */
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#define ID_PIOD ( 16) /**< \brief Parallel Input/Output Controller (PIOD) */
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#define ID_TWIHS0 ( 19) /**< \brief Two-wire Interface High Speed (TWIHS0) */
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#define ID_TWIHS1 ( 20) /**< \brief Two-wire Interface High Speed (TWIHS1) */
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#define ID_SSC ( 22) /**< \brief Synchronous Serial Controller (SSC) */
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#define ID_TC0_CHANNEL0 ( 23) /**< \brief Timer Counter (TC0_CHANNEL0) */
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#define ID_TC0_CHANNEL1 ( 24) /**< \brief Timer Counter (TC0_CHANNEL1) */
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#define ID_TC0_CHANNEL2 ( 25) /**< \brief Timer Counter (TC0_CHANNEL2) */
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#define ID_TC1_CHANNEL0 ( 26) /**< \brief Timer Counter (TC1_CHANNEL0) */
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#define ID_TC1_CHANNEL1 ( 27) /**< \brief Timer Counter (TC1_CHANNEL1) */
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#define ID_TC1_CHANNEL2 ( 28) /**< \brief Timer Counter (TC1_CHANNEL2) */
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#define ID_AFEC0 ( 29) /**< \brief Analog Front-End Controller (AFEC0) */
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#define ID_DACC ( 30) /**< \brief Digital-to-Analog Converter Controller (DACC) */
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#define ID_PWM0 ( 31) /**< \brief Pulse Width Modulation Controller (PWM0) */
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#define ID_ICM ( 32) /**< \brief Integrity Check Monitor (ICM) */
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#define ID_ACC ( 33) /**< \brief Analog Comparator Controller (ACC) */
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#define ID_USBHS ( 34) /**< \brief USB High-Speed Interface (USBHS) */
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#define ID_MCAN0 ( 35) /**< \brief Controller Area Network (MCAN0) */
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#define ID_GMAC ( 39) /**< \brief Gigabit Ethernet MAC (GMAC) */
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#define ID_AFEC1 ( 40) /**< \brief Analog Front-End Controller (AFEC1) */
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#define ID_QSPI ( 43) /**< \brief Quad Serial Peripheral Interface (QSPI) */
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#define ID_UART2 ( 44) /**< \brief Universal Asynchronous Receiver Transmitter (UART2) */
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#define ID_TC2_CHANNEL0 ( 47) /**< \brief Timer Counter (TC2_CHANNEL0) */
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#define ID_TC2_CHANNEL1 ( 48) /**< \brief Timer Counter (TC2_CHANNEL1) */
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#define ID_TC2_CHANNEL2 ( 49) /**< \brief Timer Counter (TC2_CHANNEL2) */
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#define ID_TC3_CHANNEL0 ( 50) /**< \brief Timer Counter (TC3_CHANNEL0) */
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#define ID_TC3_CHANNEL1 ( 51) /**< \brief Timer Counter (TC3_CHANNEL1) */
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#define ID_TC3_CHANNEL2 ( 52) /**< \brief Timer Counter (TC3_CHANNEL2) */
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#define ID_AES ( 56) /**< \brief Advanced Encryption Standard (AES) */
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#define ID_TRNG ( 57) /**< \brief True Random Number Generator (TRNG) */
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#define ID_XDMAC ( 58) /**< \brief Extensible DMA Controller (XDMAC) */
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#define ID_ISI ( 59) /**< \brief Image Sensor Interface (ISI) */
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#define ID_PWM1 ( 60) /**< \brief Pulse Width Modulation Controller (PWM1) */
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#define ID_RSWDT ( 63) /**< \brief Reinforced Safety Watchdog Timer (RSWDT) */
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#define ID_PERIPH_MAX ( 63) /**< \brief Number of peripheral IDs */
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/** @} end of Peripheral Ids Definitions */
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/** \addtogroup SAME70J19B_base Peripheral Base Address Definitions
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* @{
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*/
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/* ************************************************************************** */
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/* REGISTER STRUCTURE ADDRESS DEFINITIONS FOR SAME70J19B */
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/* ************************************************************************** */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define ACC_REGS ((acc_registers_t*)0x40044000) /**< \brief ACC Registers Address */
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#define AES_REGS ((aes_registers_t*)0x4006c000) /**< \brief AES Registers Address */
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#define AFEC0_REGS ((afec_registers_t*)0x4003c000) /**< \brief AFEC0 Registers Address */
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#define AFEC1_REGS ((afec_registers_t*)0x40064000) /**< \brief AFEC1 Registers Address */
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#define CHIPID_REGS ((chipid_registers_t*)0x400e0940) /**< \brief CHIPID Registers Address */
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#define DACC_REGS ((dacc_registers_t*)0x40040000) /**< \brief DACC Registers Address */
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#define EFC_REGS ((efc_registers_t*)0x400e0c00) /**< \brief EFC Registers Address */
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#define GMAC_REGS ((gmac_registers_t*)0x40050000) /**< \brief GMAC Registers Address */
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#define GPBR_REGS ((gpbr_registers_t*)0x400e1890) /**< \brief GPBR Registers Address */
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#define ICM_REGS ((icm_registers_t*)0x40048000) /**< \brief ICM Registers Address */
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#define ISI_REGS ((isi_registers_t*)0x4004c000) /**< \brief ISI Registers Address */
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#define MATRIX_REGS ((matrix_registers_t*)0x40088000) /**< \brief MATRIX Registers Address */
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#define MCAN0_REGS ((mcan_registers_t*)0x40030000) /**< \brief MCAN0 Registers Address */
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#define PIOA_REGS ((pio_registers_t*)0x400e0e00) /**< \brief PIOA Registers Address */
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#define PIOB_REGS ((pio_registers_t*)0x400e1000) /**< \brief PIOB Registers Address */
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#define PIOD_REGS ((pio_registers_t*)0x400e1400) /**< \brief PIOD Registers Address */
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#define PMC_REGS ((pmc_registers_t*)0x400e0600) /**< \brief PMC Registers Address */
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#define PWM0_REGS ((pwm_registers_t*)0x40020000) /**< \brief PWM0 Registers Address */
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#define PWM1_REGS ((pwm_registers_t*)0x4005c000) /**< \brief PWM1 Registers Address */
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#define QSPI_REGS ((qspi_registers_t*)0x4007c000) /**< \brief QSPI Registers Address */
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#define RSTC_REGS ((rstc_registers_t*)0x400e1800) /**< \brief RSTC Registers Address */
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#define RSWDT_REGS ((rswdt_registers_t*)0x400e1900) /**< \brief RSWDT Registers Address */
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#define RTC_REGS ((rtc_registers_t*)0x400e1860) /**< \brief RTC Registers Address */
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#define RTT_REGS ((rtt_registers_t*)0x400e1830) /**< \brief RTT Registers Address */
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#define SSC_REGS ((ssc_registers_t*)0x40004000) /**< \brief SSC Registers Address */
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#define SUPC_REGS ((supc_registers_t*)0x400e1810) /**< \brief SUPC Registers Address */
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#define TC0_REGS ((tc_registers_t*)0x4000c000) /**< \brief TC0 Registers Address */
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#define TC1_REGS ((tc_registers_t*)0x40010000) /**< \brief TC1 Registers Address */
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#define TC2_REGS ((tc_registers_t*)0x40014000) /**< \brief TC2 Registers Address */
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#define TC3_REGS ((tc_registers_t*)0x40054000) /**< \brief TC3 Registers Address */
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#define TRNG_REGS ((trng_registers_t*)0x40070000) /**< \brief TRNG Registers Address */
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#define TWIHS0_REGS ((twihs_registers_t*)0x40018000) /**< \brief TWIHS0 Registers Address */
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#define TWIHS1_REGS ((twihs_registers_t*)0x4001c000) /**< \brief TWIHS1 Registers Address */
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#define UART0_REGS ((uart_registers_t*)0x400e0800) /**< \brief UART0 Registers Address */
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#define UART1_REGS ((uart_registers_t*)0x400e0a00) /**< \brief UART1 Registers Address */
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#define UART2_REGS ((uart_registers_t*)0x400e1a00) /**< \brief UART2 Registers Address */
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#define USART0_REGS ((usart_registers_t*)0x40024000) /**< \brief USART0 Registers Address */
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#define USART1_REGS ((usart_registers_t*)0x40028000) /**< \brief USART1 Registers Address */
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#define USBHS_REGS ((usbhs_registers_t*)0x40038000) /**< \brief USBHS Registers Address */
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#define UTMI_REGS ((utmi_registers_t*)0x400e0400) /**< \brief UTMI Registers Address */
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#define WDT_REGS ((wdt_registers_t*)0x400e1850) /**< \brief WDT Registers Address */
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#define XDMAC_REGS ((xdmac_registers_t*)0x40078000) /**< \brief XDMAC Registers Address */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/** @} end of Peripheral Base Address Definitions */
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/** \addtogroup SAME70J19B_base Peripheral Base Address Definitions
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* @{
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*/
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/* ************************************************************************** */
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/* BASE ADDRESS DEFINITIONS FOR SAME70J19B */
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/* ************************************************************************** */
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#define ACC_BASE_ADDRESS _UL_(0x40044000) /**< \brief ACC Base Address */
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#define AES_BASE_ADDRESS _UL_(0x4006c000) /**< \brief AES Base Address */
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#define AFEC0_BASE_ADDRESS _UL_(0x4003c000) /**< \brief AFEC0 Base Address */
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#define AFEC1_BASE_ADDRESS _UL_(0x40064000) /**< \brief AFEC1 Base Address */
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#define CHIPID_BASE_ADDRESS _UL_(0x400e0940) /**< \brief CHIPID Base Address */
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#define DACC_BASE_ADDRESS _UL_(0x40040000) /**< \brief DACC Base Address */
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#define EFC_BASE_ADDRESS _UL_(0x400e0c00) /**< \brief EFC Base Address */
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#define GMAC_BASE_ADDRESS _UL_(0x40050000) /**< \brief GMAC Base Address */
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#define GPBR_BASE_ADDRESS _UL_(0x400e1890) /**< \brief GPBR Base Address */
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#define ICM_BASE_ADDRESS _UL_(0x40048000) /**< \brief ICM Base Address */
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#define ISI_BASE_ADDRESS _UL_(0x4004c000) /**< \brief ISI Base Address */
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#define MATRIX_BASE_ADDRESS _UL_(0x40088000) /**< \brief MATRIX Base Address */
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#define MCAN0_BASE_ADDRESS _UL_(0x40030000) /**< \brief MCAN0 Base Address */
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#define PIOA_BASE_ADDRESS _UL_(0x400e0e00) /**< \brief PIOA Base Address */
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#define PIOB_BASE_ADDRESS _UL_(0x400e1000) /**< \brief PIOB Base Address */
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#define PIOD_BASE_ADDRESS _UL_(0x400e1400) /**< \brief PIOD Base Address */
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#define PMC_BASE_ADDRESS _UL_(0x400e0600) /**< \brief PMC Base Address */
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#define PWM0_BASE_ADDRESS _UL_(0x40020000) /**< \brief PWM0 Base Address */
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#define PWM1_BASE_ADDRESS _UL_(0x4005c000) /**< \brief PWM1 Base Address */
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#define QSPI_BASE_ADDRESS _UL_(0x4007c000) /**< \brief QSPI Base Address */
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#define RSTC_BASE_ADDRESS _UL_(0x400e1800) /**< \brief RSTC Base Address */
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#define RSWDT_BASE_ADDRESS _UL_(0x400e1900) /**< \brief RSWDT Base Address */
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#define RTC_BASE_ADDRESS _UL_(0x400e1860) /**< \brief RTC Base Address */
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#define RTT_BASE_ADDRESS _UL_(0x400e1830) /**< \brief RTT Base Address */
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#define SSC_BASE_ADDRESS _UL_(0x40004000) /**< \brief SSC Base Address */
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#define SUPC_BASE_ADDRESS _UL_(0x400e1810) /**< \brief SUPC Base Address */
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#define TC0_BASE_ADDRESS _UL_(0x4000c000) /**< \brief TC0 Base Address */
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#define TC1_BASE_ADDRESS _UL_(0x40010000) /**< \brief TC1 Base Address */
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#define TC2_BASE_ADDRESS _UL_(0x40014000) /**< \brief TC2 Base Address */
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|
#define TC3_BASE_ADDRESS _UL_(0x40054000) /**< \brief TC3 Base Address */
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#define TRNG_BASE_ADDRESS _UL_(0x40070000) /**< \brief TRNG Base Address */
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#define TWIHS0_BASE_ADDRESS _UL_(0x40018000) /**< \brief TWIHS0 Base Address */
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|
#define TWIHS1_BASE_ADDRESS _UL_(0x4001c000) /**< \brief TWIHS1 Base Address */
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|
#define UART0_BASE_ADDRESS _UL_(0x400e0800) /**< \brief UART0 Base Address */
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|
#define UART1_BASE_ADDRESS _UL_(0x400e0a00) /**< \brief UART1 Base Address */
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|
#define UART2_BASE_ADDRESS _UL_(0x400e1a00) /**< \brief UART2 Base Address */
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|
#define USART0_BASE_ADDRESS _UL_(0x40024000) /**< \brief USART0 Base Address */
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#define USART1_BASE_ADDRESS _UL_(0x40028000) /**< \brief USART1 Base Address */
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#define USBHS_BASE_ADDRESS _UL_(0x40038000) /**< \brief USBHS Base Address */
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|
#define UTMI_BASE_ADDRESS _UL_(0x400e0400) /**< \brief UTMI Base Address */
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|
#define WDT_BASE_ADDRESS _UL_(0x400e1850) /**< \brief WDT Base Address */
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|
#define XDMAC_BASE_ADDRESS _UL_(0x40078000) /**< \brief XDMAC Base Address */
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|
/** @} end of Peripheral Base Address Definitions */
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|
|
|
/** \addtogroup SAME70J19B_pio Peripheral Pio Definitions
|
|
* @{
|
|
*/
|
|
|
|
/* ************************************************************************** */
|
|
/* PIO DEFINITIONS FOR SAME70J19B */
|
|
/* ************************************************************************** */
|
|
#include "pio/same70j19b.h"
|
|
/** @} end of Peripheral Pio Definitions */
|
|
|
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/* ************************************************************************** */
|
|
/* MEMORY MAPPING DEFINITIONS FOR SAME70J19B */
|
|
/* ************************************************************************** */
|
|
|
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#define PERIPHERALS_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: io */
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#define SYSTEM_SIZE _UL_(0x10000000) /* 262144kB Memory segment type: io */
|
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#define QSPIMEM_SIZE _UL_(0x20000000) /* 524288kB Memory segment type: other */
|
|
#define AXIMX_SIZE _UL_(0x00100000) /* 1024kB Memory segment type: other */
|
|
#define ITCM_SIZE _UL_(0x00200000) /* 2048kB Memory segment type: other */
|
|
#define IFLASH_SIZE _UL_(0x00080000) /* 512kB Memory segment type: flash */
|
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#define IFLASH_PAGE_SIZE _UL_( 512)
|
|
#define IFLASH_NB_OF_PAGES _UL_( 1024)
|
|
|
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#define IROM_SIZE _UL_(0x00004000) /* 16kB Memory segment type: rom */
|
|
#define DTCM_SIZE _UL_(0x00020000) /* 128kB Memory segment type: other */
|
|
#define IRAM_SIZE _UL_(0x00040000) /* 256kB Memory segment type: ram */
|
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|
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#define PERIPHERALS_ADDR _UL_(0x40000000) /**< PERIPHERALS base address (type: io)*/
|
|
#define SYSTEM_ADDR _UL_(0xe0000000) /**< SYSTEM base address (type: io)*/
|
|
#define QSPIMEM_ADDR _UL_(0x80000000) /**< QSPIMEM base address (type: other)*/
|
|
#define AXIMX_ADDR _UL_(0xa0000000) /**< AXIMX base address (type: other)*/
|
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#define ITCM_ADDR _UL_(0x00000000) /**< ITCM base address (type: other)*/
|
|
#define IFLASH_ADDR _UL_(0x00400000) /**< IFLASH base address (type: flash)*/
|
|
#define IROM_ADDR _UL_(0x00800000) /**< IROM base address (type: rom)*/
|
|
#define DTCM_ADDR _UL_(0x20000000) /**< DTCM base address (type: other)*/
|
|
#define IRAM_ADDR _UL_(0x20400000) /**< IRAM base address (type: ram)*/
|
|
|
|
/* ************************************************************************** */
|
|
/** DEVICE SIGNATURES FOR SAME70J19B */
|
|
/* ************************************************************************** */
|
|
#define CHIP_JTAGID _UL_(0X05B3D03F)
|
|
#define CHIP_CIDR _UL_(0XA10D0A01)
|
|
#define CHIP_EXID _UL_(0X00000000)
|
|
|
|
/* ************************************************************************** */
|
|
/** ELECTRICAL DEFINITIONS FOR SAME70J19B */
|
|
/* ************************************************************************** */
|
|
#define CHIP_FREQ_SLCK_RC_MIN _UL_(20000)
|
|
#define CHIP_FREQ_SLCK_RC _UL_(32000) /**< \brief Typical Slow Clock Internal RC frequency */
|
|
#define CHIP_FREQ_SLCK_RC_MAX _UL_(44000)
|
|
#define CHIP_FREQ_MAINCK_RC_4MHZ _UL_(4000000)
|
|
#define CHIP_FREQ_MAINCK_RC_8MHZ _UL_(8000000)
|
|
#define CHIP_FREQ_MAINCK_RC_12MHZ _UL_(12000000)
|
|
#define CHIP_FREQ_CPU_MAX _UL_(300000000)
|
|
#define CHIP_FREQ_XTAL_32K _UL_(32768)
|
|
#define CHIP_FREQ_XTAL_12M _UL_(12000000)
|
|
#define CHIP_FREQ_FWS_0 _UL_(23000000) /**< \brief Maximum operating frequency when FWS is 0 */
|
|
#define CHIP_FREQ_FWS_1 _UL_(46000000) /**< \brief Maximum operating frequency when FWS is 1 */
|
|
#define CHIP_FREQ_FWS_2 _UL_(69000000) /**< \brief Maximum operating frequency when FWS is 2 */
|
|
#define CHIP_FREQ_FWS_3 _UL_(92000000) /**< \brief Maximum operating frequency when FWS is 3 */
|
|
#define CHIP_FREQ_FWS_4 _UL_(115000000) /**< \brief Maximum operating frequency when FWS is 4 */
|
|
#define CHIP_FREQ_FWS_5 _UL_(138000000) /**< \brief Maximum operating frequency when FWS is 5 */
|
|
#define CHIP_FREQ_FWS_6 _UL_(150000000) /**< \brief Maximum operating frequency when FWS is 6 */
|
|
#define CHIP_FREQ_FWS_NUMBER _UL_(7) /**< \brief Number of FWS ranges */
|
|
|
|
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
/** @} end of SAME70J19B definitions */
|
|
|
|
|
|
#endif /* _SAME70J19B_H_ */
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|
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