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107 lines
9.5 KiB
C
107 lines
9.5 KiB
C
/**
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* \brief Component description for RSTC
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-03-04T11:03:42Z */
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#ifndef _SAME70_RSTC_COMPONENT_H_
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#define _SAME70_RSTC_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR RSTC */
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/* ************************************************************************** */
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/* -------- RSTC_CR : (RSTC Offset: 0x00) ( /W 32) Control Register -------- */
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#define RSTC_CR_PROCRST_Pos _U_(0) /**< (RSTC_CR) Processor Reset Position */
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#define RSTC_CR_PROCRST_Msk (_U_(0x1) << RSTC_CR_PROCRST_Pos) /**< (RSTC_CR) Processor Reset Mask */
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#define RSTC_CR_PROCRST(value) (RSTC_CR_PROCRST_Msk & ((value) << RSTC_CR_PROCRST_Pos))
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#define RSTC_CR_EXTRST_Pos _U_(3) /**< (RSTC_CR) External Reset Position */
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#define RSTC_CR_EXTRST_Msk (_U_(0x1) << RSTC_CR_EXTRST_Pos) /**< (RSTC_CR) External Reset Mask */
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#define RSTC_CR_EXTRST(value) (RSTC_CR_EXTRST_Msk & ((value) << RSTC_CR_EXTRST_Pos))
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#define RSTC_CR_KEY_Pos _U_(24) /**< (RSTC_CR) System Reset Key Position */
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#define RSTC_CR_KEY_Msk (_U_(0xFF) << RSTC_CR_KEY_Pos) /**< (RSTC_CR) System Reset Key Mask */
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#define RSTC_CR_KEY(value) (RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))
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#define RSTC_CR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. */
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#define RSTC_CR_KEY_PASSWD (RSTC_CR_KEY_PASSWD_Val << RSTC_CR_KEY_Pos) /**< (RSTC_CR) Writing any other value in this field aborts the write operation. Position */
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#define RSTC_CR_Msk _U_(0xFF000009) /**< (RSTC_CR) Register Mask */
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/* -------- RSTC_SR : (RSTC Offset: 0x04) ( R/ 32) Status Register -------- */
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#define RSTC_SR_URSTS_Pos _U_(0) /**< (RSTC_SR) User Reset Status Position */
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#define RSTC_SR_URSTS_Msk (_U_(0x1) << RSTC_SR_URSTS_Pos) /**< (RSTC_SR) User Reset Status Mask */
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#define RSTC_SR_URSTS(value) (RSTC_SR_URSTS_Msk & ((value) << RSTC_SR_URSTS_Pos))
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#define RSTC_SR_RSTTYP_Pos _U_(8) /**< (RSTC_SR) Reset Type Position */
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#define RSTC_SR_RSTTYP_Msk (_U_(0x7) << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Reset Type Mask */
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#define RSTC_SR_RSTTYP(value) (RSTC_SR_RSTTYP_Msk & ((value) << RSTC_SR_RSTTYP_Pos))
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#define RSTC_SR_RSTTYP_GENERAL_RST_Val _U_(0x0) /**< (RSTC_SR) First power-up reset */
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#define RSTC_SR_RSTTYP_BACKUP_RST_Val _U_(0x1) /**< (RSTC_SR) Return from Backup Mode */
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#define RSTC_SR_RSTTYP_WDT_RST_Val _U_(0x2) /**< (RSTC_SR) Watchdog fault occurred */
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#define RSTC_SR_RSTTYP_SOFT_RST_Val _U_(0x3) /**< (RSTC_SR) Processor reset required by the software */
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#define RSTC_SR_RSTTYP_USER_RST_Val _U_(0x4) /**< (RSTC_SR) NRST pin detected low */
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#define RSTC_SR_RSTTYP_GENERAL_RST (RSTC_SR_RSTTYP_GENERAL_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) First power-up reset Position */
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#define RSTC_SR_RSTTYP_BACKUP_RST (RSTC_SR_RSTTYP_BACKUP_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Return from Backup Mode Position */
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#define RSTC_SR_RSTTYP_WDT_RST (RSTC_SR_RSTTYP_WDT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Watchdog fault occurred Position */
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#define RSTC_SR_RSTTYP_SOFT_RST (RSTC_SR_RSTTYP_SOFT_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) Processor reset required by the software Position */
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#define RSTC_SR_RSTTYP_USER_RST (RSTC_SR_RSTTYP_USER_RST_Val << RSTC_SR_RSTTYP_Pos) /**< (RSTC_SR) NRST pin detected low Position */
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#define RSTC_SR_NRSTL_Pos _U_(16) /**< (RSTC_SR) NRST Pin Level Position */
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#define RSTC_SR_NRSTL_Msk (_U_(0x1) << RSTC_SR_NRSTL_Pos) /**< (RSTC_SR) NRST Pin Level Mask */
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#define RSTC_SR_NRSTL(value) (RSTC_SR_NRSTL_Msk & ((value) << RSTC_SR_NRSTL_Pos))
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#define RSTC_SR_SRCMP_Pos _U_(17) /**< (RSTC_SR) Software Reset Command in Progress Position */
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#define RSTC_SR_SRCMP_Msk (_U_(0x1) << RSTC_SR_SRCMP_Pos) /**< (RSTC_SR) Software Reset Command in Progress Mask */
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#define RSTC_SR_SRCMP(value) (RSTC_SR_SRCMP_Msk & ((value) << RSTC_SR_SRCMP_Pos))
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#define RSTC_SR_Msk _U_(0x00030701) /**< (RSTC_SR) Register Mask */
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/* -------- RSTC_MR : (RSTC Offset: 0x08) (R/W 32) Mode Register -------- */
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#define RSTC_MR_URSTEN_Pos _U_(0) /**< (RSTC_MR) User Reset Enable Position */
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#define RSTC_MR_URSTEN_Msk (_U_(0x1) << RSTC_MR_URSTEN_Pos) /**< (RSTC_MR) User Reset Enable Mask */
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#define RSTC_MR_URSTEN(value) (RSTC_MR_URSTEN_Msk & ((value) << RSTC_MR_URSTEN_Pos))
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#define RSTC_MR_URSTIEN_Pos _U_(4) /**< (RSTC_MR) User Reset Interrupt Enable Position */
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#define RSTC_MR_URSTIEN_Msk (_U_(0x1) << RSTC_MR_URSTIEN_Pos) /**< (RSTC_MR) User Reset Interrupt Enable Mask */
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#define RSTC_MR_URSTIEN(value) (RSTC_MR_URSTIEN_Msk & ((value) << RSTC_MR_URSTIEN_Pos))
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#define RSTC_MR_ERSTL_Pos _U_(8) /**< (RSTC_MR) External Reset Length Position */
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#define RSTC_MR_ERSTL_Msk (_U_(0xF) << RSTC_MR_ERSTL_Pos) /**< (RSTC_MR) External Reset Length Mask */
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#define RSTC_MR_ERSTL(value) (RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))
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#define RSTC_MR_KEY_Pos _U_(24) /**< (RSTC_MR) Write Access Password Position */
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#define RSTC_MR_KEY_Msk (_U_(0xFF) << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Write Access Password Mask */
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#define RSTC_MR_KEY(value) (RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))
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#define RSTC_MR_KEY_PASSWD_Val _U_(0xA5) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. */
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#define RSTC_MR_KEY_PASSWD (RSTC_MR_KEY_PASSWD_Val << RSTC_MR_KEY_Pos) /**< (RSTC_MR) Writing any other value in this field aborts the write operation.Always reads as 0. Position */
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#define RSTC_MR_Msk _U_(0xFF000F11) /**< (RSTC_MR) Register Mask */
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/** \brief RSTC register offsets definitions */
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#define RSTC_CR_REG_OFST (0x00) /**< (RSTC_CR) Control Register Offset */
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#define RSTC_SR_REG_OFST (0x04) /**< (RSTC_SR) Status Register Offset */
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#define RSTC_MR_REG_OFST (0x08) /**< (RSTC_MR) Mode Register Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief RSTC register API structure */
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typedef struct
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{
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__O uint32_t RSTC_CR; /**< Offset: 0x00 ( /W 32) Control Register */
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__I uint32_t RSTC_SR; /**< Offset: 0x04 (R/ 32) Status Register */
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__IO uint32_t RSTC_MR; /**< Offset: 0x08 (R/W 32) Mode Register */
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} rstc_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME70_RSTC_COMPONENT_H_ */
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