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317 lines
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317 lines
41 KiB
HTML
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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/sdhc0.h File Reference</title>
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<div id="projectname">SAME54P20A Test Project
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="summary">
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<a href="#define-members">Macros</a> </div>
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<div class="headertitle">
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<div class="title">sdhc0.h File Reference</div> </div>
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<div class="contents">
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<p>Instance description for SDHC0.
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<a href="#details">More...</a></p>
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<p><a href="sdhc0_8h_source.html">Go to the source code of this file.</a></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a3695cb2179c6ba0b73670c7c2a0e3ba0"><td class="memItemLeft" align="right" valign="top"><a id="a3695cb2179c6ba0b73670c7c2a0e3ba0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a3695cb2179c6ba0b73670c7c2a0e3ba0">REG_SDHC0_SSAR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x45000000UL)</td></tr>
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<tr class="memdesc:a3695cb2179c6ba0b73670c7c2a0e3ba0"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) SDMA System Address / Argument 2 <br /></td></tr>
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<tr class="separator:a3695cb2179c6ba0b73670c7c2a0e3ba0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6e4a2e3551a2c80965626b8d50a99f25"><td class="memItemLeft" align="right" valign="top"><a id="a6e4a2e3551a2c80965626b8d50a99f25"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a6e4a2e3551a2c80965626b8d50a99f25">REG_SDHC0_BSR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x45000004UL)</td></tr>
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<tr class="memdesc:a6e4a2e3551a2c80965626b8d50a99f25"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Block Size <br /></td></tr>
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<tr class="separator:a6e4a2e3551a2c80965626b8d50a99f25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adb52791aa544884480994bfa6eb75fd0"><td class="memItemLeft" align="right" valign="top"><a id="adb52791aa544884480994bfa6eb75fd0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#adb52791aa544884480994bfa6eb75fd0">REG_SDHC0_BCR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x45000006UL)</td></tr>
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<tr class="memdesc:adb52791aa544884480994bfa6eb75fd0"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Block Count <br /></td></tr>
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<tr class="separator:adb52791aa544884480994bfa6eb75fd0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad58d1f9c45f36e6fdf46312798880eae"><td class="memItemLeft" align="right" valign="top"><a id="ad58d1f9c45f36e6fdf46312798880eae"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#ad58d1f9c45f36e6fdf46312798880eae">REG_SDHC0_ARG1R</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x45000008UL)</td></tr>
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<tr class="memdesc:ad58d1f9c45f36e6fdf46312798880eae"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Argument 1 <br /></td></tr>
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<tr class="separator:ad58d1f9c45f36e6fdf46312798880eae"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7326f90f66f7ea6c5abc3a67808ee4c3"><td class="memItemLeft" align="right" valign="top"><a id="a7326f90f66f7ea6c5abc3a67808ee4c3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a7326f90f66f7ea6c5abc3a67808ee4c3">REG_SDHC0_TMR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4500000CUL)</td></tr>
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<tr class="memdesc:a7326f90f66f7ea6c5abc3a67808ee4c3"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Transfer Mode <br /></td></tr>
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<tr class="separator:a7326f90f66f7ea6c5abc3a67808ee4c3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acebe2e5b7c8e5a606871e1ef2504dd7d"><td class="memItemLeft" align="right" valign="top"><a id="acebe2e5b7c8e5a606871e1ef2504dd7d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#acebe2e5b7c8e5a606871e1ef2504dd7d">REG_SDHC0_CR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4500000EUL)</td></tr>
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<tr class="memdesc:acebe2e5b7c8e5a606871e1ef2504dd7d"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Command <br /></td></tr>
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<tr class="separator:acebe2e5b7c8e5a606871e1ef2504dd7d"><td class="memSeparator" colspan="2"> </td></tr>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#ad3cd56a71426e6367a4d2c8009cc0f38">REG_SDHC0_RR0</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x45000010UL)</td></tr>
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<tr class="memdesc:ad3cd56a71426e6367a4d2c8009cc0f38"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Response 0 <br /></td></tr>
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<tr class="separator:ad3cd56a71426e6367a4d2c8009cc0f38"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8e35725407edde52eb484ed948e6cd7"><td class="memItemLeft" align="right" valign="top"><a id="af8e35725407edde52eb484ed948e6cd7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#af8e35725407edde52eb484ed948e6cd7">REG_SDHC0_RR1</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x45000014UL)</td></tr>
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<tr class="memdesc:af8e35725407edde52eb484ed948e6cd7"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Response 1 <br /></td></tr>
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<tr class="separator:af8e35725407edde52eb484ed948e6cd7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a455c7976200ddbf1fa9b6bca155828f7"><td class="memItemLeft" align="right" valign="top"><a id="a455c7976200ddbf1fa9b6bca155828f7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a455c7976200ddbf1fa9b6bca155828f7">REG_SDHC0_RR2</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x45000018UL)</td></tr>
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<tr class="memdesc:a455c7976200ddbf1fa9b6bca155828f7"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Response 2 <br /></td></tr>
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<tr class="separator:a455c7976200ddbf1fa9b6bca155828f7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a38420fbdc8db86ff4f5893b6caa335bb"><td class="memItemLeft" align="right" valign="top"><a id="a38420fbdc8db86ff4f5893b6caa335bb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a38420fbdc8db86ff4f5893b6caa335bb">REG_SDHC0_RR3</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x4500001CUL)</td></tr>
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<tr class="memdesc:a38420fbdc8db86ff4f5893b6caa335bb"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Response 3 <br /></td></tr>
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<tr class="separator:a38420fbdc8db86ff4f5893b6caa335bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a59b4ced585ad7176acb3b92739724a5d"><td class="memItemLeft" align="right" valign="top"><a id="a59b4ced585ad7176acb3b92739724a5d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a59b4ced585ad7176acb3b92739724a5d">REG_SDHC0_BDPR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x45000020UL)</td></tr>
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<tr class="memdesc:a59b4ced585ad7176acb3b92739724a5d"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Buffer Data <a class="el" href="structPort.html" title="PORT hardware registers.">Port</a> <br /></td></tr>
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<tr class="separator:a59b4ced585ad7176acb3b92739724a5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae714d8136f42942701851e84f9f8da83"><td class="memItemLeft" align="right" valign="top"><a id="ae714d8136f42942701851e84f9f8da83"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#ae714d8136f42942701851e84f9f8da83">REG_SDHC0_PSR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x45000024UL)</td></tr>
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<tr class="memdesc:ae714d8136f42942701851e84f9f8da83"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Present State <br /></td></tr>
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<tr class="separator:ae714d8136f42942701851e84f9f8da83"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a06b3d080fd02861d1f5ecf1d4f22e462"><td class="memItemLeft" align="right" valign="top"><a id="a06b3d080fd02861d1f5ecf1d4f22e462"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a06b3d080fd02861d1f5ecf1d4f22e462">REG_SDHC0_HC1R</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x45000028UL)</td></tr>
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<tr class="memdesc:a06b3d080fd02861d1f5ecf1d4f22e462"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Host Control 1 <br /></td></tr>
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<tr class="separator:a06b3d080fd02861d1f5ecf1d4f22e462"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a29bdc3880bc43b731a3daaa73cb68e84"><td class="memItemLeft" align="right" valign="top"><a id="a29bdc3880bc43b731a3daaa73cb68e84"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a29bdc3880bc43b731a3daaa73cb68e84">REG_SDHC0_PCR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x45000029UL)</td></tr>
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<tr class="memdesc:a29bdc3880bc43b731a3daaa73cb68e84"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Power Control <br /></td></tr>
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<tr class="separator:a29bdc3880bc43b731a3daaa73cb68e84"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaccd503df351230a5db360fc1601d679"><td class="memItemLeft" align="right" valign="top"><a id="aaccd503df351230a5db360fc1601d679"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#aaccd503df351230a5db360fc1601d679">REG_SDHC0_BGCR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4500002AUL)</td></tr>
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<tr class="memdesc:aaccd503df351230a5db360fc1601d679"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Block Gap Control <br /></td></tr>
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<tr class="separator:aaccd503df351230a5db360fc1601d679"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2ea595abf511c6c02adfec5714ab5fef"><td class="memItemLeft" align="right" valign="top"><a id="a2ea595abf511c6c02adfec5714ab5fef"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a2ea595abf511c6c02adfec5714ab5fef">REG_SDHC0_WCR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4500002BUL)</td></tr>
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<tr class="memdesc:a2ea595abf511c6c02adfec5714ab5fef"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Wakeup Control <br /></td></tr>
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<tr class="separator:a2ea595abf511c6c02adfec5714ab5fef"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac75f9f32870dd366d220260ea3de9431"><td class="memItemLeft" align="right" valign="top"><a id="ac75f9f32870dd366d220260ea3de9431"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#ac75f9f32870dd366d220260ea3de9431">REG_SDHC0_CCR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4500002CUL)</td></tr>
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<tr class="memdesc:ac75f9f32870dd366d220260ea3de9431"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Clock Control <br /></td></tr>
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<tr class="separator:ac75f9f32870dd366d220260ea3de9431"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a54d19d359e5f1a7008e8b06463a7227b"><td class="memItemLeft" align="right" valign="top"><a id="a54d19d359e5f1a7008e8b06463a7227b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a54d19d359e5f1a7008e8b06463a7227b">REG_SDHC0_TCR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4500002EUL)</td></tr>
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<tr class="memdesc:a54d19d359e5f1a7008e8b06463a7227b"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Timeout Control <br /></td></tr>
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<tr class="separator:a54d19d359e5f1a7008e8b06463a7227b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a846bdd51d47c4f9fb956cb94c4898d25"><td class="memItemLeft" align="right" valign="top"><a id="a846bdd51d47c4f9fb956cb94c4898d25"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a846bdd51d47c4f9fb956cb94c4898d25">REG_SDHC0_SRR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x4500002FUL)</td></tr>
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<tr class="memdesc:a846bdd51d47c4f9fb956cb94c4898d25"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Software Reset <br /></td></tr>
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<tr class="separator:a846bdd51d47c4f9fb956cb94c4898d25"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a22e5137d5a791d12287f400cc248a86e"><td class="memItemLeft" align="right" valign="top"><a id="a22e5137d5a791d12287f400cc248a86e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a22e5137d5a791d12287f400cc248a86e">REG_SDHC0_NISTR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x45000030UL)</td></tr>
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<tr class="memdesc:a22e5137d5a791d12287f400cc248a86e"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Normal Interrupt Status <br /></td></tr>
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<tr class="separator:a22e5137d5a791d12287f400cc248a86e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afee4ce1af019f9525680c63bc11c66a5"><td class="memItemLeft" align="right" valign="top"><a id="afee4ce1af019f9525680c63bc11c66a5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#afee4ce1af019f9525680c63bc11c66a5">REG_SDHC0_EISTR</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x45000032UL)</td></tr>
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<tr class="memdesc:afee4ce1af019f9525680c63bc11c66a5"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Error Interrupt Status <br /></td></tr>
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<tr class="separator:afee4ce1af019f9525680c63bc11c66a5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af01e54658554c5ab36e8dbe6404afac2"><td class="memItemLeft" align="right" valign="top"><a id="af01e54658554c5ab36e8dbe6404afac2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#af01e54658554c5ab36e8dbe6404afac2">REG_SDHC0_NISTER</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x45000034UL)</td></tr>
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<tr class="memdesc:af01e54658554c5ab36e8dbe6404afac2"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Normal Interrupt Status Enable <br /></td></tr>
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<tr class="separator:af01e54658554c5ab36e8dbe6404afac2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae42ad685b4c5eb512902caf3c7c28f5f"><td class="memItemLeft" align="right" valign="top"><a id="ae42ad685b4c5eb512902caf3c7c28f5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#ae42ad685b4c5eb512902caf3c7c28f5f">REG_SDHC0_EISTER</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x45000036UL)</td></tr>
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<tr class="memdesc:ae42ad685b4c5eb512902caf3c7c28f5f"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Error Interrupt Status Enable <br /></td></tr>
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<tr class="separator:ae42ad685b4c5eb512902caf3c7c28f5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab2f2ab02827eb11f4880d9b32e010d59"><td class="memItemLeft" align="right" valign="top"><a id="ab2f2ab02827eb11f4880d9b32e010d59"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#ab2f2ab02827eb11f4880d9b32e010d59">REG_SDHC0_NISIER</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x45000038UL)</td></tr>
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<tr class="memdesc:ab2f2ab02827eb11f4880d9b32e010d59"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Normal Interrupt Signal Enable <br /></td></tr>
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<tr class="separator:ab2f2ab02827eb11f4880d9b32e010d59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3c2cfb7ec143b61384b546293c68b3f9"><td class="memItemLeft" align="right" valign="top"><a id="a3c2cfb7ec143b61384b546293c68b3f9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a3c2cfb7ec143b61384b546293c68b3f9">REG_SDHC0_EISIER</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4500003AUL)</td></tr>
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<tr class="memdesc:a3c2cfb7ec143b61384b546293c68b3f9"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Error Interrupt Signal Enable <br /></td></tr>
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<tr class="separator:a3c2cfb7ec143b61384b546293c68b3f9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8219bd02b101c7bcd2af365c2a9fe481"><td class="memItemLeft" align="right" valign="top"><a id="a8219bd02b101c7bcd2af365c2a9fe481"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a8219bd02b101c7bcd2af365c2a9fe481">REG_SDHC0_ACESR</a>   (*(<a class="el" href="same54n19a_8h.html#aebf6e33c2d49a802e06e22a95ea9d0d0">RoReg16</a>*)0x4500003CUL)</td></tr>
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<tr class="memdesc:a8219bd02b101c7bcd2af365c2a9fe481"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Auto CMD Error Status <br /></td></tr>
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<tr class="separator:a8219bd02b101c7bcd2af365c2a9fe481"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab82e5a790d6ec89390c7d4aa5666db5f"><td class="memItemLeft" align="right" valign="top"><a id="ab82e5a790d6ec89390c7d4aa5666db5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#ab82e5a790d6ec89390c7d4aa5666db5f">REG_SDHC0_HC2R</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4500003EUL)</td></tr>
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<tr class="memdesc:ab82e5a790d6ec89390c7d4aa5666db5f"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Host Control 2 <br /></td></tr>
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<tr class="separator:ab82e5a790d6ec89390c7d4aa5666db5f"><td class="memSeparator" colspan="2"> </td></tr>
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|
<tr class="memitem:a865e5cf75b21647416ba9c7ab514c409"><td class="memItemLeft" align="right" valign="top"><a id="a865e5cf75b21647416ba9c7ab514c409"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a865e5cf75b21647416ba9c7ab514c409">REG_SDHC0_CA0R</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x45000040UL)</td></tr>
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<tr class="memdesc:a865e5cf75b21647416ba9c7ab514c409"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Capabilities 0 <br /></td></tr>
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<tr class="separator:a865e5cf75b21647416ba9c7ab514c409"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0b2de4fa31463afcad2c78a7dee8e30f"><td class="memItemLeft" align="right" valign="top"><a id="a0b2de4fa31463afcad2c78a7dee8e30f"></a>
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|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a0b2de4fa31463afcad2c78a7dee8e30f">REG_SDHC0_CA1R</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x45000044UL)</td></tr>
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|
<tr class="memdesc:a0b2de4fa31463afcad2c78a7dee8e30f"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Capabilities 1 <br /></td></tr>
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|
<tr class="separator:a0b2de4fa31463afcad2c78a7dee8e30f"><td class="memSeparator" colspan="2"> </td></tr>
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|
<tr class="memitem:a802640cecf001888af7a8542d200717a"><td class="memItemLeft" align="right" valign="top"><a id="a802640cecf001888af7a8542d200717a"></a>
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|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a802640cecf001888af7a8542d200717a">REG_SDHC0_MCCAR</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x45000048UL)</td></tr>
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|
<tr class="memdesc:a802640cecf001888af7a8542d200717a"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Maximum Current Capabilities <br /></td></tr>
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<tr class="separator:a802640cecf001888af7a8542d200717a"><td class="memSeparator" colspan="2"> </td></tr>
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|
<tr class="memitem:af4b154a9e23d23b3d295a225886ff3db"><td class="memItemLeft" align="right" valign="top"><a id="af4b154a9e23d23b3d295a225886ff3db"></a>
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|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#af4b154a9e23d23b3d295a225886ff3db">REG_SDHC0_FERACES</a>   (*(<a class="el" href="same54n19a_8h.html#a0ab0e5f6c8301aa1c2068e511d854094">WoReg16</a>*)0x45000050UL)</td></tr>
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|
<tr class="memdesc:af4b154a9e23d23b3d295a225886ff3db"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Force Event for Auto CMD Error Status <br /></td></tr>
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|
<tr class="separator:af4b154a9e23d23b3d295a225886ff3db"><td class="memSeparator" colspan="2"> </td></tr>
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|
<tr class="memitem:a113f41481ffa3737bcfa7fc77bcb393c"><td class="memItemLeft" align="right" valign="top"><a id="a113f41481ffa3737bcfa7fc77bcb393c"></a>
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|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a113f41481ffa3737bcfa7fc77bcb393c">REG_SDHC0_FEREIS</a>   (*(<a class="el" href="same54n19a_8h.html#a0ab0e5f6c8301aa1c2068e511d854094">WoReg16</a>*)0x45000052UL)</td></tr>
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|
<tr class="memdesc:a113f41481ffa3737bcfa7fc77bcb393c"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Force Event for Error Interrupt Status <br /></td></tr>
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|
<tr class="separator:a113f41481ffa3737bcfa7fc77bcb393c"><td class="memSeparator" colspan="2"> </td></tr>
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|
<tr class="memitem:abbeb89ce1658423d64509263c505e5ed"><td class="memItemLeft" align="right" valign="top"><a id="abbeb89ce1658423d64509263c505e5ed"></a>
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|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#abbeb89ce1658423d64509263c505e5ed">REG_SDHC0_AESR</a>   (*(<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> *)0x45000054UL)</td></tr>
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|
<tr class="memdesc:abbeb89ce1658423d64509263c505e5ed"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) ADMA Error Status <br /></td></tr>
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<tr class="separator:abbeb89ce1658423d64509263c505e5ed"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a01b67e59d23e1bf5d51c1455c71cbf9d"><td class="memItemLeft" align="right" valign="top"><a id="a01b67e59d23e1bf5d51c1455c71cbf9d"></a>
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|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a01b67e59d23e1bf5d51c1455c71cbf9d">REG_SDHC0_ASAR0</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x45000058UL)</td></tr>
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|
<tr class="memdesc:a01b67e59d23e1bf5d51c1455c71cbf9d"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) ADMA System Address 0 <br /></td></tr>
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|
<tr class="separator:a01b67e59d23e1bf5d51c1455c71cbf9d"><td class="memSeparator" colspan="2"> </td></tr>
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|
<tr class="memitem:a5ededed3623b008b851d6013b71385df"><td class="memItemLeft" align="right" valign="top"><a id="a5ededed3623b008b851d6013b71385df"></a>
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|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a5ededed3623b008b851d6013b71385df">REG_SDHC0_PVR0</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x45000060UL)</td></tr>
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|
<tr class="memdesc:a5ededed3623b008b851d6013b71385df"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Preset Value 0 <br /></td></tr>
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|
<tr class="separator:a5ededed3623b008b851d6013b71385df"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa7f687a5f11f86ca6bbdded8220b3a3f"><td class="memItemLeft" align="right" valign="top"><a id="aa7f687a5f11f86ca6bbdded8220b3a3f"></a>
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|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#aa7f687a5f11f86ca6bbdded8220b3a3f">REG_SDHC0_PVR1</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x45000062UL)</td></tr>
|
|
<tr class="memdesc:aa7f687a5f11f86ca6bbdded8220b3a3f"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Preset Value 1 <br /></td></tr>
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|
<tr class="separator:aa7f687a5f11f86ca6bbdded8220b3a3f"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ae42ac93bc95d1843a9e00f8a080a9abc"><td class="memItemLeft" align="right" valign="top"><a id="ae42ac93bc95d1843a9e00f8a080a9abc"></a>
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|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#ae42ac93bc95d1843a9e00f8a080a9abc">REG_SDHC0_PVR2</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x45000064UL)</td></tr>
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|
<tr class="memdesc:ae42ac93bc95d1843a9e00f8a080a9abc"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Preset Value 2 <br /></td></tr>
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|
<tr class="separator:ae42ac93bc95d1843a9e00f8a080a9abc"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:ac7200583b01b1c23e10721ada67dfb42"><td class="memItemLeft" align="right" valign="top"><a id="ac7200583b01b1c23e10721ada67dfb42"></a>
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|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#ac7200583b01b1c23e10721ada67dfb42">REG_SDHC0_PVR3</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x45000066UL)</td></tr>
|
|
<tr class="memdesc:ac7200583b01b1c23e10721ada67dfb42"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Preset Value 3 <br /></td></tr>
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|
<tr class="separator:ac7200583b01b1c23e10721ada67dfb42"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:af32132b4d1bd45e6034f43e9e29ff786"><td class="memItemLeft" align="right" valign="top"><a id="af32132b4d1bd45e6034f43e9e29ff786"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#af32132b4d1bd45e6034f43e9e29ff786">REG_SDHC0_PVR4</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x45000068UL)</td></tr>
|
|
<tr class="memdesc:af32132b4d1bd45e6034f43e9e29ff786"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Preset Value 4 <br /></td></tr>
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|
<tr class="separator:af32132b4d1bd45e6034f43e9e29ff786"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a83ffc2c8ee862aac765e29a5ef691967"><td class="memItemLeft" align="right" valign="top"><a id="a83ffc2c8ee862aac765e29a5ef691967"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a83ffc2c8ee862aac765e29a5ef691967">REG_SDHC0_PVR5</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4500006AUL)</td></tr>
|
|
<tr class="memdesc:a83ffc2c8ee862aac765e29a5ef691967"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Preset Value 5 <br /></td></tr>
|
|
<tr class="separator:a83ffc2c8ee862aac765e29a5ef691967"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a820e282b1a4a9322e476758aca91afdc"><td class="memItemLeft" align="right" valign="top"><a id="a820e282b1a4a9322e476758aca91afdc"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a820e282b1a4a9322e476758aca91afdc">REG_SDHC0_PVR6</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4500006CUL)</td></tr>
|
|
<tr class="memdesc:a820e282b1a4a9322e476758aca91afdc"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Preset Value 6 <br /></td></tr>
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|
<tr class="separator:a820e282b1a4a9322e476758aca91afdc"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:aa603acee5c06a96653d8f7aadbae7bc3"><td class="memItemLeft" align="right" valign="top"><a id="aa603acee5c06a96653d8f7aadbae7bc3"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#aa603acee5c06a96653d8f7aadbae7bc3">REG_SDHC0_PVR7</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x4500006EUL)</td></tr>
|
|
<tr class="memdesc:aa603acee5c06a96653d8f7aadbae7bc3"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Preset Value 7 <br /></td></tr>
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|
<tr class="separator:aa603acee5c06a96653d8f7aadbae7bc3"><td class="memSeparator" colspan="2"> </td></tr>
|
|
<tr class="memitem:a3cf10b105f2388cf57b4c2a9c483dbba"><td class="memItemLeft" align="right" valign="top"><a id="a3cf10b105f2388cf57b4c2a9c483dbba"></a>
|
|
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a3cf10b105f2388cf57b4c2a9c483dbba">REG_SDHC0_SISR</a>   (*(<a class="el" href="same54n19a_8h.html#aebf6e33c2d49a802e06e22a95ea9d0d0">RoReg16</a>*)0x450000FCUL)</td></tr>
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|
<tr class="memdesc:a3cf10b105f2388cf57b4c2a9c483dbba"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Slot Interrupt Status <br /></td></tr>
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<tr class="separator:a3cf10b105f2388cf57b4c2a9c483dbba"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aec1b9dfc99591aca10aec7dcff241912"><td class="memItemLeft" align="right" valign="top"><a id="aec1b9dfc99591aca10aec7dcff241912"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#aec1b9dfc99591aca10aec7dcff241912">REG_SDHC0_HCVR</a>   (*(<a class="el" href="same54n19a_8h.html#aebf6e33c2d49a802e06e22a95ea9d0d0">RoReg16</a>*)0x450000FEUL)</td></tr>
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<tr class="memdesc:aec1b9dfc99591aca10aec7dcff241912"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Host Controller Version <br /></td></tr>
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<tr class="separator:aec1b9dfc99591aca10aec7dcff241912"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a16d94bce19764c546698dee52d72c33c"><td class="memItemLeft" align="right" valign="top"><a id="a16d94bce19764c546698dee52d72c33c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a16d94bce19764c546698dee52d72c33c">REG_SDHC0_MC1R</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x45000204UL)</td></tr>
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<tr class="memdesc:a16d94bce19764c546698dee52d72c33c"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) MMC Control 1 <br /></td></tr>
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<tr class="separator:a16d94bce19764c546698dee52d72c33c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a293c2130e7b0235b4b2dd126de440343"><td class="memItemLeft" align="right" valign="top"><a id="a293c2130e7b0235b4b2dd126de440343"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a293c2130e7b0235b4b2dd126de440343">REG_SDHC0_MC2R</a>   (*(<a class="el" href="same54n19a_8h.html#a5e336e5a36ee12ebeafb021108e5275b">WoReg8</a> *)0x45000205UL)</td></tr>
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<tr class="memdesc:a293c2130e7b0235b4b2dd126de440343"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) MMC Control 2 <br /></td></tr>
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<tr class="separator:a293c2130e7b0235b4b2dd126de440343"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4d95eb39eecfb3662e5da58c0b6caead"><td class="memItemLeft" align="right" valign="top"><a id="a4d95eb39eecfb3662e5da58c0b6caead"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a4d95eb39eecfb3662e5da58c0b6caead">REG_SDHC0_ACR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x45000208UL)</td></tr>
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<tr class="memdesc:a4d95eb39eecfb3662e5da58c0b6caead"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) AHB Control <br /></td></tr>
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<tr class="separator:a4d95eb39eecfb3662e5da58c0b6caead"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a05190211f9e011750ee27a84d2691bad"><td class="memItemLeft" align="right" valign="top"><a id="a05190211f9e011750ee27a84d2691bad"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a05190211f9e011750ee27a84d2691bad">REG_SDHC0_CC2R</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x4500020CUL)</td></tr>
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<tr class="memdesc:a05190211f9e011750ee27a84d2691bad"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Clock Control 2 <br /></td></tr>
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<tr class="separator:a05190211f9e011750ee27a84d2691bad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a31f207b7486da4fe61b6f3ee94216a1f"><td class="memItemLeft" align="right" valign="top"><a id="a31f207b7486da4fe61b6f3ee94216a1f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a31f207b7486da4fe61b6f3ee94216a1f">REG_SDHC0_CACR</a>   (*(<a class="el" href="same54n19a_8h.html#acf1496e3bbe303e55f627fc7558a68c7">RwReg</a> *)0x45000230UL)</td></tr>
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<tr class="memdesc:a31f207b7486da4fe61b6f3ee94216a1f"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Capabilities Control <br /></td></tr>
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<tr class="separator:a31f207b7486da4fe61b6f3ee94216a1f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9f8587caee794d6f4e61f49cdbadf394"><td class="memItemLeft" align="right" valign="top"><a id="a9f8587caee794d6f4e61f49cdbadf394"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="sdhc0_8h.html#a9f8587caee794d6f4e61f49cdbadf394">REG_SDHC0_DBGR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x45000234UL)</td></tr>
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<tr class="memdesc:a9f8587caee794d6f4e61f49cdbadf394"><td class="mdescLeft"> </td><td class="mdescRight">(SDHC0) Debug <br /></td></tr>
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<tr class="separator:a9f8587caee794d6f4e61f49cdbadf394"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2c99a2ee5a70cd4463ef44ca599ff737"><td class="memItemLeft" align="right" valign="top"><a id="a2c99a2ee5a70cd4463ef44ca599ff737"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC0_CARD_DATA_SIZE</b>   4</td></tr>
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<tr class="separator:a2c99a2ee5a70cd4463ef44ca599ff737"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acd6d46702b6e4332263eefe981c85772"><td class="memItemLeft" align="right" valign="top"><a id="acd6d46702b6e4332263eefe981c85772"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC0_CLK_AHB_ID</b>   15</td></tr>
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<tr class="separator:acd6d46702b6e4332263eefe981c85772"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a01907e6006c9fbac7454c1c5b21f7852"><td class="memItemLeft" align="right" valign="top"><a id="a01907e6006c9fbac7454c1c5b21f7852"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC0_GCLK_ID</b>   45</td></tr>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC0_GCLK_ID_SLOW</b>   3</td></tr>
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<tr class="memitem:aa61b29d59bd0b36888bb6f8070faa85d"><td class="memItemLeft" align="right" valign="top"><a id="aa61b29d59bd0b36888bb6f8070faa85d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC0_NB_OF_DEVICES</b>   1</td></tr>
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<tr class="memitem:afff2609cb59864c3e9a352e48080d019"><td class="memItemLeft" align="right" valign="top"><a id="afff2609cb59864c3e9a352e48080d019"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC0_NB_REG_PVR</b>   8</td></tr>
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<tr class="memitem:abda7c83d8e2a5e6e2a5601296235535b"><td class="memItemLeft" align="right" valign="top"><a id="abda7c83d8e2a5e6e2a5601296235535b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>SDHC0_NB_REG_RR</b>   4</td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Instance description for SDHC0. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="sdhc0_8h_source.html">sdhc0.h</a>.</p>
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