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<div class="title">dsu.h File Reference</div> </div>
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<p>Component description for DSU.
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<p><a href="component_2dsu_8h_source.html">Go to the source code of this file.</a></p>
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Data Structures</h2></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__CTRL__Type.html">DSU_CTRL_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__STATUSA__Type.html">DSU_STATUSA_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__STATUSB__Type.html">DSU_STATUSB_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__ADDR__Type.html">DSU_ADDR_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__LENGTH__Type.html">DSU_LENGTH_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__DATA__Type.html">DSU_DATA_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__DCC__Type.html">DSU_DCC_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__DID__Type.html">DSU_DID_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__CFG__Type.html">DSU_CFG_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__ENTRY0__Type.html">DSU_ENTRY0_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__ENTRY1__Type.html">DSU_ENTRY1_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__END__Type.html">DSU_END_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__MEMTYPE__Type.html">DSU_MEMTYPE_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__PID4__Type.html">DSU_PID4_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__PID5__Type.html">DSU_PID5_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__PID6__Type.html">DSU_PID6_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__PID7__Type.html">DSU_PID7_Type</a></td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__PID0__Type.html">DSU_PID0_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__PID1__Type.html">DSU_PID1_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__PID2__Type.html">DSU_PID2_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__PID3__Type.html">DSU_PID3_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__CID0__Type.html">DSU_CID0_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__CID1__Type.html">DSU_CID1_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__CID2__Type.html">DSU_CID2_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">union  </td><td class="memItemRight" valign="bottom"><a class="el" href="unionDSU__CID3__Type.html">DSU_CID3_Type</a></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct  </td><td class="memItemRight" valign="bottom"><a class="el" href="structDsu.html">Dsu</a></td></tr>
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<tr class="memdesc:"><td class="mdescLeft"> </td><td class="mdescRight">DSU hardware registers. <a href="structDsu.html#details">More...</a><br /></td></tr>
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<tr class="separator:"><td class="memSeparator" colspan="2"> </td></tr>
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</table><table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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Macros</h2></td></tr>
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<tr class="memitem:a5e59b005a1b4be773b6d4452d4892d19"><td class="memItemLeft" align="right" valign="top"><a id="a5e59b005a1b4be773b6d4452d4892d19"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_U2410</b></td></tr>
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<tr class="separator:a5e59b005a1b4be773b6d4452d4892d19"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af465c179d3af87802176de84057eaf96"><td class="memItemLeft" align="right" valign="top"><a id="af465c179d3af87802176de84057eaf96"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>REV_DSU</b>   0x100</td></tr>
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<tr class="separator:af465c179d3af87802176de84057eaf96"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a16d35bf197958eb309724f1d0fd8e842"><td class="memItemLeft" align="right" valign="top"><a id="a16d35bf197958eb309724f1d0fd8e842"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a16d35bf197958eb309724f1d0fd8e842">DSU_CTRL_OFFSET</a>   0x0000</td></tr>
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<tr class="memdesc:a16d35bf197958eb309724f1d0fd8e842"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CTRL offset) Control <br /></td></tr>
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<tr class="separator:a16d35bf197958eb309724f1d0fd8e842"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d27ac9a8ec8798ed407281b387c2fd0"><td class="memItemLeft" align="right" valign="top"><a id="a2d27ac9a8ec8798ed407281b387c2fd0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a2d27ac9a8ec8798ed407281b387c2fd0">DSU_CTRL_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00)</td></tr>
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<tr class="memdesc:a2d27ac9a8ec8798ed407281b387c2fd0"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CTRL reset_value) Control <br /></td></tr>
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<tr class="separator:a2d27ac9a8ec8798ed407281b387c2fd0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d08bbc3f34f53bc95415ac1c3d2ae72"><td class="memItemLeft" align="right" valign="top"><a id="a2d08bbc3f34f53bc95415ac1c3d2ae72"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a2d08bbc3f34f53bc95415ac1c3d2ae72">DSU_CTRL_SWRST_Pos</a>   0</td></tr>
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<tr class="memdesc:a2d08bbc3f34f53bc95415ac1c3d2ae72"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CTRL) Software Reset <br /></td></tr>
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<tr class="separator:a2d08bbc3f34f53bc95415ac1c3d2ae72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a271a775cfa8f562f64ab3a6f0e328a51"><td class="memItemLeft" align="right" valign="top"><a id="a271a775cfa8f562f64ab3a6f0e328a51"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CTRL_SWRST</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#a2d08bbc3f34f53bc95415ac1c3d2ae72">DSU_CTRL_SWRST_Pos</a>)</td></tr>
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<tr class="separator:a271a775cfa8f562f64ab3a6f0e328a51"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f42a18f629eccf5698c46d591b827bc"><td class="memItemLeft" align="right" valign="top"><a id="a3f42a18f629eccf5698c46d591b827bc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a3f42a18f629eccf5698c46d591b827bc">DSU_CTRL_CRC_Pos</a>   2</td></tr>
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<tr class="memdesc:a3f42a18f629eccf5698c46d591b827bc"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CTRL) 32-bit Cyclic Redundancy Code <br /></td></tr>
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<tr class="separator:a3f42a18f629eccf5698c46d591b827bc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa949503f8848f8d688497ed13a2e29b1"><td class="memItemLeft" align="right" valign="top"><a id="aa949503f8848f8d688497ed13a2e29b1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CTRL_CRC</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#a3f42a18f629eccf5698c46d591b827bc">DSU_CTRL_CRC_Pos</a>)</td></tr>
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<tr class="separator:aa949503f8848f8d688497ed13a2e29b1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae2f8bb8c8fde9739e8e15e76b5a052fc"><td class="memItemLeft" align="right" valign="top"><a id="ae2f8bb8c8fde9739e8e15e76b5a052fc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ae2f8bb8c8fde9739e8e15e76b5a052fc">DSU_CTRL_MBIST_Pos</a>   3</td></tr>
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<tr class="memdesc:ae2f8bb8c8fde9739e8e15e76b5a052fc"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CTRL) Memory built-in self-test <br /></td></tr>
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<tr class="separator:ae2f8bb8c8fde9739e8e15e76b5a052fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a29a4889c6f02e7f58d390da5cb809eab"><td class="memItemLeft" align="right" valign="top"><a id="a29a4889c6f02e7f58d390da5cb809eab"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CTRL_MBIST</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#ae2f8bb8c8fde9739e8e15e76b5a052fc">DSU_CTRL_MBIST_Pos</a>)</td></tr>
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<tr class="separator:a29a4889c6f02e7f58d390da5cb809eab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aef5ca1fd2f78e579bae1661fb54ccae7"><td class="memItemLeft" align="right" valign="top"><a id="aef5ca1fd2f78e579bae1661fb54ccae7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aef5ca1fd2f78e579bae1661fb54ccae7">DSU_CTRL_CE_Pos</a>   4</td></tr>
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<tr class="memdesc:aef5ca1fd2f78e579bae1661fb54ccae7"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CTRL) Chip-Erase <br /></td></tr>
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<tr class="separator:aef5ca1fd2f78e579bae1661fb54ccae7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5e11b643b12c8d48be1e324bc42008b6"><td class="memItemLeft" align="right" valign="top"><a id="a5e11b643b12c8d48be1e324bc42008b6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CTRL_CE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#aef5ca1fd2f78e579bae1661fb54ccae7">DSU_CTRL_CE_Pos</a>)</td></tr>
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<tr class="separator:a5e11b643b12c8d48be1e324bc42008b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a73ceacd04bd9669ed1853da944fa0c4a"><td class="memItemLeft" align="right" valign="top"><a id="a73ceacd04bd9669ed1853da944fa0c4a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a73ceacd04bd9669ed1853da944fa0c4a">DSU_CTRL_ARR_Pos</a>   6</td></tr>
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<tr class="memdesc:a73ceacd04bd9669ed1853da944fa0c4a"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CTRL) Auxiliary Row Read <br /></td></tr>
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<tr class="separator:a73ceacd04bd9669ed1853da944fa0c4a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5f2577836c76675ccc10c18819e11f39"><td class="memItemLeft" align="right" valign="top"><a id="a5f2577836c76675ccc10c18819e11f39"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CTRL_ARR</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#a73ceacd04bd9669ed1853da944fa0c4a">DSU_CTRL_ARR_Pos</a>)</td></tr>
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<tr class="separator:a5f2577836c76675ccc10c18819e11f39"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae5bcaa4f2c2619c8cedb1672a23bb902"><td class="memItemLeft" align="right" valign="top"><a id="ae5bcaa4f2c2619c8cedb1672a23bb902"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ae5bcaa4f2c2619c8cedb1672a23bb902">DSU_CTRL_SMSA_Pos</a>   7</td></tr>
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<tr class="memdesc:ae5bcaa4f2c2619c8cedb1672a23bb902"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CTRL) Start Memory Stream Access <br /></td></tr>
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<tr class="separator:ae5bcaa4f2c2619c8cedb1672a23bb902"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a83eade410db4dba9e0ae9930b67e1d4c"><td class="memItemLeft" align="right" valign="top"><a id="a83eade410db4dba9e0ae9930b67e1d4c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CTRL_SMSA</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#ae5bcaa4f2c2619c8cedb1672a23bb902">DSU_CTRL_SMSA_Pos</a>)</td></tr>
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<tr class="separator:a83eade410db4dba9e0ae9930b67e1d4c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad7cc167d8a8791942e3149bd93278134"><td class="memItemLeft" align="right" valign="top"><a id="ad7cc167d8a8791942e3149bd93278134"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ad7cc167d8a8791942e3149bd93278134">DSU_CTRL_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xDD)</td></tr>
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<tr class="memdesc:ad7cc167d8a8791942e3149bd93278134"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CTRL) MASK Register <br /></td></tr>
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<tr class="separator:ad7cc167d8a8791942e3149bd93278134"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5bbcb19f47173c3bdee8ce58b612eac0"><td class="memItemLeft" align="right" valign="top"><a id="a5bbcb19f47173c3bdee8ce58b612eac0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a5bbcb19f47173c3bdee8ce58b612eac0">DSU_STATUSA_OFFSET</a>   0x0001</td></tr>
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<tr class="memdesc:a5bbcb19f47173c3bdee8ce58b612eac0"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSA offset) Status A <br /></td></tr>
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<tr class="separator:a5bbcb19f47173c3bdee8ce58b612eac0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a39ce3f6cadacf2ea11a0e8ab5d6bcd4b"><td class="memItemLeft" align="right" valign="top"><a id="a39ce3f6cadacf2ea11a0e8ab5d6bcd4b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a39ce3f6cadacf2ea11a0e8ab5d6bcd4b">DSU_STATUSA_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00)</td></tr>
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<tr class="memdesc:a39ce3f6cadacf2ea11a0e8ab5d6bcd4b"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSA reset_value) Status A <br /></td></tr>
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<tr class="separator:a39ce3f6cadacf2ea11a0e8ab5d6bcd4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a608007c6aa3ae0221483e370d9ca999b"><td class="memItemLeft" align="right" valign="top"><a id="a608007c6aa3ae0221483e370d9ca999b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a608007c6aa3ae0221483e370d9ca999b">DSU_STATUSA_DONE_Pos</a>   0</td></tr>
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<tr class="memdesc:a608007c6aa3ae0221483e370d9ca999b"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSA) Done <br /></td></tr>
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<tr class="separator:a608007c6aa3ae0221483e370d9ca999b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a824b2ff5600830ebc7971da3eeea0b7b"><td class="memItemLeft" align="right" valign="top"><a id="a824b2ff5600830ebc7971da3eeea0b7b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSA_DONE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#a608007c6aa3ae0221483e370d9ca999b">DSU_STATUSA_DONE_Pos</a>)</td></tr>
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<tr class="separator:a824b2ff5600830ebc7971da3eeea0b7b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab5c6d644e1ec7f67cf2a9ad97a5262a2"><td class="memItemLeft" align="right" valign="top"><a id="ab5c6d644e1ec7f67cf2a9ad97a5262a2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ab5c6d644e1ec7f67cf2a9ad97a5262a2">DSU_STATUSA_CRSTEXT_Pos</a>   1</td></tr>
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<tr class="memdesc:ab5c6d644e1ec7f67cf2a9ad97a5262a2"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSA) CPU Reset Phase Extension <br /></td></tr>
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<tr class="separator:ab5c6d644e1ec7f67cf2a9ad97a5262a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4ce5d24ab18ad2bf2cc5925d30432907"><td class="memItemLeft" align="right" valign="top"><a id="a4ce5d24ab18ad2bf2cc5925d30432907"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSA_CRSTEXT</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#ab5c6d644e1ec7f67cf2a9ad97a5262a2">DSU_STATUSA_CRSTEXT_Pos</a>)</td></tr>
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<tr class="separator:a4ce5d24ab18ad2bf2cc5925d30432907"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afa02b78e838184c6f5a895f0f16c213a"><td class="memItemLeft" align="right" valign="top"><a id="afa02b78e838184c6f5a895f0f16c213a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#afa02b78e838184c6f5a895f0f16c213a">DSU_STATUSA_BERR_Pos</a>   2</td></tr>
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<tr class="memdesc:afa02b78e838184c6f5a895f0f16c213a"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSA) Bus Error <br /></td></tr>
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<tr class="separator:afa02b78e838184c6f5a895f0f16c213a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a74dbd3779decac8f909b6f2fde2df451"><td class="memItemLeft" align="right" valign="top"><a id="a74dbd3779decac8f909b6f2fde2df451"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSA_BERR</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#afa02b78e838184c6f5a895f0f16c213a">DSU_STATUSA_BERR_Pos</a>)</td></tr>
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<tr class="separator:a74dbd3779decac8f909b6f2fde2df451"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a379cd81ca596d64fff4cdf4cd0642e9d"><td class="memItemLeft" align="right" valign="top"><a id="a379cd81ca596d64fff4cdf4cd0642e9d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a379cd81ca596d64fff4cdf4cd0642e9d">DSU_STATUSA_FAIL_Pos</a>   3</td></tr>
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<tr class="memdesc:a379cd81ca596d64fff4cdf4cd0642e9d"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSA) Failure <br /></td></tr>
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<tr class="separator:a379cd81ca596d64fff4cdf4cd0642e9d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acfa2c317afc818826c5ee60f7fd5b06a"><td class="memItemLeft" align="right" valign="top"><a id="acfa2c317afc818826c5ee60f7fd5b06a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSA_FAIL</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#a379cd81ca596d64fff4cdf4cd0642e9d">DSU_STATUSA_FAIL_Pos</a>)</td></tr>
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<tr class="separator:acfa2c317afc818826c5ee60f7fd5b06a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2d5f7f64db290d822709d358b9d8baf6"><td class="memItemLeft" align="right" valign="top"><a id="a2d5f7f64db290d822709d358b9d8baf6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a2d5f7f64db290d822709d358b9d8baf6">DSU_STATUSA_PERR_Pos</a>   4</td></tr>
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<tr class="memdesc:a2d5f7f64db290d822709d358b9d8baf6"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSA) Protection Error <br /></td></tr>
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<tr class="separator:a2d5f7f64db290d822709d358b9d8baf6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0d09a64d9359e44b57ebd1734163e059"><td class="memItemLeft" align="right" valign="top"><a id="a0d09a64d9359e44b57ebd1734163e059"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSA_PERR</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#a2d5f7f64db290d822709d358b9d8baf6">DSU_STATUSA_PERR_Pos</a>)</td></tr>
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<tr class="separator:a0d09a64d9359e44b57ebd1734163e059"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a054a84324fddaaecb1b58f35c2314bc7"><td class="memItemLeft" align="right" valign="top"><a id="a054a84324fddaaecb1b58f35c2314bc7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a054a84324fddaaecb1b58f35c2314bc7">DSU_STATUSA_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1F)</td></tr>
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<tr class="memdesc:a054a84324fddaaecb1b58f35c2314bc7"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSA) MASK Register <br /></td></tr>
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<tr class="separator:a054a84324fddaaecb1b58f35c2314bc7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6633a1098b38470e1cefd46795f0cf93"><td class="memItemLeft" align="right" valign="top"><a id="a6633a1098b38470e1cefd46795f0cf93"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a6633a1098b38470e1cefd46795f0cf93">DSU_STATUSB_OFFSET</a>   0x0002</td></tr>
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<tr class="memdesc:a6633a1098b38470e1cefd46795f0cf93"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSB offset) Status B <br /></td></tr>
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<tr class="separator:a6633a1098b38470e1cefd46795f0cf93"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aef2faaac59541260b63b58569da04dee"><td class="memItemLeft" align="right" valign="top"><a id="aef2faaac59541260b63b58569da04dee"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aef2faaac59541260b63b58569da04dee">DSU_STATUSB_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00)</td></tr>
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<tr class="memdesc:aef2faaac59541260b63b58569da04dee"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSB reset_value) Status B <br /></td></tr>
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<tr class="separator:aef2faaac59541260b63b58569da04dee"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acd0a6b404b8ba52afe784b653e1b4ee7"><td class="memItemLeft" align="right" valign="top"><a id="acd0a6b404b8ba52afe784b653e1b4ee7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#acd0a6b404b8ba52afe784b653e1b4ee7">DSU_STATUSB_PROT_Pos</a>   0</td></tr>
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<tr class="memdesc:acd0a6b404b8ba52afe784b653e1b4ee7"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSB) Protected <br /></td></tr>
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<tr class="separator:acd0a6b404b8ba52afe784b653e1b4ee7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0ba62e190f2b944deffdbfc40a7ce33a"><td class="memItemLeft" align="right" valign="top"><a id="a0ba62e190f2b944deffdbfc40a7ce33a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSB_PROT</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#acd0a6b404b8ba52afe784b653e1b4ee7">DSU_STATUSB_PROT_Pos</a>)</td></tr>
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<tr class="separator:a0ba62e190f2b944deffdbfc40a7ce33a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a36bd47009661963b8c71c9dc4cb62ecb"><td class="memItemLeft" align="right" valign="top"><a id="a36bd47009661963b8c71c9dc4cb62ecb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a36bd47009661963b8c71c9dc4cb62ecb">DSU_STATUSB_DBGPRES_Pos</a>   1</td></tr>
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<tr class="memdesc:a36bd47009661963b8c71c9dc4cb62ecb"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSB) Debugger Present <br /></td></tr>
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<tr class="separator:a36bd47009661963b8c71c9dc4cb62ecb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9eae843ddddb99bef3d7358ccb5e8dc9"><td class="memItemLeft" align="right" valign="top"><a id="a9eae843ddddb99bef3d7358ccb5e8dc9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSB_DBGPRES</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#a36bd47009661963b8c71c9dc4cb62ecb">DSU_STATUSB_DBGPRES_Pos</a>)</td></tr>
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<tr class="separator:a9eae843ddddb99bef3d7358ccb5e8dc9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adc27fc361eacd9fdd30cad6459bdc7c4"><td class="memItemLeft" align="right" valign="top"><a id="adc27fc361eacd9fdd30cad6459bdc7c4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#adc27fc361eacd9fdd30cad6459bdc7c4">DSU_STATUSB_DCCD0_Pos</a>   2</td></tr>
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<tr class="memdesc:adc27fc361eacd9fdd30cad6459bdc7c4"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSB) Debug Communication Channel 0 Dirty <br /></td></tr>
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<tr class="separator:adc27fc361eacd9fdd30cad6459bdc7c4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac68c39af9734e2a6e6db0dc67bf12507"><td class="memItemLeft" align="right" valign="top"><a id="ac68c39af9734e2a6e6db0dc67bf12507"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSB_DCCD0</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(1) << <a class="el" href="component_2dsu_8h.html#adc27fc361eacd9fdd30cad6459bdc7c4">DSU_STATUSB_DCCD0_Pos</a>)</td></tr>
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<tr class="separator:ac68c39af9734e2a6e6db0dc67bf12507"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a43c23fdfaa496f809db2e9b7d0bea8a9"><td class="memItemLeft" align="right" valign="top"><a id="a43c23fdfaa496f809db2e9b7d0bea8a9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a43c23fdfaa496f809db2e9b7d0bea8a9">DSU_STATUSB_DCCD1_Pos</a>   3</td></tr>
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<tr class="memdesc:a43c23fdfaa496f809db2e9b7d0bea8a9"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSB) Debug Communication Channel 1 Dirty <br /></td></tr>
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<tr class="separator:a43c23fdfaa496f809db2e9b7d0bea8a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad229e036a6ca3ec924ca37250b6ea81c"><td class="memItemLeft" align="right" valign="top"><a id="ad229e036a6ca3ec924ca37250b6ea81c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSB_DCCD1</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(1) << <a class="el" href="component_2dsu_8h.html#a43c23fdfaa496f809db2e9b7d0bea8a9">DSU_STATUSB_DCCD1_Pos</a>)</td></tr>
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<tr class="separator:ad229e036a6ca3ec924ca37250b6ea81c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a93a180646ddd3ecc99793ef1b5bde5aa"><td class="memItemLeft" align="right" valign="top"><a id="a93a180646ddd3ecc99793ef1b5bde5aa"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a93a180646ddd3ecc99793ef1b5bde5aa">DSU_STATUSB_DCCD_Pos</a>   2</td></tr>
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<tr class="memdesc:a93a180646ddd3ecc99793ef1b5bde5aa"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSB) Debug Communication Channel x Dirty <br /></td></tr>
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<tr class="separator:a93a180646ddd3ecc99793ef1b5bde5aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a044e55aae67a53e47ac714df1cfda6da"><td class="memItemLeft" align="right" valign="top"><a id="a044e55aae67a53e47ac714df1cfda6da"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSB_DCCD_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3) << <a class="el" href="component_2dsu_8h.html#a93a180646ddd3ecc99793ef1b5bde5aa">DSU_STATUSB_DCCD_Pos</a>)</td></tr>
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<tr class="separator:a044e55aae67a53e47ac714df1cfda6da"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aef2128822b4dc82be7e1c4971676c6ad"><td class="memItemLeft" align="right" valign="top"><a id="aef2128822b4dc82be7e1c4971676c6ad"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSB_DCCD</b>(value)   (DSU_STATUSB_DCCD_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a93a180646ddd3ecc99793ef1b5bde5aa">DSU_STATUSB_DCCD_Pos</a>))</td></tr>
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<tr class="separator:aef2128822b4dc82be7e1c4971676c6ad"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a99433528b614cd9294b33c828a1a5003"><td class="memItemLeft" align="right" valign="top"><a id="a99433528b614cd9294b33c828a1a5003"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a99433528b614cd9294b33c828a1a5003">DSU_STATUSB_HPE_Pos</a>   4</td></tr>
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<tr class="memdesc:a99433528b614cd9294b33c828a1a5003"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSB) Hot-Plugging Enable <br /></td></tr>
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<tr class="separator:a99433528b614cd9294b33c828a1a5003"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab622c042fd6dd7d2d8b619ab875d2cda"><td class="memItemLeft" align="right" valign="top"><a id="ab622c042fd6dd7d2d8b619ab875d2cda"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSB_HPE</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#a99433528b614cd9294b33c828a1a5003">DSU_STATUSB_HPE_Pos</a>)</td></tr>
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<tr class="separator:ab622c042fd6dd7d2d8b619ab875d2cda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa99f386d6e5e61367d5e06aaab7ccb54"><td class="memItemLeft" align="right" valign="top"><a id="aa99f386d6e5e61367d5e06aaab7ccb54"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aa99f386d6e5e61367d5e06aaab7ccb54">DSU_STATUSB_CELCK_Pos</a>   5</td></tr>
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<tr class="memdesc:aa99f386d6e5e61367d5e06aaab7ccb54"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSB) Chip Erase Locked <br /></td></tr>
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<tr class="separator:aa99f386d6e5e61367d5e06aaab7ccb54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7fc255995d133cdb50088b885671f521"><td class="memItemLeft" align="right" valign="top"><a id="a7fc255995d133cdb50088b885671f521"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_STATUSB_CELCK</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#aa99f386d6e5e61367d5e06aaab7ccb54">DSU_STATUSB_CELCK_Pos</a>)</td></tr>
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<tr class="separator:a7fc255995d133cdb50088b885671f521"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a81d42e65d6d856087a32f89cd8ebcc23"><td class="memItemLeft" align="right" valign="top"><a id="a81d42e65d6d856087a32f89cd8ebcc23"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a81d42e65d6d856087a32f89cd8ebcc23">DSU_STATUSB_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3F)</td></tr>
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<tr class="memdesc:a81d42e65d6d856087a32f89cd8ebcc23"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_STATUSB) MASK Register <br /></td></tr>
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<tr class="separator:a81d42e65d6d856087a32f89cd8ebcc23"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abf4bde31f974267a5be16e838fb4c385"><td class="memItemLeft" align="right" valign="top"><a id="abf4bde31f974267a5be16e838fb4c385"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#abf4bde31f974267a5be16e838fb4c385">DSU_ADDR_OFFSET</a>   0x0004</td></tr>
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<tr class="memdesc:abf4bde31f974267a5be16e838fb4c385"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ADDR offset) Address <br /></td></tr>
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<tr class="separator:abf4bde31f974267a5be16e838fb4c385"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a20348917b1dead19b4cf118c7470c2e4"><td class="memItemLeft" align="right" valign="top"><a id="a20348917b1dead19b4cf118c7470c2e4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a20348917b1dead19b4cf118c7470c2e4">DSU_ADDR_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a20348917b1dead19b4cf118c7470c2e4"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ADDR reset_value) Address <br /></td></tr>
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<tr class="separator:a20348917b1dead19b4cf118c7470c2e4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad4121595b48dfe29aaec9b674634bc57"><td class="memItemLeft" align="right" valign="top"><a id="ad4121595b48dfe29aaec9b674634bc57"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ad4121595b48dfe29aaec9b674634bc57">DSU_ADDR_AMOD_Pos</a>   0</td></tr>
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<tr class="memdesc:ad4121595b48dfe29aaec9b674634bc57"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ADDR) Access Mode <br /></td></tr>
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<tr class="separator:ad4121595b48dfe29aaec9b674634bc57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a977bea859b9813e830d1993d5cd0ff86"><td class="memItemLeft" align="right" valign="top"><a id="a977bea859b9813e830d1993d5cd0ff86"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_ADDR_AMOD_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3) << <a class="el" href="component_2dsu_8h.html#ad4121595b48dfe29aaec9b674634bc57">DSU_ADDR_AMOD_Pos</a>)</td></tr>
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<tr class="separator:a977bea859b9813e830d1993d5cd0ff86"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac53e3c3b1ad8d530a190d066ae1396e3"><td class="memItemLeft" align="right" valign="top"><a id="ac53e3c3b1ad8d530a190d066ae1396e3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_ADDR_AMOD</b>(value)   (DSU_ADDR_AMOD_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#ad4121595b48dfe29aaec9b674634bc57">DSU_ADDR_AMOD_Pos</a>))</td></tr>
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<tr class="separator:ac53e3c3b1ad8d530a190d066ae1396e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a028619d29a30f3abc4ff67ce0797952c"><td class="memItemLeft" align="right" valign="top"><a id="a028619d29a30f3abc4ff67ce0797952c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a028619d29a30f3abc4ff67ce0797952c">DSU_ADDR_ADDR_Pos</a>   2</td></tr>
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<tr class="memdesc:a028619d29a30f3abc4ff67ce0797952c"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ADDR) Address <br /></td></tr>
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<tr class="separator:a028619d29a30f3abc4ff67ce0797952c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abd32d0522daddb84bbf02228c190fc49"><td class="memItemLeft" align="right" valign="top"><a id="abd32d0522daddb84bbf02228c190fc49"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_ADDR_ADDR_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3FFFFFFF) << <a class="el" href="component_2dsu_8h.html#a028619d29a30f3abc4ff67ce0797952c">DSU_ADDR_ADDR_Pos</a>)</td></tr>
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<tr class="separator:abd32d0522daddb84bbf02228c190fc49"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a87f4d8a3d868be1f3d8cc880a0b67b65"><td class="memItemLeft" align="right" valign="top"><a id="a87f4d8a3d868be1f3d8cc880a0b67b65"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_ADDR_ADDR</b>(value)   (DSU_ADDR_ADDR_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a028619d29a30f3abc4ff67ce0797952c">DSU_ADDR_ADDR_Pos</a>))</td></tr>
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<tr class="separator:a87f4d8a3d868be1f3d8cc880a0b67b65"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adfb5c4d624bfbe3736315ad712fc3238"><td class="memItemLeft" align="right" valign="top"><a id="adfb5c4d624bfbe3736315ad712fc3238"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#adfb5c4d624bfbe3736315ad712fc3238">DSU_ADDR_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFF)</td></tr>
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<tr class="memdesc:adfb5c4d624bfbe3736315ad712fc3238"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ADDR) MASK Register <br /></td></tr>
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<tr class="separator:adfb5c4d624bfbe3736315ad712fc3238"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa51326ede30d0596a90a8758846527b9"><td class="memItemLeft" align="right" valign="top"><a id="aa51326ede30d0596a90a8758846527b9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aa51326ede30d0596a90a8758846527b9">DSU_LENGTH_OFFSET</a>   0x0008</td></tr>
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<tr class="memdesc:aa51326ede30d0596a90a8758846527b9"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_LENGTH offset) Length <br /></td></tr>
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<tr class="separator:aa51326ede30d0596a90a8758846527b9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a055ab4dd190617fd309ed8db03c185ac"><td class="memItemLeft" align="right" valign="top"><a id="a055ab4dd190617fd309ed8db03c185ac"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a055ab4dd190617fd309ed8db03c185ac">DSU_LENGTH_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a055ab4dd190617fd309ed8db03c185ac"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_LENGTH reset_value) Length <br /></td></tr>
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<tr class="separator:a055ab4dd190617fd309ed8db03c185ac"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6aa7babac0719eb769c08ca1a945aa57"><td class="memItemLeft" align="right" valign="top"><a id="a6aa7babac0719eb769c08ca1a945aa57"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a6aa7babac0719eb769c08ca1a945aa57">DSU_LENGTH_LENGTH_Pos</a>   2</td></tr>
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<tr class="memdesc:a6aa7babac0719eb769c08ca1a945aa57"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_LENGTH) Length <br /></td></tr>
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<tr class="separator:a6aa7babac0719eb769c08ca1a945aa57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af8420428fca225dd9b92fb53c4498124"><td class="memItemLeft" align="right" valign="top"><a id="af8420428fca225dd9b92fb53c4498124"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_LENGTH_LENGTH_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3FFFFFFF) << <a class="el" href="component_2dsu_8h.html#a6aa7babac0719eb769c08ca1a945aa57">DSU_LENGTH_LENGTH_Pos</a>)</td></tr>
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<tr class="separator:af8420428fca225dd9b92fb53c4498124"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a89bbb4abfbd477e9791957d57d5baf5f"><td class="memItemLeft" align="right" valign="top"><a id="a89bbb4abfbd477e9791957d57d5baf5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_LENGTH_LENGTH</b>(value)   (DSU_LENGTH_LENGTH_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a6aa7babac0719eb769c08ca1a945aa57">DSU_LENGTH_LENGTH_Pos</a>))</td></tr>
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<tr class="separator:a89bbb4abfbd477e9791957d57d5baf5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1bdb22215616287bf9f8ee6b97e7f803"><td class="memItemLeft" align="right" valign="top"><a id="a1bdb22215616287bf9f8ee6b97e7f803"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a1bdb22215616287bf9f8ee6b97e7f803">DSU_LENGTH_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFC)</td></tr>
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<tr class="memdesc:a1bdb22215616287bf9f8ee6b97e7f803"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_LENGTH) MASK Register <br /></td></tr>
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<tr class="separator:a1bdb22215616287bf9f8ee6b97e7f803"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a723e04c18648c402a75cce7e93de351a"><td class="memItemLeft" align="right" valign="top"><a id="a723e04c18648c402a75cce7e93de351a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a723e04c18648c402a75cce7e93de351a">DSU_DATA_OFFSET</a>   0x000C</td></tr>
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<tr class="memdesc:a723e04c18648c402a75cce7e93de351a"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DATA offset) Data <br /></td></tr>
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<tr class="separator:a723e04c18648c402a75cce7e93de351a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3a9b805b6870ba197f179b0c6cc366ab"><td class="memItemLeft" align="right" valign="top"><a id="a3a9b805b6870ba197f179b0c6cc366ab"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a3a9b805b6870ba197f179b0c6cc366ab">DSU_DATA_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a3a9b805b6870ba197f179b0c6cc366ab"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DATA reset_value) Data <br /></td></tr>
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<tr class="separator:a3a9b805b6870ba197f179b0c6cc366ab"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a035409bf73a654618f87c65e2742bc35"><td class="memItemLeft" align="right" valign="top"><a id="a035409bf73a654618f87c65e2742bc35"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a035409bf73a654618f87c65e2742bc35">DSU_DATA_DATA_Pos</a>   0</td></tr>
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<tr class="memdesc:a035409bf73a654618f87c65e2742bc35"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DATA) Data <br /></td></tr>
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<tr class="separator:a035409bf73a654618f87c65e2742bc35"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a23b8e4cde6cb91cf05bb65a48c1250c2"><td class="memItemLeft" align="right" valign="top"><a id="a23b8e4cde6cb91cf05bb65a48c1250c2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DATA_DATA_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFF) << <a class="el" href="component_2dsu_8h.html#a035409bf73a654618f87c65e2742bc35">DSU_DATA_DATA_Pos</a>)</td></tr>
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<tr class="separator:a23b8e4cde6cb91cf05bb65a48c1250c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeb9ece8dc9d2857876bb710844551cda"><td class="memItemLeft" align="right" valign="top"><a id="aeb9ece8dc9d2857876bb710844551cda"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DATA_DATA</b>(value)   (DSU_DATA_DATA_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a035409bf73a654618f87c65e2742bc35">DSU_DATA_DATA_Pos</a>))</td></tr>
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<tr class="separator:aeb9ece8dc9d2857876bb710844551cda"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8ef0cc4d206f8b748482d8f40d4743e5"><td class="memItemLeft" align="right" valign="top"><a id="a8ef0cc4d206f8b748482d8f40d4743e5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a8ef0cc4d206f8b748482d8f40d4743e5">DSU_DATA_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFF)</td></tr>
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<tr class="memdesc:a8ef0cc4d206f8b748482d8f40d4743e5"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DATA) MASK Register <br /></td></tr>
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<tr class="separator:a8ef0cc4d206f8b748482d8f40d4743e5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a79bf45c7c66b3d6ce28c7c9f9e6b3b89"><td class="memItemLeft" align="right" valign="top"><a id="a79bf45c7c66b3d6ce28c7c9f9e6b3b89"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a79bf45c7c66b3d6ce28c7c9f9e6b3b89">DSU_DCC_OFFSET</a>   0x0010</td></tr>
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<tr class="memdesc:a79bf45c7c66b3d6ce28c7c9f9e6b3b89"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DCC offset) Debug Communication Channel n <br /></td></tr>
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<tr class="separator:a79bf45c7c66b3d6ce28c7c9f9e6b3b89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af005efb1f6ed05574d398463365093b8"><td class="memItemLeft" align="right" valign="top"><a id="af005efb1f6ed05574d398463365093b8"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#af005efb1f6ed05574d398463365093b8">DSU_DCC_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:af005efb1f6ed05574d398463365093b8"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DCC reset_value) Debug Communication Channel n <br /></td></tr>
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<tr class="separator:af005efb1f6ed05574d398463365093b8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5d96d9ba36151557c8211afc631280c6"><td class="memItemLeft" align="right" valign="top"><a id="a5d96d9ba36151557c8211afc631280c6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a5d96d9ba36151557c8211afc631280c6">DSU_DCC_DATA_Pos</a>   0</td></tr>
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<tr class="memdesc:a5d96d9ba36151557c8211afc631280c6"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DCC) Data <br /></td></tr>
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<tr class="separator:a5d96d9ba36151557c8211afc631280c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10a910bf866c48cce4bafb987cdbe360"><td class="memItemLeft" align="right" valign="top"><a id="a10a910bf866c48cce4bafb987cdbe360"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DCC_DATA_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFF) << <a class="el" href="component_2dsu_8h.html#a5d96d9ba36151557c8211afc631280c6">DSU_DCC_DATA_Pos</a>)</td></tr>
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<tr class="separator:a10a910bf866c48cce4bafb987cdbe360"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a64c66dc7faaa799d1f4f852504d8e65c"><td class="memItemLeft" align="right" valign="top"><a id="a64c66dc7faaa799d1f4f852504d8e65c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DCC_DATA</b>(value)   (DSU_DCC_DATA_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a5d96d9ba36151557c8211afc631280c6">DSU_DCC_DATA_Pos</a>))</td></tr>
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<tr class="separator:a64c66dc7faaa799d1f4f852504d8e65c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a68f123ca6976eeb7b1320d0075b315d2"><td class="memItemLeft" align="right" valign="top"><a id="a68f123ca6976eeb7b1320d0075b315d2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a68f123ca6976eeb7b1320d0075b315d2">DSU_DCC_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFF)</td></tr>
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<tr class="memdesc:a68f123ca6976eeb7b1320d0075b315d2"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DCC) MASK Register <br /></td></tr>
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<tr class="separator:a68f123ca6976eeb7b1320d0075b315d2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1f8a682ec241602def0bb6f06481e4ed"><td class="memItemLeft" align="right" valign="top"><a id="a1f8a682ec241602def0bb6f06481e4ed"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a1f8a682ec241602def0bb6f06481e4ed">DSU_DID_OFFSET</a>   0x0018</td></tr>
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<tr class="memdesc:a1f8a682ec241602def0bb6f06481e4ed"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID offset) Device Identification <br /></td></tr>
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<tr class="separator:a1f8a682ec241602def0bb6f06481e4ed"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af7877874825444352e8c546a2e1a2595"><td class="memItemLeft" align="right" valign="top"><a id="af7877874825444352e8c546a2e1a2595"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#af7877874825444352e8c546a2e1a2595">DSU_DID_DEVSEL_Pos</a>   0</td></tr>
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<tr class="memdesc:af7877874825444352e8c546a2e1a2595"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Device Select <br /></td></tr>
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<tr class="separator:af7877874825444352e8c546a2e1a2595"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a00a89f3dabb49fc218fa169f510affb1"><td class="memItemLeft" align="right" valign="top"><a id="a00a89f3dabb49fc218fa169f510affb1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_DEVSEL_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFF) << <a class="el" href="component_2dsu_8h.html#af7877874825444352e8c546a2e1a2595">DSU_DID_DEVSEL_Pos</a>)</td></tr>
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<tr class="separator:a00a89f3dabb49fc218fa169f510affb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae7f77a8a06e459bf42b0bb130c1a1e58"><td class="memItemLeft" align="right" valign="top"><a id="ae7f77a8a06e459bf42b0bb130c1a1e58"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_DEVSEL</b>(value)   (DSU_DID_DEVSEL_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#af7877874825444352e8c546a2e1a2595">DSU_DID_DEVSEL_Pos</a>))</td></tr>
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<tr class="separator:ae7f77a8a06e459bf42b0bb130c1a1e58"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adf8c7ee986cf2cceec0a4d82efb513a2"><td class="memItemLeft" align="right" valign="top"><a id="adf8c7ee986cf2cceec0a4d82efb513a2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#adf8c7ee986cf2cceec0a4d82efb513a2">DSU_DID_REVISION_Pos</a>   8</td></tr>
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<tr class="memdesc:adf8c7ee986cf2cceec0a4d82efb513a2"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Revision Number <br /></td></tr>
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<tr class="separator:adf8c7ee986cf2cceec0a4d82efb513a2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab5dba5b8a06073b6c8a2cdffe5b4fc20"><td class="memItemLeft" align="right" valign="top"><a id="ab5dba5b8a06073b6c8a2cdffe5b4fc20"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_REVISION_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2dsu_8h.html#adf8c7ee986cf2cceec0a4d82efb513a2">DSU_DID_REVISION_Pos</a>)</td></tr>
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<tr class="separator:ab5dba5b8a06073b6c8a2cdffe5b4fc20"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1c662b22d53f1e09610c2c4df24e26d8"><td class="memItemLeft" align="right" valign="top"><a id="a1c662b22d53f1e09610c2c4df24e26d8"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_REVISION</b>(value)   (DSU_DID_REVISION_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#adf8c7ee986cf2cceec0a4d82efb513a2">DSU_DID_REVISION_Pos</a>))</td></tr>
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<tr class="separator:a1c662b22d53f1e09610c2c4df24e26d8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acd344f630eefc7e02ceb5f8210017b8b"><td class="memItemLeft" align="right" valign="top"><a id="acd344f630eefc7e02ceb5f8210017b8b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#acd344f630eefc7e02ceb5f8210017b8b">DSU_DID_DIE_Pos</a>   12</td></tr>
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<tr class="memdesc:acd344f630eefc7e02ceb5f8210017b8b"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Die Number <br /></td></tr>
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<tr class="separator:acd344f630eefc7e02ceb5f8210017b8b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a41443f7e74fd63e24f7990557d9ebb28"><td class="memItemLeft" align="right" valign="top"><a id="a41443f7e74fd63e24f7990557d9ebb28"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_DIE_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2dsu_8h.html#acd344f630eefc7e02ceb5f8210017b8b">DSU_DID_DIE_Pos</a>)</td></tr>
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<tr class="separator:a41443f7e74fd63e24f7990557d9ebb28"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:adcbee73ae2aeed99b44050be79c41b6d"><td class="memItemLeft" align="right" valign="top"><a id="adcbee73ae2aeed99b44050be79c41b6d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_DIE</b>(value)   (DSU_DID_DIE_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#acd344f630eefc7e02ceb5f8210017b8b">DSU_DID_DIE_Pos</a>))</td></tr>
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<tr class="separator:adcbee73ae2aeed99b44050be79c41b6d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7f9f64f65c0ec3d507ba5bc03b1a9b68"><td class="memItemLeft" align="right" valign="top"><a id="a7f9f64f65c0ec3d507ba5bc03b1a9b68"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a7f9f64f65c0ec3d507ba5bc03b1a9b68">DSU_DID_SERIES_Pos</a>   16</td></tr>
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<tr class="memdesc:a7f9f64f65c0ec3d507ba5bc03b1a9b68"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Series <br /></td></tr>
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<tr class="separator:a7f9f64f65c0ec3d507ba5bc03b1a9b68"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af0a694364add4f49a3d7ad19af011e0b"><td class="memItemLeft" align="right" valign="top"><a id="af0a694364add4f49a3d7ad19af011e0b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_SERIES_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3F) << <a class="el" href="component_2dsu_8h.html#a7f9f64f65c0ec3d507ba5bc03b1a9b68">DSU_DID_SERIES_Pos</a>)</td></tr>
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<tr class="separator:af0a694364add4f49a3d7ad19af011e0b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa8e2293c54c5435c7b90cc4ab8b0c91b"><td class="memItemLeft" align="right" valign="top"><a id="aa8e2293c54c5435c7b90cc4ab8b0c91b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_SERIES</b>(value)   (DSU_DID_SERIES_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a7f9f64f65c0ec3d507ba5bc03b1a9b68">DSU_DID_SERIES_Pos</a>))</td></tr>
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<tr class="separator:aa8e2293c54c5435c7b90cc4ab8b0c91b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa55d2175bbc40ac9d81bd297a4241916"><td class="memItemLeft" align="right" valign="top"><a id="aa55d2175bbc40ac9d81bd297a4241916"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aa55d2175bbc40ac9d81bd297a4241916">DSU_DID_SERIES_0_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0)</td></tr>
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<tr class="memdesc:aa55d2175bbc40ac9d81bd297a4241916"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Cortex-M0+ processor, basic feature set <br /></td></tr>
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<tr class="separator:aa55d2175bbc40ac9d81bd297a4241916"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5b1ab97381d29e6d852f6ef0aec8f479"><td class="memItemLeft" align="right" valign="top"><a id="a5b1ab97381d29e6d852f6ef0aec8f479"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a5b1ab97381d29e6d852f6ef0aec8f479">DSU_DID_SERIES_1_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1)</td></tr>
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<tr class="memdesc:a5b1ab97381d29e6d852f6ef0aec8f479"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Cortex-M0+ processor, USB <br /></td></tr>
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<tr class="separator:a5b1ab97381d29e6d852f6ef0aec8f479"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad25a0fe0a4a9ee82609243db4147eaeb"><td class="memItemLeft" align="right" valign="top"><a id="ad25a0fe0a4a9ee82609243db4147eaeb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_SERIES_0</b>   (<a class="el" href="component_2dsu_8h.html#aa55d2175bbc40ac9d81bd297a4241916">DSU_DID_SERIES_0_Val</a> << <a class="el" href="component_2dsu_8h.html#a7f9f64f65c0ec3d507ba5bc03b1a9b68">DSU_DID_SERIES_Pos</a>)</td></tr>
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<tr class="separator:ad25a0fe0a4a9ee82609243db4147eaeb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0393d52bdee9a481f611e749fad390ec"><td class="memItemLeft" align="right" valign="top"><a id="a0393d52bdee9a481f611e749fad390ec"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_SERIES_1</b>   (<a class="el" href="component_2dsu_8h.html#a5b1ab97381d29e6d852f6ef0aec8f479">DSU_DID_SERIES_1_Val</a> << <a class="el" href="component_2dsu_8h.html#a7f9f64f65c0ec3d507ba5bc03b1a9b68">DSU_DID_SERIES_Pos</a>)</td></tr>
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<tr class="separator:a0393d52bdee9a481f611e749fad390ec"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a738ead915cfef1cb2261b900bc2125e7"><td class="memItemLeft" align="right" valign="top"><a id="a738ead915cfef1cb2261b900bc2125e7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a738ead915cfef1cb2261b900bc2125e7">DSU_DID_FAMILY_Pos</a>   23</td></tr>
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<tr class="memdesc:a738ead915cfef1cb2261b900bc2125e7"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Family <br /></td></tr>
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<tr class="separator:a738ead915cfef1cb2261b900bc2125e7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afadbeccaa25afb79e44bfa3e1585c116"><td class="memItemLeft" align="right" valign="top"><a id="afadbeccaa25afb79e44bfa3e1585c116"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_FAMILY_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1F) << <a class="el" href="component_2dsu_8h.html#a738ead915cfef1cb2261b900bc2125e7">DSU_DID_FAMILY_Pos</a>)</td></tr>
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<tr class="separator:afadbeccaa25afb79e44bfa3e1585c116"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a60b98d79fd8846339905b75d8df68abb"><td class="memItemLeft" align="right" valign="top"><a id="a60b98d79fd8846339905b75d8df68abb"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_FAMILY</b>(value)   (DSU_DID_FAMILY_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a738ead915cfef1cb2261b900bc2125e7">DSU_DID_FAMILY_Pos</a>))</td></tr>
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<tr class="separator:a60b98d79fd8846339905b75d8df68abb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa68390a3dd287f0f36e30d40994bcb1e"><td class="memItemLeft" align="right" valign="top"><a id="aa68390a3dd287f0f36e30d40994bcb1e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aa68390a3dd287f0f36e30d40994bcb1e">DSU_DID_FAMILY_0_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0)</td></tr>
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<tr class="memdesc:aa68390a3dd287f0f36e30d40994bcb1e"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) General purpose microcontroller <br /></td></tr>
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<tr class="separator:aa68390a3dd287f0f36e30d40994bcb1e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ade6548ba38e36d9bd1487d02b2825f1c"><td class="memItemLeft" align="right" valign="top"><a id="ade6548ba38e36d9bd1487d02b2825f1c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ade6548ba38e36d9bd1487d02b2825f1c">DSU_DID_FAMILY_1_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1)</td></tr>
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<tr class="memdesc:ade6548ba38e36d9bd1487d02b2825f1c"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) PicoPower <br /></td></tr>
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<tr class="separator:ade6548ba38e36d9bd1487d02b2825f1c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab7d711b0df12398741eb2ff32acb54f6"><td class="memItemLeft" align="right" valign="top"><a id="ab7d711b0df12398741eb2ff32acb54f6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_FAMILY_0</b>   (<a class="el" href="component_2dsu_8h.html#aa68390a3dd287f0f36e30d40994bcb1e">DSU_DID_FAMILY_0_Val</a> << <a class="el" href="component_2dsu_8h.html#a738ead915cfef1cb2261b900bc2125e7">DSU_DID_FAMILY_Pos</a>)</td></tr>
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<tr class="separator:ab7d711b0df12398741eb2ff32acb54f6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a275b17cc8a72d0075cb1d867c8a253aa"><td class="memItemLeft" align="right" valign="top"><a id="a275b17cc8a72d0075cb1d867c8a253aa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_FAMILY_1</b>   (<a class="el" href="component_2dsu_8h.html#ade6548ba38e36d9bd1487d02b2825f1c">DSU_DID_FAMILY_1_Val</a> << <a class="el" href="component_2dsu_8h.html#a738ead915cfef1cb2261b900bc2125e7">DSU_DID_FAMILY_Pos</a>)</td></tr>
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<tr class="separator:a275b17cc8a72d0075cb1d867c8a253aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af39e8c9b37c218a74228db9507493fa2"><td class="memItemLeft" align="right" valign="top"><a id="af39e8c9b37c218a74228db9507493fa2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#af39e8c9b37c218a74228db9507493fa2">DSU_DID_PROCESSOR_Pos</a>   28</td></tr>
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<tr class="memdesc:af39e8c9b37c218a74228db9507493fa2"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Processor <br /></td></tr>
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<tr class="separator:af39e8c9b37c218a74228db9507493fa2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad4accb27c5fd296512c1ed43dd84c93d"><td class="memItemLeft" align="right" valign="top"><a id="ad4accb27c5fd296512c1ed43dd84c93d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_PROCESSOR_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2dsu_8h.html#af39e8c9b37c218a74228db9507493fa2">DSU_DID_PROCESSOR_Pos</a>)</td></tr>
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<tr class="separator:ad4accb27c5fd296512c1ed43dd84c93d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7631b295029e2c4f2068fb1aeef05634"><td class="memItemLeft" align="right" valign="top"><a id="a7631b295029e2c4f2068fb1aeef05634"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_PROCESSOR</b>(value)   (DSU_DID_PROCESSOR_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#af39e8c9b37c218a74228db9507493fa2">DSU_DID_PROCESSOR_Pos</a>))</td></tr>
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<tr class="separator:a7631b295029e2c4f2068fb1aeef05634"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab0125f19b1c66669ea789521e33360c6"><td class="memItemLeft" align="right" valign="top"><a id="ab0125f19b1c66669ea789521e33360c6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ab0125f19b1c66669ea789521e33360c6">DSU_DID_PROCESSOR_CM0P_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1)</td></tr>
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<tr class="memdesc:ab0125f19b1c66669ea789521e33360c6"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Cortex-M0+ <br /></td></tr>
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<tr class="separator:ab0125f19b1c66669ea789521e33360c6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0df4a2a0af94a6b4490a23d5c4b03bfd"><td class="memItemLeft" align="right" valign="top"><a id="a0df4a2a0af94a6b4490a23d5c4b03bfd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a0df4a2a0af94a6b4490a23d5c4b03bfd">DSU_DID_PROCESSOR_CM23_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x2)</td></tr>
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<tr class="memdesc:a0df4a2a0af94a6b4490a23d5c4b03bfd"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Cortex-M23 <br /></td></tr>
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<tr class="separator:a0df4a2a0af94a6b4490a23d5c4b03bfd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abfb5d107e61e5ec48206450c921b4a4b"><td class="memItemLeft" align="right" valign="top"><a id="abfb5d107e61e5ec48206450c921b4a4b"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#abfb5d107e61e5ec48206450c921b4a4b">DSU_DID_PROCESSOR_CM3_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3)</td></tr>
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<tr class="memdesc:abfb5d107e61e5ec48206450c921b4a4b"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Cortex-M3 <br /></td></tr>
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<tr class="separator:abfb5d107e61e5ec48206450c921b4a4b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a534a13e2a895ca387b30d5a195e6b824"><td class="memItemLeft" align="right" valign="top"><a id="a534a13e2a895ca387b30d5a195e6b824"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a534a13e2a895ca387b30d5a195e6b824">DSU_DID_PROCESSOR_CM4_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x5)</td></tr>
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<tr class="memdesc:a534a13e2a895ca387b30d5a195e6b824"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Cortex-M4 <br /></td></tr>
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<tr class="separator:a534a13e2a895ca387b30d5a195e6b824"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afa6c40dc54282a41cc1fc2aba638ba9c"><td class="memItemLeft" align="right" valign="top"><a id="afa6c40dc54282a41cc1fc2aba638ba9c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#afa6c40dc54282a41cc1fc2aba638ba9c">DSU_DID_PROCESSOR_CM4F_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x6)</td></tr>
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<tr class="memdesc:afa6c40dc54282a41cc1fc2aba638ba9c"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Cortex-M4 with FPU <br /></td></tr>
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<tr class="separator:afa6c40dc54282a41cc1fc2aba638ba9c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a02cfd62c099a7754ee0b6339d6b8bc8c"><td class="memItemLeft" align="right" valign="top"><a id="a02cfd62c099a7754ee0b6339d6b8bc8c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a02cfd62c099a7754ee0b6339d6b8bc8c">DSU_DID_PROCESSOR_CM33_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x7)</td></tr>
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<tr class="memdesc:a02cfd62c099a7754ee0b6339d6b8bc8c"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) Cortex-M33 <br /></td></tr>
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<tr class="separator:a02cfd62c099a7754ee0b6339d6b8bc8c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a74f458934fcc3c777641b92064bb6700"><td class="memItemLeft" align="right" valign="top"><a id="a74f458934fcc3c777641b92064bb6700"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_PROCESSOR_CM0P</b>   (<a class="el" href="component_2dsu_8h.html#ab0125f19b1c66669ea789521e33360c6">DSU_DID_PROCESSOR_CM0P_Val</a> << <a class="el" href="component_2dsu_8h.html#af39e8c9b37c218a74228db9507493fa2">DSU_DID_PROCESSOR_Pos</a>)</td></tr>
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<tr class="separator:a74f458934fcc3c777641b92064bb6700"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a483520476495bbfe809ddcffdafc8669"><td class="memItemLeft" align="right" valign="top"><a id="a483520476495bbfe809ddcffdafc8669"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_PROCESSOR_CM23</b>   (<a class="el" href="component_2dsu_8h.html#a0df4a2a0af94a6b4490a23d5c4b03bfd">DSU_DID_PROCESSOR_CM23_Val</a> << <a class="el" href="component_2dsu_8h.html#af39e8c9b37c218a74228db9507493fa2">DSU_DID_PROCESSOR_Pos</a>)</td></tr>
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<tr class="separator:a483520476495bbfe809ddcffdafc8669"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aff20fc234e9894d23c485c69da737f9f"><td class="memItemLeft" align="right" valign="top"><a id="aff20fc234e9894d23c485c69da737f9f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_PROCESSOR_CM3</b>   (<a class="el" href="component_2dsu_8h.html#abfb5d107e61e5ec48206450c921b4a4b">DSU_DID_PROCESSOR_CM3_Val</a> << <a class="el" href="component_2dsu_8h.html#af39e8c9b37c218a74228db9507493fa2">DSU_DID_PROCESSOR_Pos</a>)</td></tr>
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<tr class="separator:aff20fc234e9894d23c485c69da737f9f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a29c82146d2cc3d42a255993e77092396"><td class="memItemLeft" align="right" valign="top"><a id="a29c82146d2cc3d42a255993e77092396"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_PROCESSOR_CM4</b>   (<a class="el" href="component_2dsu_8h.html#a534a13e2a895ca387b30d5a195e6b824">DSU_DID_PROCESSOR_CM4_Val</a> << <a class="el" href="component_2dsu_8h.html#af39e8c9b37c218a74228db9507493fa2">DSU_DID_PROCESSOR_Pos</a>)</td></tr>
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<tr class="separator:a29c82146d2cc3d42a255993e77092396"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a84860ec98ee0f3636028fb7ff4d44c09"><td class="memItemLeft" align="right" valign="top"><a id="a84860ec98ee0f3636028fb7ff4d44c09"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_PROCESSOR_CM4F</b>   (<a class="el" href="component_2dsu_8h.html#afa6c40dc54282a41cc1fc2aba638ba9c">DSU_DID_PROCESSOR_CM4F_Val</a> << <a class="el" href="component_2dsu_8h.html#af39e8c9b37c218a74228db9507493fa2">DSU_DID_PROCESSOR_Pos</a>)</td></tr>
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<tr class="separator:a84860ec98ee0f3636028fb7ff4d44c09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac8d5fb96f5ae740ba7bdfe736c0a9860"><td class="memItemLeft" align="right" valign="top"><a id="ac8d5fb96f5ae740ba7bdfe736c0a9860"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_DID_PROCESSOR_CM33</b>   (<a class="el" href="component_2dsu_8h.html#a02cfd62c099a7754ee0b6339d6b8bc8c">DSU_DID_PROCESSOR_CM33_Val</a> << <a class="el" href="component_2dsu_8h.html#af39e8c9b37c218a74228db9507493fa2">DSU_DID_PROCESSOR_Pos</a>)</td></tr>
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<tr class="separator:ac8d5fb96f5ae740ba7bdfe736c0a9860"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac1403dba443577379c24df9d1bff8cb1"><td class="memItemLeft" align="right" valign="top"><a id="ac1403dba443577379c24df9d1bff8cb1"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ac1403dba443577379c24df9d1bff8cb1">DSU_DID_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFBFFFFF)</td></tr>
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<tr class="memdesc:ac1403dba443577379c24df9d1bff8cb1"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_DID) MASK Register <br /></td></tr>
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<tr class="separator:ac1403dba443577379c24df9d1bff8cb1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8c62f4d1e6354ed3d19a6f1d0106e246"><td class="memItemLeft" align="right" valign="top"><a id="a8c62f4d1e6354ed3d19a6f1d0106e246"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a8c62f4d1e6354ed3d19a6f1d0106e246">DSU_CFG_OFFSET</a>   0x001C</td></tr>
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<tr class="memdesc:a8c62f4d1e6354ed3d19a6f1d0106e246"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CFG offset) Configuration <br /></td></tr>
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<tr class="separator:a8c62f4d1e6354ed3d19a6f1d0106e246"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8e3905dda579f2cd6b30b66ed021a0b5"><td class="memItemLeft" align="right" valign="top"><a id="a8e3905dda579f2cd6b30b66ed021a0b5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a8e3905dda579f2cd6b30b66ed021a0b5">DSU_CFG_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000002)</td></tr>
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<tr class="memdesc:a8e3905dda579f2cd6b30b66ed021a0b5"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CFG reset_value) Configuration <br /></td></tr>
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<tr class="separator:a8e3905dda579f2cd6b30b66ed021a0b5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6d98254c90559c6b73604015294b6b40"><td class="memItemLeft" align="right" valign="top"><a id="a6d98254c90559c6b73604015294b6b40"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a6d98254c90559c6b73604015294b6b40">DSU_CFG_LQOS_Pos</a>   0</td></tr>
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<tr class="memdesc:a6d98254c90559c6b73604015294b6b40"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CFG) Latency Quality Of Service <br /></td></tr>
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<tr class="separator:a6d98254c90559c6b73604015294b6b40"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae649628f1cd69edafe8ac59755e6042c"><td class="memItemLeft" align="right" valign="top"><a id="ae649628f1cd69edafe8ac59755e6042c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CFG_LQOS_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3) << <a class="el" href="component_2dsu_8h.html#a6d98254c90559c6b73604015294b6b40">DSU_CFG_LQOS_Pos</a>)</td></tr>
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<tr class="separator:ae649628f1cd69edafe8ac59755e6042c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a322d4b1640b4afa78f2085ee2394d127"><td class="memItemLeft" align="right" valign="top"><a id="a322d4b1640b4afa78f2085ee2394d127"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CFG_LQOS</b>(value)   (DSU_CFG_LQOS_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a6d98254c90559c6b73604015294b6b40">DSU_CFG_LQOS_Pos</a>))</td></tr>
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<tr class="separator:a322d4b1640b4afa78f2085ee2394d127"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a589df5c7af4d30c5109d1353eabd48a9"><td class="memItemLeft" align="right" valign="top"><a id="a589df5c7af4d30c5109d1353eabd48a9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a589df5c7af4d30c5109d1353eabd48a9">DSU_CFG_DCCDMALEVEL_Pos</a>   2</td></tr>
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<tr class="memdesc:a589df5c7af4d30c5109d1353eabd48a9"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CFG) DMA Trigger Level <br /></td></tr>
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<tr class="separator:a589df5c7af4d30c5109d1353eabd48a9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a276b9dce0509c5197514d4668ef8fd6a"><td class="memItemLeft" align="right" valign="top"><a id="a276b9dce0509c5197514d4668ef8fd6a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CFG_DCCDMALEVEL_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x3) << <a class="el" href="component_2dsu_8h.html#a589df5c7af4d30c5109d1353eabd48a9">DSU_CFG_DCCDMALEVEL_Pos</a>)</td></tr>
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<tr class="separator:a276b9dce0509c5197514d4668ef8fd6a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3d2e8fb8370375a8b89e0e2489d97a14"><td class="memItemLeft" align="right" valign="top"><a id="a3d2e8fb8370375a8b89e0e2489d97a14"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CFG_DCCDMALEVEL</b>(value)   (DSU_CFG_DCCDMALEVEL_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a589df5c7af4d30c5109d1353eabd48a9">DSU_CFG_DCCDMALEVEL_Pos</a>))</td></tr>
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<tr class="separator:a3d2e8fb8370375a8b89e0e2489d97a14"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a08775cb0aac097f6c9208783fbda68ff"><td class="memItemLeft" align="right" valign="top"><a id="a08775cb0aac097f6c9208783fbda68ff"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a08775cb0aac097f6c9208783fbda68ff">DSU_CFG_DCCDMALEVEL_EMPTY_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0)</td></tr>
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<tr class="memdesc:a08775cb0aac097f6c9208783fbda68ff"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CFG) Trigger rises when DCC is empty <br /></td></tr>
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<tr class="separator:a08775cb0aac097f6c9208783fbda68ff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aad9ff896ba8016cc22e8aebe849ac0e0"><td class="memItemLeft" align="right" valign="top"><a id="aad9ff896ba8016cc22e8aebe849ac0e0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aad9ff896ba8016cc22e8aebe849ac0e0">DSU_CFG_DCCDMALEVEL_FULL_Val</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1)</td></tr>
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<tr class="memdesc:aad9ff896ba8016cc22e8aebe849ac0e0"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CFG) Trigger rises when DCC is full <br /></td></tr>
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<tr class="separator:aad9ff896ba8016cc22e8aebe849ac0e0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afae6221f9a787068aa3683eed995c005"><td class="memItemLeft" align="right" valign="top"><a id="afae6221f9a787068aa3683eed995c005"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CFG_DCCDMALEVEL_EMPTY</b>   (<a class="el" href="component_2dsu_8h.html#a08775cb0aac097f6c9208783fbda68ff">DSU_CFG_DCCDMALEVEL_EMPTY_Val</a> << <a class="el" href="component_2dsu_8h.html#a589df5c7af4d30c5109d1353eabd48a9">DSU_CFG_DCCDMALEVEL_Pos</a>)</td></tr>
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<tr class="separator:afae6221f9a787068aa3683eed995c005"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8626da854d2974e7defcc9625f2e3485"><td class="memItemLeft" align="right" valign="top"><a id="a8626da854d2974e7defcc9625f2e3485"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CFG_DCCDMALEVEL_FULL</b>   (<a class="el" href="component_2dsu_8h.html#aad9ff896ba8016cc22e8aebe849ac0e0">DSU_CFG_DCCDMALEVEL_FULL_Val</a> << <a class="el" href="component_2dsu_8h.html#a589df5c7af4d30c5109d1353eabd48a9">DSU_CFG_DCCDMALEVEL_Pos</a>)</td></tr>
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<tr class="separator:a8626da854d2974e7defcc9625f2e3485"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1dd49a77ed00b0d8b29a092fed417845"><td class="memItemLeft" align="right" valign="top"><a id="a1dd49a77ed00b0d8b29a092fed417845"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a1dd49a77ed00b0d8b29a092fed417845">DSU_CFG_ETBRAMEN_Pos</a>   4</td></tr>
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<tr class="memdesc:a1dd49a77ed00b0d8b29a092fed417845"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CFG) Trace Control <br /></td></tr>
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<tr class="separator:a1dd49a77ed00b0d8b29a092fed417845"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3f32626ab76953494c4cf0d4ca18b2c2"><td class="memItemLeft" align="right" valign="top"><a id="a3f32626ab76953494c4cf0d4ca18b2c2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CFG_ETBRAMEN</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#a1dd49a77ed00b0d8b29a092fed417845">DSU_CFG_ETBRAMEN_Pos</a>)</td></tr>
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<tr class="separator:a3f32626ab76953494c4cf0d4ca18b2c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac4777e024751c158ef31e676ec63eac9"><td class="memItemLeft" align="right" valign="top"><a id="ac4777e024751c158ef31e676ec63eac9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ac4777e024751c158ef31e676ec63eac9">DSU_CFG_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0000001F)</td></tr>
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<tr class="memdesc:ac4777e024751c158ef31e676ec63eac9"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CFG) MASK Register <br /></td></tr>
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<tr class="separator:ac4777e024751c158ef31e676ec63eac9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aab06d4df5675d46495c1506ff2f2bf2c"><td class="memItemLeft" align="right" valign="top"><a id="aab06d4df5675d46495c1506ff2f2bf2c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aab06d4df5675d46495c1506ff2f2bf2c">DSU_ENTRY0_OFFSET</a>   0x1000</td></tr>
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<tr class="memdesc:aab06d4df5675d46495c1506ff2f2bf2c"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ENTRY0 offset) CoreSight ROM Table Entry 0 <br /></td></tr>
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<tr class="separator:aab06d4df5675d46495c1506ff2f2bf2c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8017bdfde4195a88bccf08a7ad26f5ca"><td class="memItemLeft" align="right" valign="top"><a id="a8017bdfde4195a88bccf08a7ad26f5ca"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a8017bdfde4195a88bccf08a7ad26f5ca">DSU_ENTRY0_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x9F0FC002)</td></tr>
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<tr class="memdesc:a8017bdfde4195a88bccf08a7ad26f5ca"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ENTRY0 reset_value) CoreSight ROM Table Entry 0 <br /></td></tr>
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<tr class="separator:a8017bdfde4195a88bccf08a7ad26f5ca"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab0c18ae2688f543939477aebbe76ee54"><td class="memItemLeft" align="right" valign="top"><a id="ab0c18ae2688f543939477aebbe76ee54"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ab0c18ae2688f543939477aebbe76ee54">DSU_ENTRY0_EPRES_Pos</a>   0</td></tr>
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<tr class="memdesc:ab0c18ae2688f543939477aebbe76ee54"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ENTRY0) Entry Present <br /></td></tr>
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<tr class="separator:ab0c18ae2688f543939477aebbe76ee54"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6c401381fced4d940cef9ed1cb0bf71a"><td class="memItemLeft" align="right" valign="top"><a id="a6c401381fced4d940cef9ed1cb0bf71a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_ENTRY0_EPRES</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#ab0c18ae2688f543939477aebbe76ee54">DSU_ENTRY0_EPRES_Pos</a>)</td></tr>
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<tr class="separator:a6c401381fced4d940cef9ed1cb0bf71a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad27fea4487d4ce75afd0b580219487b6"><td class="memItemLeft" align="right" valign="top"><a id="ad27fea4487d4ce75afd0b580219487b6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ad27fea4487d4ce75afd0b580219487b6">DSU_ENTRY0_FMT_Pos</a>   1</td></tr>
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<tr class="memdesc:ad27fea4487d4ce75afd0b580219487b6"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ENTRY0) Format <br /></td></tr>
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<tr class="separator:ad27fea4487d4ce75afd0b580219487b6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af52ac00c014438b8c28c1e5cd3acc389"><td class="memItemLeft" align="right" valign="top"><a id="af52ac00c014438b8c28c1e5cd3acc389"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_ENTRY0_FMT</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#ad27fea4487d4ce75afd0b580219487b6">DSU_ENTRY0_FMT_Pos</a>)</td></tr>
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<tr class="separator:af52ac00c014438b8c28c1e5cd3acc389"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a281853c30a01a33bb71d921008daf56c"><td class="memItemLeft" align="right" valign="top"><a id="a281853c30a01a33bb71d921008daf56c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a281853c30a01a33bb71d921008daf56c">DSU_ENTRY0_ADDOFF_Pos</a>   12</td></tr>
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<tr class="memdesc:a281853c30a01a33bb71d921008daf56c"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ENTRY0) Address Offset <br /></td></tr>
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<tr class="separator:a281853c30a01a33bb71d921008daf56c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acebdea9b5a2589153faa09bdfd152bd2"><td class="memItemLeft" align="right" valign="top"><a id="acebdea9b5a2589153faa09bdfd152bd2"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_ENTRY0_ADDOFF_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFF) << <a class="el" href="component_2dsu_8h.html#a281853c30a01a33bb71d921008daf56c">DSU_ENTRY0_ADDOFF_Pos</a>)</td></tr>
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<tr class="separator:acebdea9b5a2589153faa09bdfd152bd2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8069c18e95c0860b3a09774c20a6ec67"><td class="memItemLeft" align="right" valign="top"><a id="a8069c18e95c0860b3a09774c20a6ec67"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_ENTRY0_ADDOFF</b>(value)   (DSU_ENTRY0_ADDOFF_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a281853c30a01a33bb71d921008daf56c">DSU_ENTRY0_ADDOFF_Pos</a>))</td></tr>
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<tr class="separator:a8069c18e95c0860b3a09774c20a6ec67"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aefdc95e7fcd5bc171ef80131a547588e"><td class="memItemLeft" align="right" valign="top"><a id="aefdc95e7fcd5bc171ef80131a547588e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aefdc95e7fcd5bc171ef80131a547588e">DSU_ENTRY0_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFF003)</td></tr>
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<tr class="memdesc:aefdc95e7fcd5bc171ef80131a547588e"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ENTRY0) MASK Register <br /></td></tr>
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<tr class="separator:aefdc95e7fcd5bc171ef80131a547588e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac5708bb2fe2ee100cdddae6442828217"><td class="memItemLeft" align="right" valign="top"><a id="ac5708bb2fe2ee100cdddae6442828217"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ac5708bb2fe2ee100cdddae6442828217">DSU_ENTRY1_OFFSET</a>   0x1004</td></tr>
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<tr class="memdesc:ac5708bb2fe2ee100cdddae6442828217"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ENTRY1 offset) CoreSight ROM Table Entry 1 <br /></td></tr>
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<tr class="separator:ac5708bb2fe2ee100cdddae6442828217"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9f8fce8b585b23a09dd0abac9fadf06e"><td class="memItemLeft" align="right" valign="top"><a id="a9f8fce8b585b23a09dd0abac9fadf06e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a9f8fce8b585b23a09dd0abac9fadf06e">DSU_ENTRY1_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a9f8fce8b585b23a09dd0abac9fadf06e"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ENTRY1 reset_value) CoreSight ROM Table Entry 1 <br /></td></tr>
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<tr class="separator:a9f8fce8b585b23a09dd0abac9fadf06e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afdfc580b0b4e1677b6ce0b4843199d76"><td class="memItemLeft" align="right" valign="top"><a id="afdfc580b0b4e1677b6ce0b4843199d76"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#afdfc580b0b4e1677b6ce0b4843199d76">DSU_ENTRY1_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFF)</td></tr>
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<tr class="memdesc:afdfc580b0b4e1677b6ce0b4843199d76"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_ENTRY1) MASK Register <br /></td></tr>
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<tr class="separator:afdfc580b0b4e1677b6ce0b4843199d76"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae6ea9aca4f5434a9e01445fc08782f59"><td class="memItemLeft" align="right" valign="top"><a id="ae6ea9aca4f5434a9e01445fc08782f59"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ae6ea9aca4f5434a9e01445fc08782f59">DSU_END_OFFSET</a>   0x1008</td></tr>
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<tr class="memdesc:ae6ea9aca4f5434a9e01445fc08782f59"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_END offset) CoreSight ROM Table End <br /></td></tr>
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<tr class="separator:ae6ea9aca4f5434a9e01445fc08782f59"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa4380f101e160fd70e41789f57871f63"><td class="memItemLeft" align="right" valign="top"><a id="aa4380f101e160fd70e41789f57871f63"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aa4380f101e160fd70e41789f57871f63">DSU_END_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:aa4380f101e160fd70e41789f57871f63"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_END reset_value) CoreSight ROM Table End <br /></td></tr>
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<tr class="separator:aa4380f101e160fd70e41789f57871f63"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a490d2f02762f42681fc4dcaa0db570bb"><td class="memItemLeft" align="right" valign="top"><a id="a490d2f02762f42681fc4dcaa0db570bb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a490d2f02762f42681fc4dcaa0db570bb">DSU_END_END_Pos</a>   0</td></tr>
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<tr class="memdesc:a490d2f02762f42681fc4dcaa0db570bb"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_END) End Marker <br /></td></tr>
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<tr class="separator:a490d2f02762f42681fc4dcaa0db570bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaf87e985a2898109e146e505e1bc603e"><td class="memItemLeft" align="right" valign="top"><a id="aaf87e985a2898109e146e505e1bc603e"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_END_END_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFF) << <a class="el" href="component_2dsu_8h.html#a490d2f02762f42681fc4dcaa0db570bb">DSU_END_END_Pos</a>)</td></tr>
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<tr class="separator:aaf87e985a2898109e146e505e1bc603e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7f75f47734b0964eae647d11b91f7748"><td class="memItemLeft" align="right" valign="top"><a id="a7f75f47734b0964eae647d11b91f7748"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_END_END</b>(value)   (DSU_END_END_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a490d2f02762f42681fc4dcaa0db570bb">DSU_END_END_Pos</a>))</td></tr>
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<tr class="separator:a7f75f47734b0964eae647d11b91f7748"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac1fdb41335952f536cc506c75a0f2e5f"><td class="memItemLeft" align="right" valign="top"><a id="ac1fdb41335952f536cc506c75a0f2e5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ac1fdb41335952f536cc506c75a0f2e5f">DSU_END_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFFFFFFFF)</td></tr>
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<tr class="memdesc:ac1fdb41335952f536cc506c75a0f2e5f"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_END) MASK Register <br /></td></tr>
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<tr class="separator:ac1fdb41335952f536cc506c75a0f2e5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9cfb1a386c96d79aa14d0556e89a9847"><td class="memItemLeft" align="right" valign="top"><a id="a9cfb1a386c96d79aa14d0556e89a9847"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a9cfb1a386c96d79aa14d0556e89a9847">DSU_MEMTYPE_OFFSET</a>   0x1FCC</td></tr>
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<tr class="memdesc:a9cfb1a386c96d79aa14d0556e89a9847"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_MEMTYPE offset) CoreSight ROM Table Memory Type <br /></td></tr>
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<tr class="separator:a9cfb1a386c96d79aa14d0556e89a9847"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae696aac50623781af5c363bb4819a651"><td class="memItemLeft" align="right" valign="top"><a id="ae696aac50623781af5c363bb4819a651"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ae696aac50623781af5c363bb4819a651">DSU_MEMTYPE_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:ae696aac50623781af5c363bb4819a651"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_MEMTYPE reset_value) CoreSight ROM Table Memory Type <br /></td></tr>
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<tr class="separator:ae696aac50623781af5c363bb4819a651"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af9e3cd3a0a5383eb7790554b6b26b2d3"><td class="memItemLeft" align="right" valign="top"><a id="af9e3cd3a0a5383eb7790554b6b26b2d3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#af9e3cd3a0a5383eb7790554b6b26b2d3">DSU_MEMTYPE_SMEMP_Pos</a>   0</td></tr>
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<tr class="memdesc:af9e3cd3a0a5383eb7790554b6b26b2d3"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_MEMTYPE) System Memory Present <br /></td></tr>
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<tr class="separator:af9e3cd3a0a5383eb7790554b6b26b2d3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aab193425e2e460aea861c9c2ef10fd42"><td class="memItemLeft" align="right" valign="top"><a id="aab193425e2e460aea861c9c2ef10fd42"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_MEMTYPE_SMEMP</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#af9e3cd3a0a5383eb7790554b6b26b2d3">DSU_MEMTYPE_SMEMP_Pos</a>)</td></tr>
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<tr class="separator:aab193425e2e460aea861c9c2ef10fd42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1452bd6135db23612661a14aba71c287"><td class="memItemLeft" align="right" valign="top"><a id="a1452bd6135db23612661a14aba71c287"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a1452bd6135db23612661a14aba71c287">DSU_MEMTYPE_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000001)</td></tr>
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<tr class="memdesc:a1452bd6135db23612661a14aba71c287"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_MEMTYPE) MASK Register <br /></td></tr>
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<tr class="separator:a1452bd6135db23612661a14aba71c287"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9b2486d7ffbc473daa210a53c58ae205"><td class="memItemLeft" align="right" valign="top"><a id="a9b2486d7ffbc473daa210a53c58ae205"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a9b2486d7ffbc473daa210a53c58ae205">DSU_PID4_OFFSET</a>   0x1FD0</td></tr>
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<tr class="memdesc:a9b2486d7ffbc473daa210a53c58ae205"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID4 offset) Peripheral Identification 4 <br /></td></tr>
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<tr class="separator:a9b2486d7ffbc473daa210a53c58ae205"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:abff45dc09472f6ef982d193afd7841cc"><td class="memItemLeft" align="right" valign="top"><a id="abff45dc09472f6ef982d193afd7841cc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#abff45dc09472f6ef982d193afd7841cc">DSU_PID4_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:abff45dc09472f6ef982d193afd7841cc"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID4 reset_value) Peripheral Identification 4 <br /></td></tr>
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<tr class="separator:abff45dc09472f6ef982d193afd7841cc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a09592aca2e0907f95a7a1b7898f77734"><td class="memItemLeft" align="right" valign="top"><a id="a09592aca2e0907f95a7a1b7898f77734"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a09592aca2e0907f95a7a1b7898f77734">DSU_PID4_JEPCC_Pos</a>   0</td></tr>
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<tr class="memdesc:a09592aca2e0907f95a7a1b7898f77734"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID4) JEP-106 Continuation Code <br /></td></tr>
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<tr class="separator:a09592aca2e0907f95a7a1b7898f77734"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2a82152e8d4b608bac249b7a20648725"><td class="memItemLeft" align="right" valign="top"><a id="a2a82152e8d4b608bac249b7a20648725"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID4_JEPCC_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2dsu_8h.html#a09592aca2e0907f95a7a1b7898f77734">DSU_PID4_JEPCC_Pos</a>)</td></tr>
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<tr class="separator:a2a82152e8d4b608bac249b7a20648725"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5fd67c05238d1180cab16bd3363d12e3"><td class="memItemLeft" align="right" valign="top"><a id="a5fd67c05238d1180cab16bd3363d12e3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID4_JEPCC</b>(value)   (DSU_PID4_JEPCC_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a09592aca2e0907f95a7a1b7898f77734">DSU_PID4_JEPCC_Pos</a>))</td></tr>
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<tr class="separator:a5fd67c05238d1180cab16bd3363d12e3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa75dd4a5e3f39a78aacfe256a1db4df9"><td class="memItemLeft" align="right" valign="top"><a id="aa75dd4a5e3f39a78aacfe256a1db4df9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aa75dd4a5e3f39a78aacfe256a1db4df9">DSU_PID4_FKBC_Pos</a>   4</td></tr>
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<tr class="memdesc:aa75dd4a5e3f39a78aacfe256a1db4df9"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID4) 4KB count <br /></td></tr>
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<tr class="separator:aa75dd4a5e3f39a78aacfe256a1db4df9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acf7090567b13986ca1ee4903dfbc1157"><td class="memItemLeft" align="right" valign="top"><a id="acf7090567b13986ca1ee4903dfbc1157"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID4_FKBC_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2dsu_8h.html#aa75dd4a5e3f39a78aacfe256a1db4df9">DSU_PID4_FKBC_Pos</a>)</td></tr>
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<tr class="separator:acf7090567b13986ca1ee4903dfbc1157"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac37ce079f68b9fd6e3fc8b02bc876590"><td class="memItemLeft" align="right" valign="top"><a id="ac37ce079f68b9fd6e3fc8b02bc876590"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID4_FKBC</b>(value)   (DSU_PID4_FKBC_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#aa75dd4a5e3f39a78aacfe256a1db4df9">DSU_PID4_FKBC_Pos</a>))</td></tr>
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<tr class="separator:ac37ce079f68b9fd6e3fc8b02bc876590"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4d757ce3a91f809a48fe7fbe9a72724e"><td class="memItemLeft" align="right" valign="top"><a id="a4d757ce3a91f809a48fe7fbe9a72724e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a4d757ce3a91f809a48fe7fbe9a72724e">DSU_PID4_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x000000FF)</td></tr>
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<tr class="memdesc:a4d757ce3a91f809a48fe7fbe9a72724e"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID4) MASK Register <br /></td></tr>
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<tr class="separator:a4d757ce3a91f809a48fe7fbe9a72724e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a55456b82aa4473e1294da9cddff8dc7f"><td class="memItemLeft" align="right" valign="top"><a id="a55456b82aa4473e1294da9cddff8dc7f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a55456b82aa4473e1294da9cddff8dc7f">DSU_PID5_OFFSET</a>   0x1FD4</td></tr>
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<tr class="memdesc:a55456b82aa4473e1294da9cddff8dc7f"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID5 offset) Peripheral Identification 5 <br /></td></tr>
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<tr class="separator:a55456b82aa4473e1294da9cddff8dc7f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a660196a26277134b1faa0e3cb16a45df"><td class="memItemLeft" align="right" valign="top"><a id="a660196a26277134b1faa0e3cb16a45df"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a660196a26277134b1faa0e3cb16a45df">DSU_PID5_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a660196a26277134b1faa0e3cb16a45df"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID5 reset_value) Peripheral Identification 5 <br /></td></tr>
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<tr class="separator:a660196a26277134b1faa0e3cb16a45df"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a5859f5a5ab794ef6639607ee21c9bfb0"><td class="memItemLeft" align="right" valign="top"><a id="a5859f5a5ab794ef6639607ee21c9bfb0"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a5859f5a5ab794ef6639607ee21c9bfb0">DSU_PID5_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a5859f5a5ab794ef6639607ee21c9bfb0"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID5) MASK Register <br /></td></tr>
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<tr class="separator:a5859f5a5ab794ef6639607ee21c9bfb0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aef7906d7c83735893dad365a6292f4c2"><td class="memItemLeft" align="right" valign="top"><a id="aef7906d7c83735893dad365a6292f4c2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aef7906d7c83735893dad365a6292f4c2">DSU_PID6_OFFSET</a>   0x1FD8</td></tr>
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<tr class="memdesc:aef7906d7c83735893dad365a6292f4c2"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID6 offset) Peripheral Identification 6 <br /></td></tr>
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<tr class="separator:aef7906d7c83735893dad365a6292f4c2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0ec56c9b11834ea4e78e4bb56f8d504d"><td class="memItemLeft" align="right" valign="top"><a id="a0ec56c9b11834ea4e78e4bb56f8d504d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a0ec56c9b11834ea4e78e4bb56f8d504d">DSU_PID6_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a0ec56c9b11834ea4e78e4bb56f8d504d"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID6 reset_value) Peripheral Identification 6 <br /></td></tr>
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<tr class="separator:a0ec56c9b11834ea4e78e4bb56f8d504d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac1a214954faa7cfd1597c2f5dc50b61e"><td class="memItemLeft" align="right" valign="top"><a id="ac1a214954faa7cfd1597c2f5dc50b61e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ac1a214954faa7cfd1597c2f5dc50b61e">DSU_PID6_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:ac1a214954faa7cfd1597c2f5dc50b61e"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID6) MASK Register <br /></td></tr>
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<tr class="separator:ac1a214954faa7cfd1597c2f5dc50b61e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a177551481d873cd49c5348a580bb583d"><td class="memItemLeft" align="right" valign="top"><a id="a177551481d873cd49c5348a580bb583d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a177551481d873cd49c5348a580bb583d">DSU_PID7_OFFSET</a>   0x1FDC</td></tr>
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<tr class="memdesc:a177551481d873cd49c5348a580bb583d"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID7 offset) Peripheral Identification 7 <br /></td></tr>
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<tr class="separator:a177551481d873cd49c5348a580bb583d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a425f24c2e936c926f005cec6d504049a"><td class="memItemLeft" align="right" valign="top"><a id="a425f24c2e936c926f005cec6d504049a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a425f24c2e936c926f005cec6d504049a">DSU_PID7_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a425f24c2e936c926f005cec6d504049a"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID7 reset_value) Peripheral Identification 7 <br /></td></tr>
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<tr class="separator:a425f24c2e936c926f005cec6d504049a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a16cbaf00d0e9956cdbf2f3f627576ecc"><td class="memItemLeft" align="right" valign="top"><a id="a16cbaf00d0e9956cdbf2f3f627576ecc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a16cbaf00d0e9956cdbf2f3f627576ecc">DSU_PID7_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:a16cbaf00d0e9956cdbf2f3f627576ecc"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID7) MASK Register <br /></td></tr>
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<tr class="separator:a16cbaf00d0e9956cdbf2f3f627576ecc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aea9d171f0922c1d3459cd94571421b57"><td class="memItemLeft" align="right" valign="top"><a id="aea9d171f0922c1d3459cd94571421b57"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aea9d171f0922c1d3459cd94571421b57">DSU_PID0_OFFSET</a>   0x1FE0</td></tr>
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<tr class="memdesc:aea9d171f0922c1d3459cd94571421b57"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID0 offset) Peripheral Identification 0 <br /></td></tr>
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<tr class="separator:aea9d171f0922c1d3459cd94571421b57"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:afbf547350eaa735fb153d3b6dcc09408"><td class="memItemLeft" align="right" valign="top"><a id="afbf547350eaa735fb153d3b6dcc09408"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#afbf547350eaa735fb153d3b6dcc09408">DSU_PID0_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x000000D0)</td></tr>
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<tr class="memdesc:afbf547350eaa735fb153d3b6dcc09408"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID0 reset_value) Peripheral Identification 0 <br /></td></tr>
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<tr class="separator:afbf547350eaa735fb153d3b6dcc09408"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af2273a145c71eec0de2c40ddd80e4283"><td class="memItemLeft" align="right" valign="top"><a id="af2273a145c71eec0de2c40ddd80e4283"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#af2273a145c71eec0de2c40ddd80e4283">DSU_PID0_PARTNBL_Pos</a>   0</td></tr>
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<tr class="memdesc:af2273a145c71eec0de2c40ddd80e4283"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID0) Part Number Low <br /></td></tr>
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<tr class="separator:af2273a145c71eec0de2c40ddd80e4283"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a54a82c896045decd005d66a532015c5f"><td class="memItemLeft" align="right" valign="top"><a id="a54a82c896045decd005d66a532015c5f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID0_PARTNBL_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFF) << <a class="el" href="component_2dsu_8h.html#af2273a145c71eec0de2c40ddd80e4283">DSU_PID0_PARTNBL_Pos</a>)</td></tr>
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<tr class="separator:a54a82c896045decd005d66a532015c5f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7ae8e82452e6c2e7bafadf3233ca549b"><td class="memItemLeft" align="right" valign="top"><a id="a7ae8e82452e6c2e7bafadf3233ca549b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID0_PARTNBL</b>(value)   (DSU_PID0_PARTNBL_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#af2273a145c71eec0de2c40ddd80e4283">DSU_PID0_PARTNBL_Pos</a>))</td></tr>
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<tr class="separator:a7ae8e82452e6c2e7bafadf3233ca549b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae813809af590e3ba3aa212704b194593"><td class="memItemLeft" align="right" valign="top"><a id="ae813809af590e3ba3aa212704b194593"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ae813809af590e3ba3aa212704b194593">DSU_PID0_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x000000FF)</td></tr>
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<tr class="memdesc:ae813809af590e3ba3aa212704b194593"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID0) MASK Register <br /></td></tr>
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<tr class="separator:ae813809af590e3ba3aa212704b194593"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1114e2adaab2fe61ed027acf899418de"><td class="memItemLeft" align="right" valign="top"><a id="a1114e2adaab2fe61ed027acf899418de"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a1114e2adaab2fe61ed027acf899418de">DSU_PID1_OFFSET</a>   0x1FE4</td></tr>
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<tr class="memdesc:a1114e2adaab2fe61ed027acf899418de"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID1 offset) Peripheral Identification 1 <br /></td></tr>
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<tr class="separator:a1114e2adaab2fe61ed027acf899418de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a257a59dab5e1bef2c233b637968f2786"><td class="memItemLeft" align="right" valign="top"><a id="a257a59dab5e1bef2c233b637968f2786"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a257a59dab5e1bef2c233b637968f2786">DSU_PID1_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x000000FC)</td></tr>
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<tr class="memdesc:a257a59dab5e1bef2c233b637968f2786"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID1 reset_value) Peripheral Identification 1 <br /></td></tr>
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<tr class="separator:a257a59dab5e1bef2c233b637968f2786"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a6dff7e586efe49ba2aa268119a27218d"><td class="memItemLeft" align="right" valign="top"><a id="a6dff7e586efe49ba2aa268119a27218d"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a6dff7e586efe49ba2aa268119a27218d">DSU_PID1_PARTNBH_Pos</a>   0</td></tr>
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<tr class="memdesc:a6dff7e586efe49ba2aa268119a27218d"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID1) Part Number High <br /></td></tr>
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<tr class="separator:a6dff7e586efe49ba2aa268119a27218d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a03bce9efd137e37e8c749cdb2bdfe890"><td class="memItemLeft" align="right" valign="top"><a id="a03bce9efd137e37e8c749cdb2bdfe890"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID1_PARTNBH_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2dsu_8h.html#a6dff7e586efe49ba2aa268119a27218d">DSU_PID1_PARTNBH_Pos</a>)</td></tr>
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<tr class="separator:a03bce9efd137e37e8c749cdb2bdfe890"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a61b0efd1cd16141a3808d1bad644a5aa"><td class="memItemLeft" align="right" valign="top"><a id="a61b0efd1cd16141a3808d1bad644a5aa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID1_PARTNBH</b>(value)   (DSU_PID1_PARTNBH_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a6dff7e586efe49ba2aa268119a27218d">DSU_PID1_PARTNBH_Pos</a>))</td></tr>
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<tr class="separator:a61b0efd1cd16141a3808d1bad644a5aa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a64528557ce517ad0117a1416e03e0be9"><td class="memItemLeft" align="right" valign="top"><a id="a64528557ce517ad0117a1416e03e0be9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a64528557ce517ad0117a1416e03e0be9">DSU_PID1_JEPIDCL_Pos</a>   4</td></tr>
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<tr class="memdesc:a64528557ce517ad0117a1416e03e0be9"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID1) Low part of the JEP-106 Identity Code <br /></td></tr>
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<tr class="separator:a64528557ce517ad0117a1416e03e0be9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af45a07f7bcaedb965d705f1575f1438f"><td class="memItemLeft" align="right" valign="top"><a id="af45a07f7bcaedb965d705f1575f1438f"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID1_JEPIDCL_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2dsu_8h.html#a64528557ce517ad0117a1416e03e0be9">DSU_PID1_JEPIDCL_Pos</a>)</td></tr>
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<tr class="separator:af45a07f7bcaedb965d705f1575f1438f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aea602fc378fd5fb10111e3d8e9022cf3"><td class="memItemLeft" align="right" valign="top"><a id="aea602fc378fd5fb10111e3d8e9022cf3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID1_JEPIDCL</b>(value)   (DSU_PID1_JEPIDCL_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a64528557ce517ad0117a1416e03e0be9">DSU_PID1_JEPIDCL_Pos</a>))</td></tr>
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<tr class="separator:aea602fc378fd5fb10111e3d8e9022cf3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2398899995a62f2a20b4390051c5d269"><td class="memItemLeft" align="right" valign="top"><a id="a2398899995a62f2a20b4390051c5d269"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a2398899995a62f2a20b4390051c5d269">DSU_PID1_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x000000FF)</td></tr>
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<tr class="memdesc:a2398899995a62f2a20b4390051c5d269"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID1) MASK Register <br /></td></tr>
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<tr class="separator:a2398899995a62f2a20b4390051c5d269"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ae848d742529a04e4fc64065f2bfde2d7"><td class="memItemLeft" align="right" valign="top"><a id="ae848d742529a04e4fc64065f2bfde2d7"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ae848d742529a04e4fc64065f2bfde2d7">DSU_PID2_OFFSET</a>   0x1FE8</td></tr>
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<tr class="memdesc:ae848d742529a04e4fc64065f2bfde2d7"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID2 offset) Peripheral Identification 2 <br /></td></tr>
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<tr class="separator:ae848d742529a04e4fc64065f2bfde2d7"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a34f08ebf29928fc5c95f018abbc6d3a3"><td class="memItemLeft" align="right" valign="top"><a id="a34f08ebf29928fc5c95f018abbc6d3a3"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a34f08ebf29928fc5c95f018abbc6d3a3">DSU_PID2_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000009)</td></tr>
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<tr class="memdesc:a34f08ebf29928fc5c95f018abbc6d3a3"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID2 reset_value) Peripheral Identification 2 <br /></td></tr>
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<tr class="separator:a34f08ebf29928fc5c95f018abbc6d3a3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4b2aa922b81ecb07b672d813558306fc"><td class="memItemLeft" align="right" valign="top"><a id="a4b2aa922b81ecb07b672d813558306fc"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a4b2aa922b81ecb07b672d813558306fc">DSU_PID2_JEPIDCH_Pos</a>   0</td></tr>
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<tr class="memdesc:a4b2aa922b81ecb07b672d813558306fc"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID2) JEP-106 Identity Code High <br /></td></tr>
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<tr class="separator:a4b2aa922b81ecb07b672d813558306fc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9aa269300c59a1466dd1e04f8bfbd7a1"><td class="memItemLeft" align="right" valign="top"><a id="a9aa269300c59a1466dd1e04f8bfbd7a1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID2_JEPIDCH_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x7) << <a class="el" href="component_2dsu_8h.html#a4b2aa922b81ecb07b672d813558306fc">DSU_PID2_JEPIDCH_Pos</a>)</td></tr>
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<tr class="separator:a9aa269300c59a1466dd1e04f8bfbd7a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a37fa971dc278d5f39db2207b421c5dc3"><td class="memItemLeft" align="right" valign="top"><a id="a37fa971dc278d5f39db2207b421c5dc3"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID2_JEPIDCH</b>(value)   (DSU_PID2_JEPIDCH_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a4b2aa922b81ecb07b672d813558306fc">DSU_PID2_JEPIDCH_Pos</a>))</td></tr>
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<tr class="separator:a37fa971dc278d5f39db2207b421c5dc3"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a88346fef117d36aa2dba1ffabc5e908a"><td class="memItemLeft" align="right" valign="top"><a id="a88346fef117d36aa2dba1ffabc5e908a"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a88346fef117d36aa2dba1ffabc5e908a">DSU_PID2_JEPU_Pos</a>   3</td></tr>
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<tr class="memdesc:a88346fef117d36aa2dba1ffabc5e908a"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID2) JEP-106 Identity Code is used <br /></td></tr>
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<tr class="separator:a88346fef117d36aa2dba1ffabc5e908a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a967771691bc8307f873ebe12770a9b46"><td class="memItemLeft" align="right" valign="top"><a id="a967771691bc8307f873ebe12770a9b46"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID2_JEPU</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x1) << <a class="el" href="component_2dsu_8h.html#a88346fef117d36aa2dba1ffabc5e908a">DSU_PID2_JEPU_Pos</a>)</td></tr>
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<tr class="separator:a967771691bc8307f873ebe12770a9b46"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acb24de7b25b93dd1c040ed75899fd545"><td class="memItemLeft" align="right" valign="top"><a id="acb24de7b25b93dd1c040ed75899fd545"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#acb24de7b25b93dd1c040ed75899fd545">DSU_PID2_REVISION_Pos</a>   4</td></tr>
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<tr class="memdesc:acb24de7b25b93dd1c040ed75899fd545"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID2) Revision Number <br /></td></tr>
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<tr class="separator:acb24de7b25b93dd1c040ed75899fd545"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a82145131b9b62c23c97969def2900d5d"><td class="memItemLeft" align="right" valign="top"><a id="a82145131b9b62c23c97969def2900d5d"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID2_REVISION_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2dsu_8h.html#acb24de7b25b93dd1c040ed75899fd545">DSU_PID2_REVISION_Pos</a>)</td></tr>
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<tr class="separator:a82145131b9b62c23c97969def2900d5d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a2aded9774af773c83f88843254b3921b"><td class="memItemLeft" align="right" valign="top"><a id="a2aded9774af773c83f88843254b3921b"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID2_REVISION</b>(value)   (DSU_PID2_REVISION_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#acb24de7b25b93dd1c040ed75899fd545">DSU_PID2_REVISION_Pos</a>))</td></tr>
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<tr class="separator:a2aded9774af773c83f88843254b3921b"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4166d965b2c546c98a12d698fd27aa37"><td class="memItemLeft" align="right" valign="top"><a id="a4166d965b2c546c98a12d698fd27aa37"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a4166d965b2c546c98a12d698fd27aa37">DSU_PID2_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x000000FF)</td></tr>
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<tr class="memdesc:a4166d965b2c546c98a12d698fd27aa37"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID2) MASK Register <br /></td></tr>
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<tr class="separator:a4166d965b2c546c98a12d698fd27aa37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0dadf53ca912be72cc37e2eddedbacfa"><td class="memItemLeft" align="right" valign="top"><a id="a0dadf53ca912be72cc37e2eddedbacfa"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a0dadf53ca912be72cc37e2eddedbacfa">DSU_PID3_OFFSET</a>   0x1FEC</td></tr>
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<tr class="memdesc:a0dadf53ca912be72cc37e2eddedbacfa"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID3 offset) Peripheral Identification 3 <br /></td></tr>
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<tr class="separator:a0dadf53ca912be72cc37e2eddedbacfa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aaf4259207024e68a7734aa815f281bb2"><td class="memItemLeft" align="right" valign="top"><a id="aaf4259207024e68a7734aa815f281bb2"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aaf4259207024e68a7734aa815f281bb2">DSU_PID3_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000000)</td></tr>
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<tr class="memdesc:aaf4259207024e68a7734aa815f281bb2"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID3 reset_value) Peripheral Identification 3 <br /></td></tr>
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<tr class="separator:aaf4259207024e68a7734aa815f281bb2"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab4e2a84699bcb677236554a721bbe8f4"><td class="memItemLeft" align="right" valign="top"><a id="ab4e2a84699bcb677236554a721bbe8f4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ab4e2a84699bcb677236554a721bbe8f4">DSU_PID3_CUSMOD_Pos</a>   0</td></tr>
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<tr class="memdesc:ab4e2a84699bcb677236554a721bbe8f4"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID3) ARM CUSMOD <br /></td></tr>
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<tr class="separator:ab4e2a84699bcb677236554a721bbe8f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a42edeb1d05942c2e02601a8e1abebdaa"><td class="memItemLeft" align="right" valign="top"><a id="a42edeb1d05942c2e02601a8e1abebdaa"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID3_CUSMOD_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2dsu_8h.html#ab4e2a84699bcb677236554a721bbe8f4">DSU_PID3_CUSMOD_Pos</a>)</td></tr>
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<tr class="separator:a42edeb1d05942c2e02601a8e1abebdaa"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:affea388f2f5da700b0e9143232f45d37"><td class="memItemLeft" align="right" valign="top"><a id="affea388f2f5da700b0e9143232f45d37"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID3_CUSMOD</b>(value)   (DSU_PID3_CUSMOD_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#ab4e2a84699bcb677236554a721bbe8f4">DSU_PID3_CUSMOD_Pos</a>))</td></tr>
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<tr class="separator:affea388f2f5da700b0e9143232f45d37"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10e1892be1ad4ad3d2eb63267999efb9"><td class="memItemLeft" align="right" valign="top"><a id="a10e1892be1ad4ad3d2eb63267999efb9"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a10e1892be1ad4ad3d2eb63267999efb9">DSU_PID3_REVAND_Pos</a>   4</td></tr>
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<tr class="memdesc:a10e1892be1ad4ad3d2eb63267999efb9"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID3) Revision Number <br /></td></tr>
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<tr class="separator:a10e1892be1ad4ad3d2eb63267999efb9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8aa490a6598622e9f161af9ec209d893"><td class="memItemLeft" align="right" valign="top"><a id="a8aa490a6598622e9f161af9ec209d893"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID3_REVAND_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2dsu_8h.html#a10e1892be1ad4ad3d2eb63267999efb9">DSU_PID3_REVAND_Pos</a>)</td></tr>
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<tr class="separator:a8aa490a6598622e9f161af9ec209d893"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:af2028d73f3440267982dc85909f7eecc"><td class="memItemLeft" align="right" valign="top"><a id="af2028d73f3440267982dc85909f7eecc"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_PID3_REVAND</b>(value)   (DSU_PID3_REVAND_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a10e1892be1ad4ad3d2eb63267999efb9">DSU_PID3_REVAND_Pos</a>))</td></tr>
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<tr class="separator:af2028d73f3440267982dc85909f7eecc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aeaed416954ecb7d99c60af8c7b68b8bb"><td class="memItemLeft" align="right" valign="top"><a id="aeaed416954ecb7d99c60af8c7b68b8bb"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aeaed416954ecb7d99c60af8c7b68b8bb">DSU_PID3_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x000000FF)</td></tr>
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<tr class="memdesc:aeaed416954ecb7d99c60af8c7b68b8bb"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_PID3) MASK Register <br /></td></tr>
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<tr class="separator:aeaed416954ecb7d99c60af8c7b68b8bb"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a04d4b050a6adad9da4caf0993e010d8f"><td class="memItemLeft" align="right" valign="top"><a id="a04d4b050a6adad9da4caf0993e010d8f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a04d4b050a6adad9da4caf0993e010d8f">DSU_CID0_OFFSET</a>   0x1FF0</td></tr>
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<tr class="memdesc:a04d4b050a6adad9da4caf0993e010d8f"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID0 offset) Component Identification 0 <br /></td></tr>
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<tr class="separator:a04d4b050a6adad9da4caf0993e010d8f"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a614c4aa7339cc2b804cd773e20ca7bf5"><td class="memItemLeft" align="right" valign="top"><a id="a614c4aa7339cc2b804cd773e20ca7bf5"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a614c4aa7339cc2b804cd773e20ca7bf5">DSU_CID0_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x0000000D)</td></tr>
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<tr class="memdesc:a614c4aa7339cc2b804cd773e20ca7bf5"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID0 reset_value) Component Identification 0 <br /></td></tr>
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<tr class="separator:a614c4aa7339cc2b804cd773e20ca7bf5"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a684c02c36c7acb7066c55e248c85c44e"><td class="memItemLeft" align="right" valign="top"><a id="a684c02c36c7acb7066c55e248c85c44e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a684c02c36c7acb7066c55e248c85c44e">DSU_CID0_PREAMBLEB0_Pos</a>   0</td></tr>
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<tr class="memdesc:a684c02c36c7acb7066c55e248c85c44e"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID0) Preamble Byte 0 <br /></td></tr>
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<tr class="separator:a684c02c36c7acb7066c55e248c85c44e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:accaacf599c31ea471efbdf7838d26de6"><td class="memItemLeft" align="right" valign="top"><a id="accaacf599c31ea471efbdf7838d26de6"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CID0_PREAMBLEB0_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFF) << <a class="el" href="component_2dsu_8h.html#a684c02c36c7acb7066c55e248c85c44e">DSU_CID0_PREAMBLEB0_Pos</a>)</td></tr>
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<tr class="separator:accaacf599c31ea471efbdf7838d26de6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a38870d39881d4e6cbacc18de7a44529c"><td class="memItemLeft" align="right" valign="top"><a id="a38870d39881d4e6cbacc18de7a44529c"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CID0_PREAMBLEB0</b>(value)   (DSU_CID0_PREAMBLEB0_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a684c02c36c7acb7066c55e248c85c44e">DSU_CID0_PREAMBLEB0_Pos</a>))</td></tr>
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<tr class="separator:a38870d39881d4e6cbacc18de7a44529c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7c41f1841c69429dc59c6466b4fc0742"><td class="memItemLeft" align="right" valign="top"><a id="a7c41f1841c69429dc59c6466b4fc0742"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a7c41f1841c69429dc59c6466b4fc0742">DSU_CID0_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x000000FF)</td></tr>
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<tr class="memdesc:a7c41f1841c69429dc59c6466b4fc0742"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID0) MASK Register <br /></td></tr>
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<tr class="separator:a7c41f1841c69429dc59c6466b4fc0742"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a1000fee5818fa48da89833ca079a3a5c"><td class="memItemLeft" align="right" valign="top"><a id="a1000fee5818fa48da89833ca079a3a5c"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a1000fee5818fa48da89833ca079a3a5c">DSU_CID1_OFFSET</a>   0x1FF4</td></tr>
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<tr class="memdesc:a1000fee5818fa48da89833ca079a3a5c"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID1 offset) Component Identification 1 <br /></td></tr>
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<tr class="separator:a1000fee5818fa48da89833ca079a3a5c"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0ddd2062d17bc1957afe23b2f02a46bd"><td class="memItemLeft" align="right" valign="top"><a id="a0ddd2062d17bc1957afe23b2f02a46bd"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a0ddd2062d17bc1957afe23b2f02a46bd">DSU_CID1_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000010)</td></tr>
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<tr class="memdesc:a0ddd2062d17bc1957afe23b2f02a46bd"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID1 reset_value) Component Identification 1 <br /></td></tr>
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<tr class="separator:a0ddd2062d17bc1957afe23b2f02a46bd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7496e12eabba3a78eaef45bd496a9c89"><td class="memItemLeft" align="right" valign="top"><a id="a7496e12eabba3a78eaef45bd496a9c89"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a7496e12eabba3a78eaef45bd496a9c89">DSU_CID1_PREAMBLE_Pos</a>   0</td></tr>
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<tr class="memdesc:a7496e12eabba3a78eaef45bd496a9c89"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID1) Preamble <br /></td></tr>
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<tr class="separator:a7496e12eabba3a78eaef45bd496a9c89"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a10a983b3963ff405e03427c16369b0be"><td class="memItemLeft" align="right" valign="top"><a id="a10a983b3963ff405e03427c16369b0be"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CID1_PREAMBLE_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2dsu_8h.html#a7496e12eabba3a78eaef45bd496a9c89">DSU_CID1_PREAMBLE_Pos</a>)</td></tr>
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<tr class="separator:a10a983b3963ff405e03427c16369b0be"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac5f44f703f59fd2e482381626a483701"><td class="memItemLeft" align="right" valign="top"><a id="ac5f44f703f59fd2e482381626a483701"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CID1_PREAMBLE</b>(value)   (DSU_CID1_PREAMBLE_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a7496e12eabba3a78eaef45bd496a9c89">DSU_CID1_PREAMBLE_Pos</a>))</td></tr>
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<tr class="separator:ac5f44f703f59fd2e482381626a483701"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa505d5dbcb38fd84adf608eaaa7948a6"><td class="memItemLeft" align="right" valign="top"><a id="aa505d5dbcb38fd84adf608eaaa7948a6"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aa505d5dbcb38fd84adf608eaaa7948a6">DSU_CID1_CCLASS_Pos</a>   4</td></tr>
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<tr class="memdesc:aa505d5dbcb38fd84adf608eaaa7948a6"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID1) Component Class <br /></td></tr>
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<tr class="separator:aa505d5dbcb38fd84adf608eaaa7948a6"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a4266168966ac857f7f418fa53692dc42"><td class="memItemLeft" align="right" valign="top"><a id="a4266168966ac857f7f418fa53692dc42"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CID1_CCLASS_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xF) << <a class="el" href="component_2dsu_8h.html#aa505d5dbcb38fd84adf608eaaa7948a6">DSU_CID1_CCLASS_Pos</a>)</td></tr>
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<tr class="separator:a4266168966ac857f7f418fa53692dc42"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab1b3d33d5908526ca1032a0ac8d792a1"><td class="memItemLeft" align="right" valign="top"><a id="ab1b3d33d5908526ca1032a0ac8d792a1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CID1_CCLASS</b>(value)   (DSU_CID1_CCLASS_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#aa505d5dbcb38fd84adf608eaaa7948a6">DSU_CID1_CCLASS_Pos</a>))</td></tr>
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<tr class="separator:ab1b3d33d5908526ca1032a0ac8d792a1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab3c48e6716c2288f0cbecf4a4991dcff"><td class="memItemLeft" align="right" valign="top"><a id="ab3c48e6716c2288f0cbecf4a4991dcff"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ab3c48e6716c2288f0cbecf4a4991dcff">DSU_CID1_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x000000FF)</td></tr>
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<tr class="memdesc:ab3c48e6716c2288f0cbecf4a4991dcff"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID1) MASK Register <br /></td></tr>
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<tr class="separator:ab3c48e6716c2288f0cbecf4a4991dcff"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ab07b638d6710bb917955217815dcd84e"><td class="memItemLeft" align="right" valign="top"><a id="ab07b638d6710bb917955217815dcd84e"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ab07b638d6710bb917955217815dcd84e">DSU_CID2_OFFSET</a>   0x1FF8</td></tr>
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<tr class="memdesc:ab07b638d6710bb917955217815dcd84e"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID2 offset) Component Identification 2 <br /></td></tr>
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<tr class="separator:ab07b638d6710bb917955217815dcd84e"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a0276c33d43081b5c8cd478b611723f36"><td class="memItemLeft" align="right" valign="top"><a id="a0276c33d43081b5c8cd478b611723f36"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a0276c33d43081b5c8cd478b611723f36">DSU_CID2_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x00000005)</td></tr>
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<tr class="memdesc:a0276c33d43081b5c8cd478b611723f36"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID2 reset_value) Component Identification 2 <br /></td></tr>
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<tr class="separator:a0276c33d43081b5c8cd478b611723f36"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a755afb0dc289f0eeaaf805636836da72"><td class="memItemLeft" align="right" valign="top"><a id="a755afb0dc289f0eeaaf805636836da72"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a755afb0dc289f0eeaaf805636836da72">DSU_CID2_PREAMBLEB2_Pos</a>   0</td></tr>
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<tr class="memdesc:a755afb0dc289f0eeaaf805636836da72"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID2) Preamble Byte 2 <br /></td></tr>
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<tr class="separator:a755afb0dc289f0eeaaf805636836da72"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac588c40c7349a7b9803a8e38bfe9118a"><td class="memItemLeft" align="right" valign="top"><a id="ac588c40c7349a7b9803a8e38bfe9118a"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CID2_PREAMBLEB2_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFF) << <a class="el" href="component_2dsu_8h.html#a755afb0dc289f0eeaaf805636836da72">DSU_CID2_PREAMBLEB2_Pos</a>)</td></tr>
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<tr class="separator:ac588c40c7349a7b9803a8e38bfe9118a"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a826f45b240e84f67a102fd541f6184f1"><td class="memItemLeft" align="right" valign="top"><a id="a826f45b240e84f67a102fd541f6184f1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CID2_PREAMBLEB2</b>(value)   (DSU_CID2_PREAMBLEB2_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#a755afb0dc289f0eeaaf805636836da72">DSU_CID2_PREAMBLEB2_Pos</a>))</td></tr>
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<tr class="separator:a826f45b240e84f67a102fd541f6184f1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aedee750a7bad4de75131402ddea84c91"><td class="memItemLeft" align="right" valign="top"><a id="aedee750a7bad4de75131402ddea84c91"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#aedee750a7bad4de75131402ddea84c91">DSU_CID2_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x000000FF)</td></tr>
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<tr class="memdesc:aedee750a7bad4de75131402ddea84c91"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID2) MASK Register <br /></td></tr>
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<tr class="separator:aedee750a7bad4de75131402ddea84c91"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a9863199733ba4498f102f28fc2c40021"><td class="memItemLeft" align="right" valign="top"><a id="a9863199733ba4498f102f28fc2c40021"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a9863199733ba4498f102f28fc2c40021">DSU_CID3_OFFSET</a>   0x1FFC</td></tr>
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<tr class="memdesc:a9863199733ba4498f102f28fc2c40021"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID3 offset) Component Identification 3 <br /></td></tr>
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<tr class="separator:a9863199733ba4498f102f28fc2c40021"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a8cfe3b4da150c87da70eccd4c07280f4"><td class="memItemLeft" align="right" valign="top"><a id="a8cfe3b4da150c87da70eccd4c07280f4"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a8cfe3b4da150c87da70eccd4c07280f4">DSU_CID3_RESETVALUE</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x000000B1)</td></tr>
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<tr class="memdesc:a8cfe3b4da150c87da70eccd4c07280f4"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID3 reset_value) Component Identification 3 <br /></td></tr>
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<tr class="separator:a8cfe3b4da150c87da70eccd4c07280f4"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad11a14455b5f888c07616d9c56808b09"><td class="memItemLeft" align="right" valign="top"><a id="ad11a14455b5f888c07616d9c56808b09"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#ad11a14455b5f888c07616d9c56808b09">DSU_CID3_PREAMBLEB3_Pos</a>   0</td></tr>
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<tr class="memdesc:ad11a14455b5f888c07616d9c56808b09"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID3) Preamble Byte 3 <br /></td></tr>
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<tr class="separator:ad11a14455b5f888c07616d9c56808b09"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a371986d5abba79b7e4389d750150cad1"><td class="memItemLeft" align="right" valign="top"><a id="a371986d5abba79b7e4389d750150cad1"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CID3_PREAMBLEB3_Msk</b>   (<a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0xFF) << <a class="el" href="component_2dsu_8h.html#ad11a14455b5f888c07616d9c56808b09">DSU_CID3_PREAMBLEB3_Pos</a>)</td></tr>
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<tr class="separator:a371986d5abba79b7e4389d750150cad1"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aa750f726cef165ba74dd6469057fa7d9"><td class="memItemLeft" align="right" valign="top"><a id="aa750f726cef165ba74dd6469057fa7d9"></a>
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#define </td><td class="memItemRight" valign="bottom"><b>DSU_CID3_PREAMBLEB3</b>(value)   (DSU_CID3_PREAMBLEB3_Msk & ((value) << <a class="el" href="component_2dsu_8h.html#ad11a14455b5f888c07616d9c56808b09">DSU_CID3_PREAMBLEB3_Pos</a>))</td></tr>
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<tr class="separator:aa750f726cef165ba74dd6469057fa7d9"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a7b551efb4b690585f91a21e36b24215f"><td class="memItemLeft" align="right" valign="top"><a id="a7b551efb4b690585f91a21e36b24215f"></a>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="component_2dsu_8h.html#a7b551efb4b690585f91a21e36b24215f">DSU_CID3_MASK</a>   <a class="el" href="same54p20a_8h.html#ab21106c87e6a98f4e2833499325b2867">_U_</a>(0x000000FF)</td></tr>
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<tr class="memdesc:a7b551efb4b690585f91a21e36b24215f"><td class="mdescLeft"> </td><td class="mdescRight">(DSU_CID3) MASK Register <br /></td></tr>
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<tr class="separator:a7b551efb4b690585f91a21e36b24215f"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>Component description for DSU. </p>
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<p>Copyright (c) 2019 Microchip Technology Inc.</p>
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<p>\asf_license_start </p>
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<p class="definition">Definition in file <a class="el" href="component_2dsu_8h_source.html">dsu.h</a>.</p>
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