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<title>Blackfin Syntax - Using as</title>
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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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<div class="node">
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<a name="Blackfin-Syntax"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="Blackfin-Directives.html#Blackfin-Directives">Blackfin Directives</a>,
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Previous: <a rel="previous" accesskey="p" href="Blackfin-Options.html#Blackfin-Options">Blackfin Options</a>,
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Up: <a rel="up" accesskey="u" href="Blackfin_002dDependent.html#Blackfin_002dDependent">Blackfin-Dependent</a>
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<hr>
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</div>
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<h4 class="subsection">9.6.2 Syntax</h4>
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<p><a name="index-Blackfin-syntax-813"></a><a name="index-syntax_002c-Blackfin-814"></a>
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<dl>
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<dt><code>Special Characters</code><dd>Assembler input is free format and may appear anywhere on the line.
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One instruction may extend across multiple lines or more than one
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instruction may appear on the same line. White space (space, tab,
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comments or newline) may appear anywhere between tokens. A token must
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not have embedded spaces. Tokens include numbers, register names,
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keywords, user identifiers, and also some multicharacter special
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symbols like "+=", "/*" or "||".
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<p>Comments are introduced by the ‘<samp><span class="samp">#</span></samp>’ character and extend to the
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end of the current line. If the ‘<samp><span class="samp">#</span></samp>’ appears as the first
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character of a line, the whole line is treated as a comment, but in
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this case the line can also be a logical line number directive
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(see <a href="Comments.html#Comments">Comments</a>) or a preprocessor control command
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(see <a href="Preprocessing.html#Preprocessing">Preprocessing</a>).
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<br><dt><code>Instruction Delimiting</code><dd>A semicolon must terminate every instruction. Sometimes a complete
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instruction will consist of more than one operation. There are two
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cases where this occurs. The first is when two general operations
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are combined. Normally a comma separates the different parts, as in
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<pre class="smallexample"> a0= r3.h * r2.l, a1 = r3.l * r2.h ;
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</pre>
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<p>The second case occurs when a general instruction is combined with one
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or two memory references for joint issue. The latter portions are
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set off by a "||" token.
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<pre class="smallexample"> a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];
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</pre>
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<p>Multiple instructions can occur on the same line. Each must be
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terminated by a semicolon character.
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<br><dt><code>Register Names</code><dd>
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The assembler treats register names and instruction keywords in a case
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insensitive manner. User identifiers are case sensitive. Thus, R3.l,
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R3.L, r3.l and r3.L are all equivalent input to the assembler.
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<p>Register names are reserved and may not be used as program identifiers.
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<p>Some operations (such as "Move Register") require a register pair.
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Register pairs are always data registers and are denoted using a colon,
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eg., R3:2. The larger number must be written firsts. Note that the
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hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.
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<p>Some instructions (such as –SP (Push Multiple)) require a group of
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adjacent registers. Adjacent registers are denoted in the syntax by
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the range enclosed in parentheses and separated by a colon, eg., (R7:3).
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Again, the larger number appears first.
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<p>Portions of a particular register may be individually specified. This
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is written with a dot (".") following the register name and then a
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letter denoting the desired portion. For 32-bit registers, ".H"
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denotes the most significant ("High") portion. ".L" denotes the
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least-significant portion. The subdivisions of the 40-bit registers
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are described later.
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<br><dt><code>Accumulators</code><dd>The set of 40-bit registers A1 and A0 that normally contain data that
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is being manipulated. Each accumulator can be accessed in four ways.
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<dl>
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<dt><code>one 40-bit register</code><dd>The register will be referred to as A1 or A0.
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<br><dt><code>one 32-bit register</code><dd>The registers are designated as A1.W or A0.W.
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<br><dt><code>two 16-bit registers</code><dd>The registers are designated as A1.H, A1.L, A0.H or A0.L.
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<br><dt><code>one 8-bit register</code><dd>The registers are designated as A1.X or A0.X for the bits that
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extend beyond bit 31.
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</dl>
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<br><dt><code>Data Registers</code><dd>The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that
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normally contain data for manipulation. These are abbreviated as
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D-register or Dreg. Data registers can be accessed as 32-bit registers
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or as two independent 16-bit registers. The least significant 16 bits
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of each register is called the "low" half and is designated with ".L"
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following the register name. The most significant 16 bits are called
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the "high" half and is designated with ".H" following the name.
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<pre class="smallexample"> R7.L, r2.h, r4.L, R0.H
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</pre>
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<br><dt><code>Pointer Registers</code><dd>The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that
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normally contain byte addresses of data structures. These are
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abbreviated as P-register or Preg.
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<pre class="smallexample"> p2, p5, fp, sp
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</pre>
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<br><dt><code>Stack Pointer SP</code><dd>The stack pointer contains the 32-bit address of the last occupied
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byte location in the stack. The stack grows by decrementing the
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stack pointer.
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<br><dt><code>Frame Pointer FP</code><dd>The frame pointer contains the 32-bit address of the previous frame
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pointer in the stack. It is located at the top of a frame.
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<br><dt><code>Loop Top</code><dd>LT0 and LT1. These registers contain the 32-bit address of the top of
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a zero overhead loop.
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<br><dt><code>Loop Count</code><dd>LC0 and LC1. These registers contain the 32-bit counter of the zero
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overhead loop executions.
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<br><dt><code>Loop Bottom</code><dd>LB0 and LB1. These registers contain the 32-bit address of the bottom
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of a zero overhead loop.
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<br><dt><code>Index Registers</code><dd>The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte
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addresses of data structures. Abbreviated I-register or Ireg.
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<br><dt><code>Modify Registers</code><dd>The set of 32-bit registers (M0, M1, M2, M3) that normally contain
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offset values that are added and subtracted to one of the index
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registers. Abbreviated as Mreg.
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<br><dt><code>Length Registers</code><dd>The set of 32-bit registers (L0, L1, L2, L3) that normally contain the
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length in bytes of the circular buffer. Abbreviated as Lreg. Clear
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the Lreg to disable circular addressing for the corresponding Ireg.
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<br><dt><code>Base Registers</code><dd>The set of 32-bit registers (B0, B1, B2, B3) that normally contain the
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base address in bytes of the circular buffer. Abbreviated as Breg.
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<br><dt><code>Floating Point</code><dd>The Blackfin family has no hardware floating point but the .float
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directive generates ieee floating point numbers for use with software
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floating point libraries.
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<br><dt><code>Blackfin Opcodes</code><dd>For detailed information on the Blackfin machine instruction set, see
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the Blackfin(r) Processor Instruction Set Reference.
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</dl>
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</body></html>
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