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<title>M68HC11-Opts - Using as</title>
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This file documents the GNU Assembler "as".
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<a name="M68HC11-Opts"></a>
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<a name="M68HC11_002dOpts"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="M68HC11_002dSyntax.html#M68HC11_002dSyntax">M68HC11-Syntax</a>,
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Up: <a rel="up" accesskey="u" href="M68HC11_002dDependent.html#M68HC11_002dDependent">M68HC11-Dependent</a>
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<h4 class="subsection">9.24.1 M68HC11 and M68HC12 Options</h4>
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<p><a name="index-options_002c-M68HC11-1391"></a><a name="index-M68HC11-options-1392"></a>The Motorola 68HC11 and 68HC12 version of <code>as</code> have a few machine
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dependent options.
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<a name="index-g_t_0040samp_007b_002dm68hc11_007d-1393"></a>
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<dl><dt><code>-m68hc11</code><dd>This option switches the assembler into the M68HC11 mode. In this mode,
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the assembler only accepts 68HC11 operands and mnemonics. It produces
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code for the 68HC11.
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<p><a name="index-g_t_0040samp_007b_002dm68hc12_007d-1394"></a><br><dt><code>-m68hc12</code><dd>This option switches the assembler into the M68HC12 mode. In this mode,
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the assembler also accepts 68HC12 operands and mnemonics. It produces
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code for the 68HC12. A few 68HC11 instructions are replaced by
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some 68HC12 instructions as recommended by Motorola specifications.
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<p><a name="index-g_t_0040samp_007b_002dm68hcs12_007d-1395"></a><br><dt><code>-m68hcs12</code><dd>This option switches the assembler into the M68HCS12 mode. This mode is
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similar to ‘<samp><span class="samp">-m68hc12</span></samp>’ but specifies to assemble for the 68HCS12
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series. The only difference is on the assembling of the ‘<samp><span class="samp">movb</span></samp>’
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and ‘<samp><span class="samp">movw</span></samp>’ instruction when a PC-relative operand is used.
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<p><a name="index-g_t_0040samp_007b_002dmm9s12x_007d-1396"></a><br><dt><code>-mm9s12x</code><dd>This option switches the assembler into the M9S12X mode. This mode is
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similar to ‘<samp><span class="samp">-m68hc12</span></samp>’ but specifies to assemble for the S12X
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series which is a superset of the HCS12.
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<p><a name="index-g_t_0040samp_007b_002dmm9s12xg_007d-1397"></a><br><dt><code>-mm9s12xg</code><dd>This option switches the assembler into the XGATE mode for the RISC
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co-processor featured on some S12X-family chips.
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<p><a name="index-g_t_0040samp_007b_002d_002dxgate_002dramoffset_007d-1398"></a><br><dt><code>--xgate-ramoffset</code><dd>This option instructs the linker to offset RAM addresses from S12X address
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space into XGATE address space.
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<p><a name="index-g_t_0040samp_007b_002dmshort_007d-1399"></a><br><dt><code>-mshort</code><dd>This option controls the ABI and indicates to use a 16-bit integer ABI.
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It has no effect on the assembled instructions.
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This is the default.
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<p><a name="index-g_t_0040samp_007b_002dmlong_007d-1400"></a><br><dt><code>-mlong</code><dd>This option controls the ABI and indicates to use a 32-bit integer ABI.
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<p><a name="index-g_t_0040samp_007b_002dmshort_002ddouble_007d-1401"></a><br><dt><code>-mshort-double</code><dd>This option controls the ABI and indicates to use a 32-bit float ABI.
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This is the default.
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<p><a name="index-g_t_0040samp_007b_002dmlong_002ddouble_007d-1402"></a><br><dt><code>-mlong-double</code><dd>This option controls the ABI and indicates to use a 64-bit float ABI.
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<p><a name="index-g_t_0040samp_007b_002d_002dstrict_002ddirect_002dmode_007d-1403"></a><br><dt><code>--strict-direct-mode</code><dd>You can use the ‘<samp><span class="samp">--strict-direct-mode</span></samp>’ option to disable
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the automatic translation of direct page mode addressing into
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extended mode when the instruction does not support direct mode.
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For example, the ‘<samp><span class="samp">clr</span></samp>’ instruction does not support direct page
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mode addressing. When it is used with the direct page mode,
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<code>as</code> will ignore it and generate an absolute addressing.
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This option prevents <code>as</code> from doing this, and the wrong
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usage of the direct page mode will raise an error.
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<p><a name="index-g_t_0040samp_007b_002d_002dshort_002dbranches_007d-1404"></a><br><dt><code>--short-branches</code><dd>The ‘<samp><span class="samp">--short-branches</span></samp>’ option turns off the translation of
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relative branches into absolute branches when the branch offset is
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out of range. By default <code>as</code> transforms the relative
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branch (‘<samp><span class="samp">bsr</span></samp>’, ‘<samp><span class="samp">bgt</span></samp>’, ‘<samp><span class="samp">bge</span></samp>’, ‘<samp><span class="samp">beq</span></samp>’, ‘<samp><span class="samp">bne</span></samp>’,
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‘<samp><span class="samp">ble</span></samp>’, ‘<samp><span class="samp">blt</span></samp>’, ‘<samp><span class="samp">bhi</span></samp>’, ‘<samp><span class="samp">bcc</span></samp>’, ‘<samp><span class="samp">bls</span></samp>’,
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‘<samp><span class="samp">bcs</span></samp>’, ‘<samp><span class="samp">bmi</span></samp>’, ‘<samp><span class="samp">bvs</span></samp>’, ‘<samp><span class="samp">bvs</span></samp>’, ‘<samp><span class="samp">bra</span></samp>’) into
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an absolute branch when the offset is out of the -128 .. 127 range.
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In that case, the ‘<samp><span class="samp">bsr</span></samp>’ instruction is translated into a
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‘<samp><span class="samp">jsr</span></samp>’, the ‘<samp><span class="samp">bra</span></samp>’ instruction is translated into a
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‘<samp><span class="samp">jmp</span></samp>’ and the conditional branches instructions are inverted and
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followed by a ‘<samp><span class="samp">jmp</span></samp>’. This option disables these translations
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and <code>as</code> will generate an error if a relative branch
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is out of range. This option does not affect the optimization
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associated to the ‘<samp><span class="samp">jbra</span></samp>’, ‘<samp><span class="samp">jbsr</span></samp>’ and ‘<samp><span class="samp">jbXX</span></samp>’ pseudo opcodes.
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<p><a name="index-g_t_0040samp_007b_002d_002dforce_002dlong_002dbranches_007d-1405"></a><br><dt><code>--force-long-branches</code><dd>The ‘<samp><span class="samp">--force-long-branches</span></samp>’ option forces the translation of
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relative branches into absolute branches. This option does not affect
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the optimization associated to the ‘<samp><span class="samp">jbra</span></samp>’, ‘<samp><span class="samp">jbsr</span></samp>’ and
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‘<samp><span class="samp">jbXX</span></samp>’ pseudo opcodes.
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<p><a name="index-g_t_0040samp_007b_002d_002dprint_002dinsn_002dsyntax_007d-1406"></a><br><dt><code>--print-insn-syntax</code><dd>You can use the ‘<samp><span class="samp">--print-insn-syntax</span></samp>’ option to obtain the
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syntax description of the instruction when an error is detected.
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<p><a name="index-g_t_0040samp_007b_002d_002dprint_002dopcodes_007d-1407"></a><br><dt><code>--print-opcodes</code><dd>The ‘<samp><span class="samp">--print-opcodes</span></samp>’ option prints the list of all the
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instructions with their syntax. The first item of each line
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represents the instruction name and the rest of the line indicates
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the possible operands for that instruction. The list is printed
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in alphabetical order. Once the list is printed <code>as</code>
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exits.
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<p><a name="index-g_t_0040samp_007b_002d_002dgenerate_002dexample_007d-1408"></a><br><dt><code>--generate-example</code><dd>The ‘<samp><span class="samp">--generate-example</span></samp>’ option is similar to ‘<samp><span class="samp">--print-opcodes</span></samp>’
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but it generates an example for each instruction instead.
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</dl>
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</body></html>
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