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296 lines
31 KiB
C
296 lines
31 KiB
C
/**
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* \brief Component description for AES
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2017-08-25T14:00:00Z */
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#ifndef _SAME70_AES_COMPONENT_H_
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#define _SAME70_AES_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR AES */
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/* ************************************************************************** */
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/* -------- AES_CR : (AES Offset: 0x00) ( /W 32) Control Register -------- */
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#define AES_CR_START_Pos _U_(0) /**< (AES_CR) Start Processing Position */
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#define AES_CR_START_Msk (_U_(0x1) << AES_CR_START_Pos) /**< (AES_CR) Start Processing Mask */
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#define AES_CR_START(value) (AES_CR_START_Msk & ((value) << AES_CR_START_Pos))
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#define AES_CR_SWRST_Pos _U_(8) /**< (AES_CR) Software Reset Position */
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#define AES_CR_SWRST_Msk (_U_(0x1) << AES_CR_SWRST_Pos) /**< (AES_CR) Software Reset Mask */
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#define AES_CR_SWRST(value) (AES_CR_SWRST_Msk & ((value) << AES_CR_SWRST_Pos))
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#define AES_CR_Msk _U_(0x00000101) /**< (AES_CR) Register Mask */
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/* -------- AES_MR : (AES Offset: 0x04) (R/W 32) Mode Register -------- */
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#define AES_MR_CIPHER_Pos _U_(0) /**< (AES_MR) Processing Mode Position */
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#define AES_MR_CIPHER_Msk (_U_(0x1) << AES_MR_CIPHER_Pos) /**< (AES_MR) Processing Mode Mask */
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#define AES_MR_CIPHER(value) (AES_MR_CIPHER_Msk & ((value) << AES_MR_CIPHER_Pos))
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#define AES_MR_GTAGEN_Pos _U_(1) /**< (AES_MR) GCM Automatic Tag Generation Enable Position */
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#define AES_MR_GTAGEN_Msk (_U_(0x1) << AES_MR_GTAGEN_Pos) /**< (AES_MR) GCM Automatic Tag Generation Enable Mask */
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#define AES_MR_GTAGEN(value) (AES_MR_GTAGEN_Msk & ((value) << AES_MR_GTAGEN_Pos))
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#define AES_MR_DUALBUFF_Pos _U_(3) /**< (AES_MR) Dual Input Buffer Position */
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#define AES_MR_DUALBUFF_Msk (_U_(0x1) << AES_MR_DUALBUFF_Pos) /**< (AES_MR) Dual Input Buffer Mask */
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#define AES_MR_DUALBUFF(value) (AES_MR_DUALBUFF_Msk & ((value) << AES_MR_DUALBUFF_Pos))
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#define AES_MR_DUALBUFF_INACTIVE_Val _U_(0x0) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. */
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#define AES_MR_DUALBUFF_ACTIVE_Val _U_(0x1) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. */
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#define AES_MR_DUALBUFF_INACTIVE (AES_MR_DUALBUFF_INACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx cannot be written during processing of previous block. Position */
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#define AES_MR_DUALBUFF_ACTIVE (AES_MR_DUALBUFF_ACTIVE_Val << AES_MR_DUALBUFF_Pos) /**< (AES_MR) AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. Position */
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#define AES_MR_PROCDLY_Pos _U_(4) /**< (AES_MR) Processing Delay Position */
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#define AES_MR_PROCDLY_Msk (_U_(0xF) << AES_MR_PROCDLY_Pos) /**< (AES_MR) Processing Delay Mask */
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#define AES_MR_PROCDLY(value) (AES_MR_PROCDLY_Msk & ((value) << AES_MR_PROCDLY_Pos))
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#define AES_MR_SMOD_Pos _U_(8) /**< (AES_MR) Start Mode Position */
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#define AES_MR_SMOD_Msk (_U_(0x3) << AES_MR_SMOD_Pos) /**< (AES_MR) Start Mode Mask */
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#define AES_MR_SMOD(value) (AES_MR_SMOD_Msk & ((value) << AES_MR_SMOD_Pos))
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#define AES_MR_SMOD_MANUAL_START_Val _U_(0x0) /**< (AES_MR) Manual Mode */
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#define AES_MR_SMOD_AUTO_START_Val _U_(0x1) /**< (AES_MR) Auto Mode */
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#define AES_MR_SMOD_IDATAR0_START_Val _U_(0x2) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) */
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#define AES_MR_SMOD_MANUAL_START (AES_MR_SMOD_MANUAL_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Manual Mode Position */
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#define AES_MR_SMOD_AUTO_START (AES_MR_SMOD_AUTO_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) Auto Mode Position */
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#define AES_MR_SMOD_IDATAR0_START (AES_MR_SMOD_IDATAR0_START_Val << AES_MR_SMOD_Pos) /**< (AES_MR) AES_IDATAR0 access only Auto Mode (DMA) Position */
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#define AES_MR_KEYSIZE_Pos _U_(10) /**< (AES_MR) Key Size Position */
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#define AES_MR_KEYSIZE_Msk (_U_(0x3) << AES_MR_KEYSIZE_Pos) /**< (AES_MR) Key Size Mask */
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#define AES_MR_KEYSIZE(value) (AES_MR_KEYSIZE_Msk & ((value) << AES_MR_KEYSIZE_Pos))
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#define AES_MR_KEYSIZE_AES128_Val _U_(0x0) /**< (AES_MR) AES Key Size is 128 bits */
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#define AES_MR_KEYSIZE_AES192_Val _U_(0x1) /**< (AES_MR) AES Key Size is 192 bits */
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#define AES_MR_KEYSIZE_AES256_Val _U_(0x2) /**< (AES_MR) AES Key Size is 256 bits */
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#define AES_MR_KEYSIZE_AES128 (AES_MR_KEYSIZE_AES128_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 128 bits Position */
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#define AES_MR_KEYSIZE_AES192 (AES_MR_KEYSIZE_AES192_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 192 bits Position */
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#define AES_MR_KEYSIZE_AES256 (AES_MR_KEYSIZE_AES256_Val << AES_MR_KEYSIZE_Pos) /**< (AES_MR) AES Key Size is 256 bits Position */
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#define AES_MR_OPMOD_Pos _U_(12) /**< (AES_MR) Operating Mode Position */
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#define AES_MR_OPMOD_Msk (_U_(0x7) << AES_MR_OPMOD_Pos) /**< (AES_MR) Operating Mode Mask */
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#define AES_MR_OPMOD(value) (AES_MR_OPMOD_Msk & ((value) << AES_MR_OPMOD_Pos))
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#define AES_MR_OPMOD_ECB_Val _U_(0x0) /**< (AES_MR) ECB: Electronic Code Book mode */
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#define AES_MR_OPMOD_CBC_Val _U_(0x1) /**< (AES_MR) CBC: Cipher Block Chaining mode */
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#define AES_MR_OPMOD_OFB_Val _U_(0x2) /**< (AES_MR) OFB: Output Feedback mode */
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#define AES_MR_OPMOD_CFB_Val _U_(0x3) /**< (AES_MR) CFB: Cipher Feedback mode */
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#define AES_MR_OPMOD_CTR_Val _U_(0x4) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) */
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#define AES_MR_OPMOD_GCM_Val _U_(0x5) /**< (AES_MR) GCM: Galois/Counter mode */
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#define AES_MR_OPMOD_ECB (AES_MR_OPMOD_ECB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) ECB: Electronic Code Book mode Position */
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#define AES_MR_OPMOD_CBC (AES_MR_OPMOD_CBC_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CBC: Cipher Block Chaining mode Position */
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#define AES_MR_OPMOD_OFB (AES_MR_OPMOD_OFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) OFB: Output Feedback mode Position */
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#define AES_MR_OPMOD_CFB (AES_MR_OPMOD_CFB_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CFB: Cipher Feedback mode Position */
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#define AES_MR_OPMOD_CTR (AES_MR_OPMOD_CTR_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) CTR: Counter mode (16-bit internal counter) Position */
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#define AES_MR_OPMOD_GCM (AES_MR_OPMOD_GCM_Val << AES_MR_OPMOD_Pos) /**< (AES_MR) GCM: Galois/Counter mode Position */
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#define AES_MR_LOD_Pos _U_(15) /**< (AES_MR) Last Output Data Mode Position */
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#define AES_MR_LOD_Msk (_U_(0x1) << AES_MR_LOD_Pos) /**< (AES_MR) Last Output Data Mode Mask */
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#define AES_MR_LOD(value) (AES_MR_LOD_Msk & ((value) << AES_MR_LOD_Pos))
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#define AES_MR_CFBS_Pos _U_(16) /**< (AES_MR) Cipher Feedback Data Size Position */
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#define AES_MR_CFBS_Msk (_U_(0x7) << AES_MR_CFBS_Pos) /**< (AES_MR) Cipher Feedback Data Size Mask */
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#define AES_MR_CFBS(value) (AES_MR_CFBS_Msk & ((value) << AES_MR_CFBS_Pos))
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#define AES_MR_CFBS_SIZE_128BIT_Val _U_(0x0) /**< (AES_MR) 128-bit */
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#define AES_MR_CFBS_SIZE_64BIT_Val _U_(0x1) /**< (AES_MR) 64-bit */
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#define AES_MR_CFBS_SIZE_32BIT_Val _U_(0x2) /**< (AES_MR) 32-bit */
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#define AES_MR_CFBS_SIZE_16BIT_Val _U_(0x3) /**< (AES_MR) 16-bit */
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#define AES_MR_CFBS_SIZE_8BIT_Val _U_(0x4) /**< (AES_MR) 8-bit */
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#define AES_MR_CFBS_SIZE_128BIT (AES_MR_CFBS_SIZE_128BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 128-bit Position */
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#define AES_MR_CFBS_SIZE_64BIT (AES_MR_CFBS_SIZE_64BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 64-bit Position */
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#define AES_MR_CFBS_SIZE_32BIT (AES_MR_CFBS_SIZE_32BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 32-bit Position */
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#define AES_MR_CFBS_SIZE_16BIT (AES_MR_CFBS_SIZE_16BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 16-bit Position */
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#define AES_MR_CFBS_SIZE_8BIT (AES_MR_CFBS_SIZE_8BIT_Val << AES_MR_CFBS_Pos) /**< (AES_MR) 8-bit Position */
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#define AES_MR_CKEY_Pos _U_(20) /**< (AES_MR) Countermeasure Key Position */
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#define AES_MR_CKEY_Msk (_U_(0xF) << AES_MR_CKEY_Pos) /**< (AES_MR) Countermeasure Key Mask */
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#define AES_MR_CKEY(value) (AES_MR_CKEY_Msk & ((value) << AES_MR_CKEY_Pos))
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#define AES_MR_CKEY_PASSWD_Val _U_(0xE) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. */
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#define AES_MR_CKEY_PASSWD (AES_MR_CKEY_PASSWD_Val << AES_MR_CKEY_Pos) /**< (AES_MR) This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. Position */
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#define AES_MR_Msk _U_(0x00F7FFFB) /**< (AES_MR) Register Mask */
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/* -------- AES_IER : (AES Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */
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#define AES_IER_DATRDY_Pos _U_(0) /**< (AES_IER) Data Ready Interrupt Enable Position */
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#define AES_IER_DATRDY_Msk (_U_(0x1) << AES_IER_DATRDY_Pos) /**< (AES_IER) Data Ready Interrupt Enable Mask */
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#define AES_IER_DATRDY(value) (AES_IER_DATRDY_Msk & ((value) << AES_IER_DATRDY_Pos))
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#define AES_IER_URAD_Pos _U_(8) /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Position */
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#define AES_IER_URAD_Msk (_U_(0x1) << AES_IER_URAD_Pos) /**< (AES_IER) Unspecified Register Access Detection Interrupt Enable Mask */
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#define AES_IER_URAD(value) (AES_IER_URAD_Msk & ((value) << AES_IER_URAD_Pos))
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#define AES_IER_TAGRDY_Pos _U_(16) /**< (AES_IER) GCM Tag Ready Interrupt Enable Position */
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#define AES_IER_TAGRDY_Msk (_U_(0x1) << AES_IER_TAGRDY_Pos) /**< (AES_IER) GCM Tag Ready Interrupt Enable Mask */
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#define AES_IER_TAGRDY(value) (AES_IER_TAGRDY_Msk & ((value) << AES_IER_TAGRDY_Pos))
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#define AES_IER_Msk _U_(0x00010101) /**< (AES_IER) Register Mask */
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/* -------- AES_IDR : (AES Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */
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#define AES_IDR_DATRDY_Pos _U_(0) /**< (AES_IDR) Data Ready Interrupt Disable Position */
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#define AES_IDR_DATRDY_Msk (_U_(0x1) << AES_IDR_DATRDY_Pos) /**< (AES_IDR) Data Ready Interrupt Disable Mask */
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#define AES_IDR_DATRDY(value) (AES_IDR_DATRDY_Msk & ((value) << AES_IDR_DATRDY_Pos))
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#define AES_IDR_URAD_Pos _U_(8) /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Position */
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#define AES_IDR_URAD_Msk (_U_(0x1) << AES_IDR_URAD_Pos) /**< (AES_IDR) Unspecified Register Access Detection Interrupt Disable Mask */
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#define AES_IDR_URAD(value) (AES_IDR_URAD_Msk & ((value) << AES_IDR_URAD_Pos))
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#define AES_IDR_TAGRDY_Pos _U_(16) /**< (AES_IDR) GCM Tag Ready Interrupt Disable Position */
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#define AES_IDR_TAGRDY_Msk (_U_(0x1) << AES_IDR_TAGRDY_Pos) /**< (AES_IDR) GCM Tag Ready Interrupt Disable Mask */
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#define AES_IDR_TAGRDY(value) (AES_IDR_TAGRDY_Msk & ((value) << AES_IDR_TAGRDY_Pos))
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#define AES_IDR_Msk _U_(0x00010101) /**< (AES_IDR) Register Mask */
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/* -------- AES_IMR : (AES Offset: 0x18) ( R/ 32) Interrupt Mask Register -------- */
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#define AES_IMR_DATRDY_Pos _U_(0) /**< (AES_IMR) Data Ready Interrupt Mask Position */
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#define AES_IMR_DATRDY_Msk (_U_(0x1) << AES_IMR_DATRDY_Pos) /**< (AES_IMR) Data Ready Interrupt Mask Mask */
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#define AES_IMR_DATRDY(value) (AES_IMR_DATRDY_Msk & ((value) << AES_IMR_DATRDY_Pos))
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#define AES_IMR_URAD_Pos _U_(8) /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Position */
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#define AES_IMR_URAD_Msk (_U_(0x1) << AES_IMR_URAD_Pos) /**< (AES_IMR) Unspecified Register Access Detection Interrupt Mask Mask */
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#define AES_IMR_URAD(value) (AES_IMR_URAD_Msk & ((value) << AES_IMR_URAD_Pos))
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#define AES_IMR_TAGRDY_Pos _U_(16) /**< (AES_IMR) GCM Tag Ready Interrupt Mask Position */
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#define AES_IMR_TAGRDY_Msk (_U_(0x1) << AES_IMR_TAGRDY_Pos) /**< (AES_IMR) GCM Tag Ready Interrupt Mask Mask */
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#define AES_IMR_TAGRDY(value) (AES_IMR_TAGRDY_Msk & ((value) << AES_IMR_TAGRDY_Pos))
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#define AES_IMR_Msk _U_(0x00010101) /**< (AES_IMR) Register Mask */
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/* -------- AES_ISR : (AES Offset: 0x1C) ( R/ 32) Interrupt Status Register -------- */
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#define AES_ISR_DATRDY_Pos _U_(0) /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Position */
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#define AES_ISR_DATRDY_Msk (_U_(0x1) << AES_ISR_DATRDY_Pos) /**< (AES_ISR) Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) Mask */
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#define AES_ISR_DATRDY(value) (AES_ISR_DATRDY_Msk & ((value) << AES_ISR_DATRDY_Pos))
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#define AES_ISR_URAD_Pos _U_(8) /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Position */
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#define AES_ISR_URAD_Msk (_U_(0x1) << AES_ISR_URAD_Pos) /**< (AES_ISR) Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) Mask */
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#define AES_ISR_URAD(value) (AES_ISR_URAD_Msk & ((value) << AES_ISR_URAD_Pos))
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#define AES_ISR_URAT_Pos _U_(12) /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Position */
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#define AES_ISR_URAT_Msk (_U_(0xF) << AES_ISR_URAT_Pos) /**< (AES_ISR) Unspecified Register Access (cleared by writing SWRST in AES_CR) Mask */
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#define AES_ISR_URAT(value) (AES_ISR_URAT_Msk & ((value) << AES_ISR_URAT_Pos))
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#define AES_ISR_URAT_IDR_WR_PROCESSING_Val _U_(0x0) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. */
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#define AES_ISR_URAT_ODR_RD_PROCESSING_Val _U_(0x1) /**< (AES_ISR) Output Data Register read during the data processing. */
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#define AES_ISR_URAT_MR_WR_PROCESSING_Val _U_(0x2) /**< (AES_ISR) Mode Register written during the data processing. */
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#define AES_ISR_URAT_ODR_RD_SUBKGEN_Val _U_(0x3) /**< (AES_ISR) Output Data Register read during the sub-keys generation. */
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#define AES_ISR_URAT_MR_WR_SUBKGEN_Val _U_(0x4) /**< (AES_ISR) Mode Register written during the sub-keys generation. */
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#define AES_ISR_URAT_WOR_RD_ACCESS_Val _U_(0x5) /**< (AES_ISR) Write-only register read access. */
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#define AES_ISR_URAT_IDR_WR_PROCESSING (AES_ISR_URAT_IDR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Input Data Register written during the data processing when SMOD = 0x2 mode. Position */
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#define AES_ISR_URAT_ODR_RD_PROCESSING (AES_ISR_URAT_ODR_RD_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the data processing. Position */
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#define AES_ISR_URAT_MR_WR_PROCESSING (AES_ISR_URAT_MR_WR_PROCESSING_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the data processing. Position */
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#define AES_ISR_URAT_ODR_RD_SUBKGEN (AES_ISR_URAT_ODR_RD_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Output Data Register read during the sub-keys generation. Position */
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#define AES_ISR_URAT_MR_WR_SUBKGEN (AES_ISR_URAT_MR_WR_SUBKGEN_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Mode Register written during the sub-keys generation. Position */
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#define AES_ISR_URAT_WOR_RD_ACCESS (AES_ISR_URAT_WOR_RD_ACCESS_Val << AES_ISR_URAT_Pos) /**< (AES_ISR) Write-only register read access. Position */
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#define AES_ISR_TAGRDY_Pos _U_(16) /**< (AES_ISR) GCM Tag Ready Position */
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#define AES_ISR_TAGRDY_Msk (_U_(0x1) << AES_ISR_TAGRDY_Pos) /**< (AES_ISR) GCM Tag Ready Mask */
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#define AES_ISR_TAGRDY(value) (AES_ISR_TAGRDY_Msk & ((value) << AES_ISR_TAGRDY_Pos))
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#define AES_ISR_Msk _U_(0x0001F101) /**< (AES_ISR) Register Mask */
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/* -------- AES_KEYWR : (AES Offset: 0x20) ( /W 32) Key Word Register 0 -------- */
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#define AES_KEYWR_KEYW_Pos _U_(0) /**< (AES_KEYWR) Key Word Position */
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#define AES_KEYWR_KEYW_Msk (_U_(0xFFFFFFFF) << AES_KEYWR_KEYW_Pos) /**< (AES_KEYWR) Key Word Mask */
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#define AES_KEYWR_KEYW(value) (AES_KEYWR_KEYW_Msk & ((value) << AES_KEYWR_KEYW_Pos))
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#define AES_KEYWR_Msk _U_(0xFFFFFFFF) /**< (AES_KEYWR) Register Mask */
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/* -------- AES_IDATAR : (AES Offset: 0x40) ( /W 32) Input Data Register 0 -------- */
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#define AES_IDATAR_IDATA_Pos _U_(0) /**< (AES_IDATAR) Input Data Word Position */
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#define AES_IDATAR_IDATA_Msk (_U_(0xFFFFFFFF) << AES_IDATAR_IDATA_Pos) /**< (AES_IDATAR) Input Data Word Mask */
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#define AES_IDATAR_IDATA(value) (AES_IDATAR_IDATA_Msk & ((value) << AES_IDATAR_IDATA_Pos))
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#define AES_IDATAR_Msk _U_(0xFFFFFFFF) /**< (AES_IDATAR) Register Mask */
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/* -------- AES_ODATAR : (AES Offset: 0x50) ( R/ 32) Output Data Register 0 -------- */
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#define AES_ODATAR_ODATA_Pos _U_(0) /**< (AES_ODATAR) Output Data Position */
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#define AES_ODATAR_ODATA_Msk (_U_(0xFFFFFFFF) << AES_ODATAR_ODATA_Pos) /**< (AES_ODATAR) Output Data Mask */
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#define AES_ODATAR_ODATA(value) (AES_ODATAR_ODATA_Msk & ((value) << AES_ODATAR_ODATA_Pos))
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#define AES_ODATAR_Msk _U_(0xFFFFFFFF) /**< (AES_ODATAR) Register Mask */
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/* -------- AES_IVR : (AES Offset: 0x60) ( /W 32) Initialization Vector Register 0 -------- */
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#define AES_IVR_IV_Pos _U_(0) /**< (AES_IVR) Initialization Vector Position */
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#define AES_IVR_IV_Msk (_U_(0xFFFFFFFF) << AES_IVR_IV_Pos) /**< (AES_IVR) Initialization Vector Mask */
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#define AES_IVR_IV(value) (AES_IVR_IV_Msk & ((value) << AES_IVR_IV_Pos))
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#define AES_IVR_Msk _U_(0xFFFFFFFF) /**< (AES_IVR) Register Mask */
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/* -------- AES_AADLENR : (AES Offset: 0x70) (R/W 32) Additional Authenticated Data Length Register -------- */
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#define AES_AADLENR_AADLEN_Pos _U_(0) /**< (AES_AADLENR) Additional Authenticated Data Length Position */
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#define AES_AADLENR_AADLEN_Msk (_U_(0xFFFFFFFF) << AES_AADLENR_AADLEN_Pos) /**< (AES_AADLENR) Additional Authenticated Data Length Mask */
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#define AES_AADLENR_AADLEN(value) (AES_AADLENR_AADLEN_Msk & ((value) << AES_AADLENR_AADLEN_Pos))
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#define AES_AADLENR_Msk _U_(0xFFFFFFFF) /**< (AES_AADLENR) Register Mask */
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/* -------- AES_CLENR : (AES Offset: 0x74) (R/W 32) Plaintext/Ciphertext Length Register -------- */
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#define AES_CLENR_CLEN_Pos _U_(0) /**< (AES_CLENR) Plaintext/Ciphertext Length Position */
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#define AES_CLENR_CLEN_Msk (_U_(0xFFFFFFFF) << AES_CLENR_CLEN_Pos) /**< (AES_CLENR) Plaintext/Ciphertext Length Mask */
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#define AES_CLENR_CLEN(value) (AES_CLENR_CLEN_Msk & ((value) << AES_CLENR_CLEN_Pos))
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#define AES_CLENR_Msk _U_(0xFFFFFFFF) /**< (AES_CLENR) Register Mask */
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/* -------- AES_GHASHR : (AES Offset: 0x78) (R/W 32) GCM Intermediate Hash Word Register 0 -------- */
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#define AES_GHASHR_GHASH_Pos _U_(0) /**< (AES_GHASHR) Intermediate GCM Hash Word x Position */
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#define AES_GHASHR_GHASH_Msk (_U_(0xFFFFFFFF) << AES_GHASHR_GHASH_Pos) /**< (AES_GHASHR) Intermediate GCM Hash Word x Mask */
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#define AES_GHASHR_GHASH(value) (AES_GHASHR_GHASH_Msk & ((value) << AES_GHASHR_GHASH_Pos))
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#define AES_GHASHR_Msk _U_(0xFFFFFFFF) /**< (AES_GHASHR) Register Mask */
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/* -------- AES_TAGR : (AES Offset: 0x88) ( R/ 32) GCM Authentication Tag Word Register 0 -------- */
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#define AES_TAGR_TAG_Pos _U_(0) /**< (AES_TAGR) GCM Authentication Tag x Position */
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#define AES_TAGR_TAG_Msk (_U_(0xFFFFFFFF) << AES_TAGR_TAG_Pos) /**< (AES_TAGR) GCM Authentication Tag x Mask */
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#define AES_TAGR_TAG(value) (AES_TAGR_TAG_Msk & ((value) << AES_TAGR_TAG_Pos))
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#define AES_TAGR_Msk _U_(0xFFFFFFFF) /**< (AES_TAGR) Register Mask */
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/* -------- AES_CTRR : (AES Offset: 0x98) ( R/ 32) GCM Encryption Counter Value Register -------- */
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#define AES_CTRR_CTR_Pos _U_(0) /**< (AES_CTRR) GCM Encryption Counter Position */
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#define AES_CTRR_CTR_Msk (_U_(0xFFFFFFFF) << AES_CTRR_CTR_Pos) /**< (AES_CTRR) GCM Encryption Counter Mask */
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#define AES_CTRR_CTR(value) (AES_CTRR_CTR_Msk & ((value) << AES_CTRR_CTR_Pos))
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#define AES_CTRR_Msk _U_(0xFFFFFFFF) /**< (AES_CTRR) Register Mask */
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/* -------- AES_GCMHR : (AES Offset: 0x9C) (R/W 32) GCM H Word Register 0 -------- */
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#define AES_GCMHR_H_Pos _U_(0) /**< (AES_GCMHR) GCM H Word x Position */
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#define AES_GCMHR_H_Msk (_U_(0xFFFFFFFF) << AES_GCMHR_H_Pos) /**< (AES_GCMHR) GCM H Word x Mask */
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#define AES_GCMHR_H(value) (AES_GCMHR_H_Msk & ((value) << AES_GCMHR_H_Pos))
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#define AES_GCMHR_Msk _U_(0xFFFFFFFF) /**< (AES_GCMHR) Register Mask */
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/** \brief AES register offsets definitions */
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#define AES_CR_REG_OFST (0x00) /**< (AES_CR) Control Register Offset */
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#define AES_MR_REG_OFST (0x04) /**< (AES_MR) Mode Register Offset */
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#define AES_IER_REG_OFST (0x10) /**< (AES_IER) Interrupt Enable Register Offset */
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#define AES_IDR_REG_OFST (0x14) /**< (AES_IDR) Interrupt Disable Register Offset */
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#define AES_IMR_REG_OFST (0x18) /**< (AES_IMR) Interrupt Mask Register Offset */
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#define AES_ISR_REG_OFST (0x1C) /**< (AES_ISR) Interrupt Status Register Offset */
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#define AES_KEYWR_REG_OFST (0x20) /**< (AES_KEYWR) Key Word Register 0 Offset */
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#define AES_IDATAR_REG_OFST (0x40) /**< (AES_IDATAR) Input Data Register 0 Offset */
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#define AES_ODATAR_REG_OFST (0x50) /**< (AES_ODATAR) Output Data Register 0 Offset */
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#define AES_IVR_REG_OFST (0x60) /**< (AES_IVR) Initialization Vector Register 0 Offset */
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#define AES_AADLENR_REG_OFST (0x70) /**< (AES_AADLENR) Additional Authenticated Data Length Register Offset */
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#define AES_CLENR_REG_OFST (0x74) /**< (AES_CLENR) Plaintext/Ciphertext Length Register Offset */
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#define AES_GHASHR_REG_OFST (0x78) /**< (AES_GHASHR) GCM Intermediate Hash Word Register 0 Offset */
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#define AES_TAGR_REG_OFST (0x88) /**< (AES_TAGR) GCM Authentication Tag Word Register 0 Offset */
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#define AES_CTRR_REG_OFST (0x98) /**< (AES_CTRR) GCM Encryption Counter Value Register Offset */
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#define AES_GCMHR_REG_OFST (0x9C) /**< (AES_GCMHR) GCM H Word Register 0 Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief AES register API structure */
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typedef struct
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{
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__O uint32_t AES_CR; /**< Offset: 0x00 ( /W 32) Control Register */
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__IO uint32_t AES_MR; /**< Offset: 0x04 (R/W 32) Mode Register */
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__I uint8_t Reserved1[0x08];
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__O uint32_t AES_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */
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__O uint32_t AES_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */
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__I uint32_t AES_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */
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__I uint32_t AES_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */
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__O uint32_t AES_KEYWR[8]; /**< Offset: 0x20 ( /W 32) Key Word Register 0 */
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__O uint32_t AES_IDATAR[4]; /**< Offset: 0x40 ( /W 32) Input Data Register 0 */
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__I uint32_t AES_ODATAR[4]; /**< Offset: 0x50 (R/ 32) Output Data Register 0 */
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__O uint32_t AES_IVR[4]; /**< Offset: 0x60 ( /W 32) Initialization Vector Register 0 */
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__IO uint32_t AES_AADLENR; /**< Offset: 0x70 (R/W 32) Additional Authenticated Data Length Register */
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__IO uint32_t AES_CLENR; /**< Offset: 0x74 (R/W 32) Plaintext/Ciphertext Length Register */
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__IO uint32_t AES_GHASHR[4]; /**< Offset: 0x78 (R/W 32) GCM Intermediate Hash Word Register 0 */
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__I uint32_t AES_TAGR[4]; /**< Offset: 0x88 (R/ 32) GCM Authentication Tag Word Register 0 */
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__I uint32_t AES_CTRR; /**< Offset: 0x98 (R/ 32) GCM Encryption Counter Value Register */
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__IO uint32_t AES_GCMHR[4]; /**< Offset: 0x9C (R/W 32) GCM H Word Register 0 */
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} aes_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME70_AES_COMPONENT_H_ */
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