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<div id="projectname">SAME54P20A Test Project
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<div class="header">
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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Pm Struct Reference</div> </div>
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<div class="contents">
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<p>PM hardware registers.
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<a href="structPm.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="component_2pm_8h_source.html">pm.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:a5e802c548acab3cc3c21b1836d2a1a65"><td class="memItemLeft" align="right" valign="top"><a id="a5e802c548acab3cc3c21b1836d2a1a65"></a>
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__IO <a class="el" href="unionPM__CTRLA__Type.html">PM_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPm.html#a5e802c548acab3cc3c21b1836d2a1a65">CTRLA</a></td></tr>
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<tr class="memdesc:a5e802c548acab3cc3c21b1836d2a1a65"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 8) Control A. <br /></td></tr>
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<tr class="memitem:ae9475eabdc567c4cc2ba8304751d589d"><td class="memItemLeft" align="right" valign="top"><a id="ae9475eabdc567c4cc2ba8304751d589d"></a>
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__IO <a class="el" href="unionPM__SLEEPCFG__Type.html">PM_SLEEPCFG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPm.html#ae9475eabdc567c4cc2ba8304751d589d">SLEEPCFG</a></td></tr>
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<tr class="memdesc:ae9475eabdc567c4cc2ba8304751d589d"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x01 (R/W 8) Sleep Configuration. <br /></td></tr>
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<tr class="separator:ae9475eabdc567c4cc2ba8304751d589d"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ac266f3032e18755059e41c0d4a6618de"><td class="memItemLeft" align="right" valign="top"><a id="ac266f3032e18755059e41c0d4a6618de"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x2]</td></tr>
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<tr class="separator:ac266f3032e18755059e41c0d4a6618de"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:ad0083e323b10f67deea9354e60c691dd"><td class="memItemLeft" align="right" valign="top"><a id="ad0083e323b10f67deea9354e60c691dd"></a>
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__IO <a class="el" href="unionPM__INTENCLR__Type.html">PM_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPm.html#ad0083e323b10f67deea9354e60c691dd">INTENCLR</a></td></tr>
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<tr class="memdesc:ad0083e323b10f67deea9354e60c691dd"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 8) Interrupt Enable Clear. <br /></td></tr>
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<tr class="separator:ad0083e323b10f67deea9354e60c691dd"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:aae11f1dff46c370d8fd6cea5a1ba4bce"><td class="memItemLeft" align="right" valign="top"><a id="aae11f1dff46c370d8fd6cea5a1ba4bce"></a>
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__IO <a class="el" href="unionPM__INTENSET__Type.html">PM_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPm.html#aae11f1dff46c370d8fd6cea5a1ba4bce">INTENSET</a></td></tr>
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<tr class="memdesc:aae11f1dff46c370d8fd6cea5a1ba4bce"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x05 (R/W 8) Interrupt Enable Set. <br /></td></tr>
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<tr class="separator:aae11f1dff46c370d8fd6cea5a1ba4bce"><td class="memSeparator" colspan="2"> </td></tr>
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__IO <a class="el" href="unionPM__INTFLAG__Type.html">PM_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPm.html#a8089472da81397d8469b1426ccb85bc6">INTFLAG</a></td></tr>
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<tr class="memdesc:a8089472da81397d8469b1426ccb85bc6"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x1]</td></tr>
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<tr class="separator:afbf7df063e0a0cd26b1e8fcb3d081c93"><td class="memSeparator" colspan="2"> </td></tr>
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__IO <a class="el" href="unionPM__STDBYCFG__Type.html">PM_STDBYCFG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPm.html#a602e2d24b34da6b0d910f046cfd76289">STDBYCFG</a></td></tr>
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<tr class="memdesc:a602e2d24b34da6b0d910f046cfd76289"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 8) Standby Configuration. <br /></td></tr>
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__IO <a class="el" href="unionPM__HIBCFG__Type.html">PM_HIBCFG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPm.html#a276ad02ba19ab8cb44e81e4f85fa9fd8">HIBCFG</a></td></tr>
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<tr class="memdesc:a276ad02ba19ab8cb44e81e4f85fa9fd8"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x09 (R/W 8) Hibernate Configuration. <br /></td></tr>
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<tr class="separator:a276ad02ba19ab8cb44e81e4f85fa9fd8"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a76e8cf4fc4b74d7a508bd042ecc4fb30"><td class="memItemLeft" align="right" valign="top"><a id="a76e8cf4fc4b74d7a508bd042ecc4fb30"></a>
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__IO <a class="el" href="unionPM__BKUPCFG__Type.html">PM_BKUPCFG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPm.html#a76e8cf4fc4b74d7a508bd042ecc4fb30">BKUPCFG</a></td></tr>
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<tr class="memdesc:a76e8cf4fc4b74d7a508bd042ecc4fb30"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0A (R/W 8) Backup Configuration. <br /></td></tr>
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<tr class="separator:a76e8cf4fc4b74d7a508bd042ecc4fb30"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:acfe62945a13072eff01b4382b186dccc"><td class="memItemLeft" align="right" valign="top"><a id="acfe62945a13072eff01b4382b186dccc"></a>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x7]</td></tr>
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<tr class="separator:acfe62945a13072eff01b4382b186dccc"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memitem:a3e48fb857ca0dc6eb76ce225154df5f0"><td class="memItemLeft" align="right" valign="top"><a id="a3e48fb857ca0dc6eb76ce225154df5f0"></a>
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__IO <a class="el" href="unionPM__PWSAKDLY__Type.html">PM_PWSAKDLY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPm.html#a3e48fb857ca0dc6eb76ce225154df5f0">PWSAKDLY</a></td></tr>
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<tr class="memdesc:a3e48fb857ca0dc6eb76ce225154df5f0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x12 (R/W 8) Power Switch Acknowledge Delay. <br /></td></tr>
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<tr class="separator:a3e48fb857ca0dc6eb76ce225154df5f0"><td class="memSeparator" colspan="2"> </td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>PM hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="component_2pm_8h_source.html#l00243">243</a> of file <a class="el" href="component_2pm_8h_source.html">pm.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2pm_8h_source.html">pm.h</a></li>
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</ul>
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Generated by <a href="http://www.doxygen.org/index.html"><img class="footer" src="doxygen.svg" width="104" height="31" alt="doxygen"/></a> 1.8.20
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