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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">adc0.h</div> </div>
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<div class="contents">
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<a href="adc0_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
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<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_ADC0_INSTANCE_</span></div>
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<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_ADC0_INSTANCE_</span></div>
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<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
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<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for ADC0 peripheral ========== */</span></div>
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<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
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<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_ADC0_CTRLA (0x43001C00) </span></div>
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<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_ADC0_EVCTRL (0x43001C02) </span></div>
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<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_ADC0_DBGCTRL (0x43001C03) </span></div>
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<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_ADC0_INPUTCTRL (0x43001C04) </span></div>
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<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_ADC0_CTRLB (0x43001C06) </span></div>
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<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_ADC0_REFCTRL (0x43001C08) </span></div>
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<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_ADC0_AVGCTRL (0x43001C0A) </span></div>
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<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_ADC0_SAMPCTRL (0x43001C0B) </span></div>
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<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_ADC0_WINLT (0x43001C0C) </span></div>
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<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_ADC0_WINUT (0x43001C0E) </span></div>
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<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_ADC0_GAINCORR (0x43001C10) </span></div>
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<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_ADC0_OFFSETCORR (0x43001C12) </span></div>
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<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_ADC0_SWTRIG (0x43001C14) </span></div>
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<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_ADC0_INTENCLR (0x43001C2C) </span></div>
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<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_ADC0_INTENSET (0x43001C2D) </span></div>
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<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_ADC0_INTFLAG (0x43001C2E) </span></div>
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<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_ADC0_STATUS (0x43001C2F) </span></div>
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<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_ADC0_SYNCBUSY (0x43001C30) </span></div>
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<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_ADC0_DSEQDATA (0x43001C34) </span></div>
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<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_ADC0_DSEQCTRL (0x43001C38) </span></div>
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<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_ADC0_DSEQSTAT (0x43001C3C) </span></div>
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<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_ADC0_RESULT (0x43001C40) </span></div>
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<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define REG_ADC0_RESS (0x43001C44) </span></div>
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<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define REG_ADC0_CALIB (0x43001C48) </span></div>
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<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#else</span></div>
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<div class="line"><a name="l00060"></a><span class="lineno"><a class="line" href="adc0_8h.html#a9c44654964789482627e57ff5071a07e"> 60</a></span> <span class="preprocessor">#define REG_ADC0_CTRLA (*(RwReg16*)0x43001C00UL) </span></div>
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<div class="line"><a name="l00061"></a><span class="lineno"><a class="line" href="adc0_8h.html#a026712b3837538e8277d8154f47169a7"> 61</a></span> <span class="preprocessor">#define REG_ADC0_EVCTRL (*(RwReg8 *)0x43001C02UL) </span></div>
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<div class="line"><a name="l00062"></a><span class="lineno"><a class="line" href="adc0_8h.html#a89bc5e8029ad34ddc5e1f8eca07ffc47"> 62</a></span> <span class="preprocessor">#define REG_ADC0_DBGCTRL (*(RwReg8 *)0x43001C03UL) </span></div>
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<div class="line"><a name="l00063"></a><span class="lineno"><a class="line" href="adc0_8h.html#a1ff6f7b23dbd51f99217830bcca9b664"> 63</a></span> <span class="preprocessor">#define REG_ADC0_INPUTCTRL (*(RwReg16*)0x43001C04UL) </span></div>
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<div class="line"><a name="l00064"></a><span class="lineno"><a class="line" href="adc0_8h.html#afd40546059b3a35d6396fbfd6c8b585f"> 64</a></span> <span class="preprocessor">#define REG_ADC0_CTRLB (*(RwReg16*)0x43001C06UL) </span></div>
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<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="adc0_8h.html#aaf24a8578351101f1763e8abc79ec933"> 65</a></span> <span class="preprocessor">#define REG_ADC0_REFCTRL (*(RwReg8 *)0x43001C08UL) </span></div>
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<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="adc0_8h.html#a8952a2b2bb668406de90b8c4fb1cdd6b"> 66</a></span> <span class="preprocessor">#define REG_ADC0_AVGCTRL (*(RwReg8 *)0x43001C0AUL) </span></div>
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<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="adc0_8h.html#afdcaef912fad2e2b46eeba24d72b4a45"> 67</a></span> <span class="preprocessor">#define REG_ADC0_SAMPCTRL (*(RwReg8 *)0x43001C0BUL) </span></div>
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<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="adc0_8h.html#a026503ed8170e8870378faaa9a114c66"> 68</a></span> <span class="preprocessor">#define REG_ADC0_WINLT (*(RwReg16*)0x43001C0CUL) </span></div>
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<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="adc0_8h.html#a251d70cd9f80815364ea3f827aa99fef"> 69</a></span> <span class="preprocessor">#define REG_ADC0_WINUT (*(RwReg16*)0x43001C0EUL) </span></div>
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<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="adc0_8h.html#ac42157160d191aeea77d9d685abe50fc"> 70</a></span> <span class="preprocessor">#define REG_ADC0_GAINCORR (*(RwReg16*)0x43001C10UL) </span></div>
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<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="adc0_8h.html#a5cdecdc886b77341d36f648e7fb0fe3b"> 71</a></span> <span class="preprocessor">#define REG_ADC0_OFFSETCORR (*(RwReg16*)0x43001C12UL) </span></div>
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<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="adc0_8h.html#a0b0e88a17a2d0503d6194c8500ec7f6c"> 72</a></span> <span class="preprocessor">#define REG_ADC0_SWTRIG (*(RwReg8 *)0x43001C14UL) </span></div>
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<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="adc0_8h.html#a0b79fa5de2a0c2f579a7df8861a1bc01"> 73</a></span> <span class="preprocessor">#define REG_ADC0_INTENCLR (*(RwReg8 *)0x43001C2CUL) </span></div>
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<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="adc0_8h.html#a5c2c445c5b9dbf2b0d3e8143eb858546"> 74</a></span> <span class="preprocessor">#define REG_ADC0_INTENSET (*(RwReg8 *)0x43001C2DUL) </span></div>
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<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="adc0_8h.html#a63608c90cac35807698cd20ef4709a6f"> 75</a></span> <span class="preprocessor">#define REG_ADC0_INTFLAG (*(RwReg8 *)0x43001C2EUL) </span></div>
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<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="adc0_8h.html#a4d4e83d475b9725af6adbcf73a534fef"> 76</a></span> <span class="preprocessor">#define REG_ADC0_STATUS (*(RoReg8 *)0x43001C2FUL) </span></div>
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<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="adc0_8h.html#ae5b477ada134263a79f333977a355445"> 77</a></span> <span class="preprocessor">#define REG_ADC0_SYNCBUSY (*(RoReg *)0x43001C30UL) </span></div>
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<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="adc0_8h.html#af6e1172e49d902e0ceefabf7e0dc73f5"> 78</a></span> <span class="preprocessor">#define REG_ADC0_DSEQDATA (*(WoReg *)0x43001C34UL) </span></div>
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<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="adc0_8h.html#ac3f568691226998d2fe342ead8839cc1"> 79</a></span> <span class="preprocessor">#define REG_ADC0_DSEQCTRL (*(RwReg *)0x43001C38UL) </span></div>
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<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="adc0_8h.html#a821cac42870b3e9378da57aa64293d3c"> 80</a></span> <span class="preprocessor">#define REG_ADC0_DSEQSTAT (*(RoReg *)0x43001C3CUL) </span></div>
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<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="adc0_8h.html#aae29476dcfda186cbf333babd08b7697"> 81</a></span> <span class="preprocessor">#define REG_ADC0_RESULT (*(RoReg16*)0x43001C40UL) </span></div>
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<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="adc0_8h.html#acf6c96f34d09ae75760f59c38967ade9"> 82</a></span> <span class="preprocessor">#define REG_ADC0_RESS (*(RoReg16*)0x43001C44UL) </span></div>
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<div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="adc0_8h.html#afafc7b0a4ce23db4f0cd5911b382b562"> 83</a></span> <span class="preprocessor">#define REG_ADC0_CALIB (*(RwReg16*)0x43001C48UL) </span></div>
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<div class="line"><a name="l00084"></a><span class="lineno"> 84</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
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<div class="line"><a name="l00085"></a><span class="lineno"> 85</span>  </div>
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<div class="line"><a name="l00086"></a><span class="lineno"> 86</span> <span class="comment">/* ========== Instance parameters for ADC0 peripheral ========== */</span></div>
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<div class="line"><a name="l00087"></a><span class="lineno"> 87</span> <span class="preprocessor">#define ADC0_BANDGAP 27 // MUXPOS value to select BANDGAP</span></div>
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<div class="line"><a name="l00088"></a><span class="lineno"> 88</span> <span class="preprocessor">#define ADC0_CTAT 29 // MUXPOS value to select CTAT</span></div>
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<div class="line"><a name="l00089"></a><span class="lineno"> 89</span> <span class="preprocessor">#define ADC0_DMAC_ID_RESRDY 68 // index of DMA RESRDY trigger</span></div>
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<div class="line"><a name="l00090"></a><span class="lineno"> 90</span> <span class="preprocessor">#define ADC0_DMAC_ID_SEQ 69 // Index of DMA SEQ trigger</span></div>
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<div class="line"><a name="l00091"></a><span class="lineno"> 91</span> <span class="preprocessor">#define ADC0_EXTCHANNEL_MSB 15 // Number of external channels</span></div>
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<div class="line"><a name="l00092"></a><span class="lineno"> 92</span> <span class="preprocessor">#define ADC0_GCLK_ID 40 // index of Generic Clock</span></div>
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<div class="line"><a name="l00093"></a><span class="lineno"> 93</span> <span class="preprocessor">#define ADC0_MASTER_SLAVE_MODE 1 // ADC Master/Slave Mode</span></div>
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<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor">#define ADC0_OPAMP2 0 // MUXPOS value to select OPAMP2</span></div>
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<div class="line"><a name="l00095"></a><span class="lineno"> 95</span> <span class="preprocessor">#define ADC0_OPAMP01 0 // MUXPOS value to select OPAMP01</span></div>
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<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="preprocessor">#define ADC0_PTAT 28 // MUXPOS value to select PTAT</span></div>
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<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="preprocessor">#define ADC0_TOUCH_IMPLEMENTED 1 // TOUCH implemented or not</span></div>
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<div class="line"><a name="l00098"></a><span class="lineno"> 98</span>  </div>
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<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_ADC0_INSTANCE_ */</span><span class="preprocessor"></span></div>
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