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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">SercomI2cm Struct Reference</div> </div>
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<p>SERCOM_I2CM hardware registers.
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<a href="structSercomI2cm.html#details">More...</a></p>
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<p><code>#include <<a class="el" href="sercom_8h_source.html">sercom.h</a>></code></p>
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<table class="memberdecls">
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
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Data Fields</h2></td></tr>
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<tr class="memitem:ada5a8e80a8a309062779659a8520a301"><td class="memItemLeft" align="right" valign="top"><a id="ada5a8e80a8a309062779659a8520a301"></a>
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__IO <a class="el" href="unionSERCOM__I2CM__CTRLA__Type.html">SERCOM_I2CM_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomI2cm.html#ada5a8e80a8a309062779659a8520a301">CTRLA</a></td></tr>
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<tr class="memdesc:ada5a8e80a8a309062779659a8520a301"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 32) I2CM Control A. <br /></td></tr>
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<tr class="memdesc:a16405c9197468e6eefef0672b99e7ef9"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 32) I2CM Control B. <br /></td></tr>
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<tr class="memdesc:a90d7e46bb201992eaad6c632325d088b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 32) I2CM Control C. <br /></td></tr>
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__IO <a class="el" href="unionSERCOM__I2CM__BAUD__Type.html">SERCOM_I2CM_BAUD_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomI2cm.html#a49ba881fb2594e4bd81f24d5a6dbf280">BAUD</a></td></tr>
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<tr class="memdesc:a49ba881fb2594e4bd81f24d5a6dbf280"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 32) I2CM Baud Rate. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x4]</td></tr>
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__IO <a class="el" href="unionSERCOM__I2CM__INTENCLR__Type.html">SERCOM_I2CM_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomI2cm.html#a115c20fd68cbae0011a3e013c4fc7f87">INTENCLR</a></td></tr>
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<tr class="memdesc:a115c20fd68cbae0011a3e013c4fc7f87"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 8) I2CM Interrupt Enable Clear. <br /></td></tr>
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<tr class="memdesc:ab9bf32c36650e9e33c4f5457c87e1e67"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x16 (R/W 8) I2CM Interrupt Enable Set. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x1]</td></tr>
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<tr class="memdesc:a08beddd4d34c9cd8e3c54fca1e6d9dc1"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x18 (R/W 8) I2CM Interrupt Flag Status and Clear. <br /></td></tr>
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__IO <a class="el" href="unionSERCOM__I2CM__STATUS__Type.html">SERCOM_I2CM_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomI2cm.html#a7ccd67936d2c8e555c167db38729e43f">STATUS</a></td></tr>
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<tr class="memdesc:a7ccd67936d2c8e555c167db38729e43f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1A (R/W 16) I2CM Status. <br /></td></tr>
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__I <a class="el" href="unionSERCOM__I2CM__SYNCBUSY__Type.html">SERCOM_I2CM_SYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomI2cm.html#ae51a4dd77e7d7790500b65fa4b5d812c">SYNCBUSY</a></td></tr>
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<tr class="memdesc:ae51a4dd77e7d7790500b65fa4b5d812c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/ 32) I2CM Synchronization Busy. <br /></td></tr>
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<tr class="memitem:af72d46dd28fcccf39d6cb6d582b0bf37"><td class="memItemLeft" align="right" valign="top"><a id="af72d46dd28fcccf39d6cb6d582b0bf37"></a>
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__IO <a class="el" href="unionSERCOM__I2CM__ADDR__Type.html">SERCOM_I2CM_ADDR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomI2cm.html#af72d46dd28fcccf39d6cb6d582b0bf37">ADDR</a></td></tr>
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<tr class="memdesc:af72d46dd28fcccf39d6cb6d582b0bf37"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x24 (R/W 32) I2CM Address. <br /></td></tr>
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<tr class="memitem:afc1d1938d5847da43327d75f7eb5d928"><td class="memItemLeft" align="right" valign="top"><a id="afc1d1938d5847da43327d75f7eb5d928"></a>
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__IO <a class="el" href="unionSERCOM__I2CM__DATA__Type.html">SERCOM_I2CM_DATA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomI2cm.html#afc1d1938d5847da43327d75f7eb5d928">DATA</a></td></tr>
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<tr class="memdesc:afc1d1938d5847da43327d75f7eb5d928"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x28 (R/W 32) I2CM Data. <br /></td></tr>
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<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved6</b> [0x4]</td></tr>
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<tr class="memitem:ac12abbbde36c7ba5cc2e24548a3c3b69"><td class="memItemLeft" align="right" valign="top"><a id="ac12abbbde36c7ba5cc2e24548a3c3b69"></a>
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__IO <a class="el" href="unionSERCOM__I2CM__DBGCTRL__Type.html">SERCOM_I2CM_DBGCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structSercomI2cm.html#ac12abbbde36c7ba5cc2e24548a3c3b69">DBGCTRL</a></td></tr>
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<tr class="memdesc:ac12abbbde36c7ba5cc2e24548a3c3b69"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x30 (R/W 8) I2CM Debug Control. <br /></td></tr>
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</table>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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<div class="textblock"><p>SERCOM_I2CM hardware registers. </p>
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<p class="definition">Definition at line <a class="el" href="sercom_8h_source.html#l01573">1573</a> of file <a class="el" href="sercom_8h_source.html">sercom.h</a>.</p>
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</div><hr/>The documentation for this struct was generated from the following file:<ul>
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<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="sercom_8h_source.html">sercom.h</a></li>
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