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<!--
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This file documents the GNU Assembler "as".
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Copyright (C) 1991-2015 Free Software Foundation, Inc.
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Permission is granted to copy, distribute and/or modify this document
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<a name="i386-Memory"></a>
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<a name="i386_002dMemory"></a>
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<p>
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Next: <a rel="next" accesskey="n" href="i386_002dJumps.html#i386_002dJumps">i386-Jumps</a>,
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Previous: <a rel="previous" accesskey="p" href="i386_002dPrefixes.html#i386_002dPrefixes">i386-Prefixes</a>,
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<h4 class="subsection">9.15.7 Memory References</h4>
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<p><a name="index-i386-memory-references-1107"></a><a name="index-memory-references_002c-i386-1108"></a><a name="index-x86_002d64-memory-references-1109"></a><a name="index-memory-references_002c-x86_002d64-1110"></a>An Intel syntax indirect memory reference of the form
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<pre class="smallexample"> <var>section</var>:[<var>base</var> + <var>index</var>*<var>scale</var> + <var>disp</var>]
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</pre>
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<p class="noindent">is translated into the AT&T syntax
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<pre class="smallexample"> <var>section</var>:<var>disp</var>(<var>base</var>, <var>index</var>, <var>scale</var>)
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</pre>
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<p class="noindent">where <var>base</var> and <var>index</var> are the optional 32-bit base and
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index registers, <var>disp</var> is the optional displacement, and
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<var>scale</var>, taking the values 1, 2, 4, and 8, multiplies <var>index</var>
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to calculate the address of the operand. If no <var>scale</var> is
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specified, <var>scale</var> is taken to be 1. <var>section</var> specifies the
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optional section register for the memory operand, and may override the
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default section register (see a 80386 manual for section register
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defaults). Note that section overrides in AT&T syntax <em>must</em>
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be preceded by a ‘<samp><span class="samp">%</span></samp>’. If you specify a section override which
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coincides with the default section register, <code>as</code> does <em>not</em>
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output any section register override prefixes to assemble the given
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instruction. Thus, section overrides can be specified to emphasize which
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section register is used for a given memory operand.
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<p>Here are some examples of Intel and AT&T style memory references:
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<dl>
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<dt>AT&T: ‘<samp><span class="samp">-4(%ebp)</span></samp>’, Intel: ‘<samp><span class="samp">[ebp - 4]</span></samp>’<dd><var>base</var> is ‘<samp><span class="samp">%ebp</span></samp>’; <var>disp</var> is ‘<samp><span class="samp">-4</span></samp>’. <var>section</var> is
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missing, and the default section is used (‘<samp><span class="samp">%ss</span></samp>’ for addressing with
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‘<samp><span class="samp">%ebp</span></samp>’ as the base register). <var>index</var>, <var>scale</var> are both missing.
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<br><dt>AT&T: ‘<samp><span class="samp">foo(,%eax,4)</span></samp>’, Intel: ‘<samp><span class="samp">[foo + eax*4]</span></samp>’<dd><var>index</var> is ‘<samp><span class="samp">%eax</span></samp>’ (scaled by a <var>scale</var> 4); <var>disp</var> is
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‘<samp><span class="samp">foo</span></samp>’. All other fields are missing. The section register here
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defaults to ‘<samp><span class="samp">%ds</span></samp>’.
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<br><dt>AT&T: ‘<samp><span class="samp">foo(,1)</span></samp>’; Intel ‘<samp><span class="samp">[foo]</span></samp>’<dd>This uses the value pointed to by ‘<samp><span class="samp">foo</span></samp>’ as a memory operand.
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Note that <var>base</var> and <var>index</var> are both missing, but there is only
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<em>one</em> ‘<samp><span class="samp">,</span></samp>’. This is a syntactic exception.
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<br><dt>AT&T: ‘<samp><span class="samp">%gs:foo</span></samp>’; Intel ‘<samp><span class="samp">gs:foo</span></samp>’<dd>This selects the contents of the variable ‘<samp><span class="samp">foo</span></samp>’ with section
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register <var>section</var> being ‘<samp><span class="samp">%gs</span></samp>’.
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</dl>
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<p>Absolute (as opposed to PC relative) call and jump operands must be
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prefixed with ‘<samp><span class="samp">*</span></samp>’. If no ‘<samp><span class="samp">*</span></samp>’ is specified, <code>as</code>
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always chooses PC relative addressing for jump/call labels.
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<p>Any instruction that has a memory operand, but no register operand,
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<em>must</em> specify its size (byte, word, long, or quadruple) with an
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instruction mnemonic suffix (‘<samp><span class="samp">b</span></samp>’, ‘<samp><span class="samp">w</span></samp>’, ‘<samp><span class="samp">l</span></samp>’ or ‘<samp><span class="samp">q</span></samp>’,
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respectively).
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<p>The x86-64 architecture adds an RIP (instruction pointer relative)
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addressing. This addressing mode is specified by using ‘<samp><span class="samp">rip</span></samp>’ as a
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base register. Only constant offsets are valid. For example:
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<dl>
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<dt>AT&T: ‘<samp><span class="samp">1234(%rip)</span></samp>’, Intel: ‘<samp><span class="samp">[rip + 1234]</span></samp>’<dd>Points to the address 1234 bytes past the end of the current
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instruction.
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<br><dt>AT&T: ‘<samp><span class="samp">symbol(%rip)</span></samp>’, Intel: ‘<samp><span class="samp">[rip + symbol]</span></samp>’<dd>Points to the <code>symbol</code> in RIP relative way, this is shorter than
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the default absolute addressing.
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</dl>
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<p>Other addressing modes remain unchanged in x86-64 architecture, except
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registers used are 64-bit instead of 32-bit.
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