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402 lines
15 KiB
C
402 lines
15 KiB
C
#include "clocks.h"
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#include "conf_core.h"
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void clock_osc32k_init(void)
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{
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#if CORE_CONF_CLK_XOSC32K_ENABLE == 1
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OSC32KCTRL->XOSC32K.bit.CGM = CORE_CONF_CLK_XOSC32K_CGM;
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OSC32KCTRL->XOSC32K.bit.WRTLOCK = CORE_CONF_CLK_XOSC32K_WRTLOCK;
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OSC32KCTRL->XOSC32K.bit.STARTUP = CORE_CONF_CLK_XOSC32K_STARTUP_TIME;
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OSC32KCTRL->XOSC32K.bit.RUNSTDBY = CORE_CONF_CLK_XOSC32K_RUNSTDBY;
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OSC32KCTRL->XOSC32K.bit.ONDEMAND = CORE_CONF_CLK_XOSC32K_ONDEMAND;
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OSC32KCTRL->XOSC32K.bit.EN1K = CORE_CONF_CLK_XOSC32K_EN1K;
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OSC32KCTRL->XOSC32K.bit.EN32K = CORE_CONF_CLK_XOSC32K_EN32K;
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OSC32KCTRL->XOSC32K.bit.XTALEN = CORE_CONF_CLK_XOSC32K_XTALEN;
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OSC32KCTRL->CFDCTRL.bit.CFDPRESC = CORE_CONF_CLK_XOSC32K_CFDPRESC;
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OSC32KCTRL->CFDCTRL.bit.SWBACK = CORE_CONF_CLK_XOSC32K_SWBACK;
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OSC32KCTRL->CFDCTRL.bit.CFDEN = CORE_CONF_CLK_XOSC32K_CFDEN;
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#if CORE_CONF_CLK_XOSC32K_ENABLE == 1 && CORE_CONF_CLK_XOSC32K_ONDEMAND == 0
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while(OSC32KCTRL->STATUS.bit.XOSC32KRDY == 0);
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#endif
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#endif
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}
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void clock_osc_init(void)
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{
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#if CORE_CONF_CLK_XOSC0_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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OSCCTRL->XOSCCTRL[0].bit.XTALEN = CORE_CONF_CLK_XOSC0_XTALEN;
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OSCCTRL->XOSCCTRL[0].bit.RUNSTDBY = CORE_CONF_CLK_XOSC0_RUNSTDBY;
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OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = CORE_CONF_CLK_XOSC0_ONDEMAND;
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OSCCTRL->XOSCCTRL[0].bit.LOWBUFGAIN = CORE_CONF_CLK_XOSC0_LOWBUFGAIN;
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OSCCTRL->XOSCCTRL[0].bit.IPTAT = CORE_CONF_CLK_XOSC0_IPTAT;
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OSCCTRL->XOSCCTRL[0].bit.IMULT = CORE_CONF_CLK_XOSC0_IMULT;
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OSCCTRL->XOSCCTRL[0].bit.ENALC = CORE_CONF_CLK_XOSC0_ENALC;
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OSCCTRL->XOSCCTRL[0].bit.CFDEN = CORE_CONF_CLK_XOSC0_CFDEN;
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OSCCTRL->XOSCCTRL[0].bit.CFDPRESC = CORE_CONF_CLK_XOSC0_CFDPRESC;
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OSCCTRL->XOSCCTRL[0].bit.SWBEN = CORE_CONF_CLK_XOSC0_SWBEN;
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OSCCTRL->XOSCCTRL[0].bit.STARTUP = CORE_CONF_CLK_XOSC0_STARTUP_TIME;
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OSCCTRL->XOSCCTRL[0].bit.ENABLE = CORE_CONF_CLK_XOSC0_ENABLE;
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CRITICAL_SECTION_LEAVE();
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while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
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#endif
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#if CORE_CONF_CLK_XOSC1_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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OSCCTRL->XOSCCTRL[1].bit.XTALEN = CORE_CONF_CLK_XOSC1_XTALEN;
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OSCCTRL->XOSCCTRL[1].bit.RUNSTDBY = CORE_CONF_CLK_XOSC1_RUNSTDBY;
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OSCCTRL->XOSCCTRL[1].bit.LOWBUFGAIN = CORE_CONF_CLK_XOSC1_LOWBUFGAIN;
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OSCCTRL->XOSCCTRL[1].bit.IPTAT = CORE_CONF_CLK_XOSC1_IPTAT;
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OSCCTRL->XOSCCTRL[1].bit.IMULT = CORE_CONF_CLK_XOSC1_IMULT;
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OSCCTRL->XOSCCTRL[1].bit.CFDEN = CORE_CONF_CLK_XOSC1_CFDEN;
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OSCCTRL->XOSCCTRL[1].bit.CFDPRESC = CORE_CONF_CLK_XOSC1_CFDPRESC;
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OSCCTRL->XOSCCTRL[1].bit.SWBEN = CORE_CONF_CLK_XOSC1_SWBEN;
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OSCCTRL->XOSCCTRL[1].bit.STARTUP = CORE_CONF_CLK_XOSC1_STARTUP_TIME;
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OSCCTRL->XOSCCTRL[1].bit.ENABLE = CORE_CONF_CLK_XOSC1_ENABLE;
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CRITICAL_SECTION_LEAVE();
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while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
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#endif
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#if CORE_CONF_CLK_XOSC0_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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#if CORE_CONF_CLK_XOSC0_ENALC == 1
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OSCCTRL->XOSCCTRL[0].bit.ENALC = CORE_CONF_CLK_XOSC0_ENALC;
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#endif
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#if CORE_CONF_CLK_XOSC0_ONDEMAND == 1
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OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = CORE_CONF_CLK_XOSC0_ONDEMAND;
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#endif
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_CLK_XOSC1_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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#if CORE_CONF_CLK_XOSC1_ENALC == 1
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OSCCTRL->XOSCCTRL[1].bit.ENALC = CORE_CONF_CLK_XOSC1_ENALC;
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#endif
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#if CORE_CONF_CLK_XOSC1_ONDEMAND == 1
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OSCCTRL->XOSCCTRL[1].bit.ONDEMAND = CORE_CONF_CLK_XOSC1_ONDEMAND;
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#endif
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CRITICAL_SECTION_LEAVE();
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#endif
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}
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void clock_mclk_init(void)
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{
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CRITICAL_SECTION_ENTER();
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MCLK->CPUDIV.reg = CORE_CONF_MCLK_CPUDIV;
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CRITICAL_SECTION_LEAVE();
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}
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void clock_gclk_init(void)
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{
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#if CORE_CONF_GCLK_0_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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GCLK->GENCTRL[0].bit.DIV = CORE_CONF_GCLK_0_DIV_VAL;
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GCLK->GENCTRL[0].bit.DIVSEL = CORE_CONF_GCLK_0_DIVSEL;
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GCLK->GENCTRL[0].bit.RUNSTDBY = CORE_CONF_GCLK_0_RUN_IN_STANDBY;
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GCLK->GENCTRL[0].bit.OE = CORE_CONF_GCLK_0_OUTPUT_ENABLE;
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GCLK->GENCTRL[0].bit.OOV = CORE_CONF_GCLK_0_DIVSEL;
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GCLK->GENCTRL[0].bit.IDC = CORE_CONF_GCLK_0_IDC;
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GCLK->GENCTRL[0].bit.GENEN = CORE_CONF_GCLK_0_ENABLE;
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GCLK->GENCTRL[0].bit.SRC = CORE_CONF_GCLK_0_CLOCK_SOURCE;
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_GCLK_1_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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GCLK->GENCTRL[1].bit.DIV = CORE_CONF_GCLK_1_DIV_VAL;
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GCLK->GENCTRL[1].bit.DIVSEL = CORE_CONF_GCLK_1_DIVSEL;
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GCLK->GENCTRL[1].bit.RUNSTDBY = CORE_CONF_GCLK_1_RUN_IN_STANDBY;
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GCLK->GENCTRL[1].bit.OE = CORE_CONF_GCLK_1_OUTPUT_ENABLE;
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GCLK->GENCTRL[1].bit.OOV = CORE_CONF_GCLK_1_DIVSEL;
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GCLK->GENCTRL[1].bit.IDC = CORE_CONF_GCLK_1_IDC;
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GCLK->GENCTRL[1].bit.GENEN = CORE_CONF_GCLK_1_ENABLE;
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GCLK->GENCTRL[1].bit.SRC = CORE_CONF_GCLK_1_CLOCK_SOURCE;
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_GCLK_2_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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GCLK->GENCTRL[2].bit.DIV = CORE_CONF_GCLK_2_DIV_VAL;
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GCLK->GENCTRL[2].bit.DIVSEL = CORE_CONF_GCLK_2_DIVSEL;
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GCLK->GENCTRL[2].bit.RUNSTDBY = CORE_CONF_GCLK_2_RUN_IN_STANDBY;
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GCLK->GENCTRL[2].bit.OE = CORE_CONF_GCLK_2_OUTPUT_ENABLE;
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GCLK->GENCTRL[2].bit.OOV = CORE_CONF_GCLK_2_DIVSEL;
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GCLK->GENCTRL[2].bit.IDC = CORE_CONF_GCLK_2_IDC;
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GCLK->GENCTRL[2].bit.GENEN = CORE_CONF_GCLK_2_ENABLE;
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GCLK->GENCTRL[2].bit.SRC = CORE_CONF_GCLK_2_CLOCK_SOURCE;
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_GCLK_3_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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GCLK->GENCTRL[3].bit.DIV = CORE_CONF_GCLK_3_DIV_VAL;
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GCLK->GENCTRL[3].bit.DIVSEL = CORE_CONF_GCLK_3_DIVSEL;
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GCLK->GENCTRL[3].bit.RUNSTDBY = CORE_CONF_GCLK_3_RUN_IN_STANDBY;
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GCLK->GENCTRL[3].bit.OE = CORE_CONF_GCLK_3_OUTPUT_ENABLE;
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GCLK->GENCTRL[3].bit.OOV = CORE_CONF_GCLK_3_DIVSEL;
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GCLK->GENCTRL[3].bit.IDC = CORE_CONF_GCLK_3_IDC;
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GCLK->GENCTRL[3].bit.GENEN = CORE_CONF_GCLK_3_ENABLE;
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GCLK->GENCTRL[3].bit.SRC = CORE_CONF_GCLK_3_CLOCK_SOURCE;
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_GCLK_4_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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GCLK->GENCTRL[4].bit.DIV = CORE_CONF_GCLK_4_DIV_VAL;
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GCLK->GENCTRL[4].bit.DIVSEL = CORE_CONF_GCLK_4_DIVSEL;
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GCLK->GENCTRL[4].bit.RUNSTDBY = CORE_CONF_GCLK_4_RUN_IN_STANDBY;
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GCLK->GENCTRL[4].bit.OE = CORE_CONF_GCLK_4_OUTPUT_ENABLE;
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GCLK->GENCTRL[4].bit.OOV = CORE_CONF_GCLK_4_DIVSEL;
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GCLK->GENCTRL[4].bit.IDC = CORE_CONF_GCLK_4_IDC;
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GCLK->GENCTRL[4].bit.GENEN = CORE_CONF_GCLK_4_ENABLE;
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GCLK->GENCTRL[4].bit.SRC = CORE_CONF_GCLK_4_CLOCK_SOURCE;
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_GCLK_5_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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GCLK->GENCTRL[5].bit.DIV = CORE_CONF_GCLK_5_DIV_VAL;
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GCLK->GENCTRL[5].bit.DIVSEL = CORE_CONF_GCLK_5_DIVSEL;
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GCLK->GENCTRL[5].bit.RUNSTDBY = CORE_CONF_GCLK_5_RUN_IN_STANDBY;
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GCLK->GENCTRL[5].bit.OE = CORE_CONF_GCLK_5_OUTPUT_ENABLE;
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GCLK->GENCTRL[5].bit.OOV = CORE_CONF_GCLK_5_DIVSEL;
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GCLK->GENCTRL[5].bit.IDC = CORE_CONF_GCLK_5_IDC;
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GCLK->GENCTRL[5].bit.GENEN = CORE_CONF_GCLK_5_ENABLE;
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GCLK->GENCTRL[5].bit.SRC = CORE_CONF_GCLK_5_CLOCK_SOURCE;
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_GCLK_6_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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GCLK->GENCTRL[6].bit.DIV = CORE_CONF_GCLK_6_DIV_VAL;
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GCLK->GENCTRL[6].bit.DIVSEL = CORE_CONF_GCLK_6_DIVSEL;
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GCLK->GENCTRL[6].bit.RUNSTDBY = CORE_CONF_GCLK_6_RUN_IN_STANDBY;
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GCLK->GENCTRL[6].bit.OE = CORE_CONF_GCLK_6_OUTPUT_ENABLE;
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GCLK->GENCTRL[6].bit.OOV = CORE_CONF_GCLK_6_DIVSEL;
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GCLK->GENCTRL[6].bit.IDC = CORE_CONF_GCLK_6_IDC;
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GCLK->GENCTRL[6].bit.GENEN = CORE_CONF_GCLK_6_ENABLE;
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GCLK->GENCTRL[6].bit.SRC = CORE_CONF_GCLK_6_CLOCK_SOURCE;
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_GCLK_7_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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GCLK->GENCTRL[7].bit.DIV = CORE_CONF_GCLK_7_DIV_VAL;
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GCLK->GENCTRL[7].bit.DIVSEL = CORE_CONF_GCLK_7_DIVSEL;
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GCLK->GENCTRL[7].bit.RUNSTDBY = CORE_CONF_GCLK_7_RUN_IN_STANDBY;
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GCLK->GENCTRL[7].bit.OE = CORE_CONF_GCLK_7_OUTPUT_ENABLE;
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GCLK->GENCTRL[7].bit.OOV = CORE_CONF_GCLK_7_DIVSEL;
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GCLK->GENCTRL[7].bit.IDC = CORE_CONF_GCLK_7_IDC;
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GCLK->GENCTRL[7].bit.GENEN = CORE_CONF_GCLK_7_ENABLE;
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GCLK->GENCTRL[7].bit.SRC = CORE_CONF_GCLK_7_CLOCK_SOURCE;
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_GCLK_8_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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GCLK->GENCTRL[8].bit.DIV = CORE_CONF_GCLK_8_DIV_VAL;
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GCLK->GENCTRL[8].bit.DIVSEL = CORE_CONF_GCLK_8_DIVSEL;
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GCLK->GENCTRL[8].bit.RUNSTDBY = CORE_CONF_GCLK_8_RUN_IN_STANDBY;
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GCLK->GENCTRL[8].bit.OE = CORE_CONF_GCLK_8_OUTPUT_ENABLE;
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GCLK->GENCTRL[8].bit.OOV = CORE_CONF_GCLK_8_DIVSEL;
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GCLK->GENCTRL[8].bit.IDC = CORE_CONF_GCLK_8_IDC;
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GCLK->GENCTRL[8].bit.GENEN = CORE_CONF_GCLK_8_ENABLE;
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GCLK->GENCTRL[8].bit.SRC = CORE_CONF_GCLK_8_CLOCK_SOURCE;
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_GCLK_9_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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GCLK->GENCTRL[9].bit.DIV = CORE_CONF_GCLK_9_DIV_VAL;
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GCLK->GENCTRL[9].bit.DIVSEL = CORE_CONF_GCLK_9_DIVSEL;
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GCLK->GENCTRL[9].bit.RUNSTDBY = CORE_CONF_GCLK_9_RUN_IN_STANDBY;
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GCLK->GENCTRL[9].bit.OE = CORE_CONF_GCLK_9_OUTPUT_ENABLE;
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GCLK->GENCTRL[9].bit.OOV = CORE_CONF_GCLK_9_DIVSEL;
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GCLK->GENCTRL[9].bit.IDC = CORE_CONF_GCLK_9_IDC;
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GCLK->GENCTRL[9].bit.GENEN = CORE_CONF_GCLK_9_ENABLE;
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GCLK->GENCTRL[9].bit.SRC = CORE_CONF_GCLK_9_CLOCK_SOURCE;
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_GCLK_10_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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GCLK->GENCTRL[10].bit.DIV = CORE_CONF_GCLK_10_DIV_VAL;
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GCLK->GENCTRL[10].bit.DIVSEL = CORE_CONF_GCLK_10_DIVSEL;
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GCLK->GENCTRL[10].bit.RUNSTDBY = CORE_CONF_GCLK_10_RUN_IN_STANDBY;
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GCLK->GENCTRL[10].bit.OE = CORE_CONF_GCLK_10_OUTPUT_ENABLE;
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GCLK->GENCTRL[10].bit.OOV = CORE_CONF_GCLK_10_DIVSEL;
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GCLK->GENCTRL[10].bit.IDC = CORE_CONF_GCLK_10_IDC;
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GCLK->GENCTRL[10].bit.GENEN = CORE_CONF_GCLK_10_ENABLE;
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GCLK->GENCTRL[10].bit.SRC = CORE_CONF_GCLK_10_CLOCK_SOURCE;
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_GCLK_11_ENABLE == 1
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CRITICAL_SECTION_ENTER();
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GCLK->GENCTRL[11].bit.DIV = CORE_CONF_GCLK_11_DIV_VAL;
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GCLK->GENCTRL[11].bit.DIVSEL = CORE_CONF_GCLK_11_DIVSEL;
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GCLK->GENCTRL[11].bit.RUNSTDBY = CORE_CONF_GCLK_11_RUN_IN_STANDBY;
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GCLK->GENCTRL[11].bit.OE = CORE_CONF_GCLK_11_OUTPUT_ENABLE;
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GCLK->GENCTRL[11].bit.OOV = CORE_CONF_GCLK_11_DIVSEL;
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GCLK->GENCTRL[11].bit.IDC = CORE_CONF_GCLK_11_IDC;
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GCLK->GENCTRL[11].bit.GENEN = CORE_CONF_GCLK_11_ENABLE;
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GCLK->GENCTRL[11].bit.SRC = CORE_CONF_GCLK_11_CLOCK_SOURCE;
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CRITICAL_SECTION_LEAVE();
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#endif
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}
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void clock_dpll_init(void)
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{
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#if CORE_CONF_CLK_DPLL0_ENABLE == 1
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#if CORE_CONF_CLK_DPLL0_REFCLK == 0
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CRITICAL_SECTION_ENTER();
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GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].bit.GEN =
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GCLK_PCHCTRL_GEN(CORE_CONF_CLK_DPLL0_GCLK_SRC);
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GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].bit.CHEN =
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CORE_CONF_CLK_DPLL0_ENABLE;
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CRITICAL_SECTION_LEAVE();
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#endif
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CRITICAL_SECTION_ENTER();
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// write dpll ratio
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OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = CORE_CONF_CLK_DPLL0_LDRFRAC_VAL;
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OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = CORE_CONF_CLK_DPLL0_LDR_VAL;
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// write dpll ctrlb
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OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = CORE_CONF_CLK_DPLL0_DIV_VAL;
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OSCCTRL->Dpll[0].DPLLCTRLB.bit.DCOEN = CORE_CONF_CLK_DPLL0_DCOEN;
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OSCCTRL->Dpll[0].DPLLCTRLB.bit.DCOFILTER = CORE_CONF_CLK_DPLL0_DCOFILTER;
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OSCCTRL->Dpll[0].DPLLCTRLB.bit.LBYPASS = CORE_CONF_CLK_DPLL0_LBYPASS;
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OSCCTRL->Dpll[0].DPLLCTRLB.bit.LTIME = CORE_CONF_CLK_DPLL0_LTIME;
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OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = CORE_CONF_CLK_DPLL0_REFCLK;
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OSCCTRL->Dpll[0].DPLLCTRLB.bit.WUF = CORE_CONF_CLK_DPLL0_WUF;
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OSCCTRL->Dpll[0].DPLLCTRLB.bit.FILTER = CORE_CONF_CLK_DPLL0_FILTER;
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OSCCTRL->Dpll[0].DPLLCTRLA.bit.RUNSTDBY = CORE_CONF_CLK_DPLL0_RUNSTDBY;
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OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = CORE_CONF_CLK_DPLL0_ENABLE;
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CRITICAL_SECTION_LEAVE();
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#endif
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#if CORE_CONF_CLK_DPLL1_ENABLE == 1
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#if CORE_CONF_CLK_DPLL0_REFCLK == 0
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CRITICAL_SECTION_ENTER();
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GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].bit.GEN =
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GCLK_PCHCTRL_GEN(CORE_CONF_CLK_DPLL1_GCLK_SRC);
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GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].bit.CHEN =
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CORE_CONF_CLK_DPLL1_ENABLE;
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CRITICAL_SECTION_LEAVE();
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#endif
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CRITICAL_SECTION_ENTER();
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// write dpll ratio
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OSCCTRL->Dpll[1].DPLLRATIO.bit.LDRFRAC = CORE_CONF_CLK_DPLL1_LDRFRAC_VAL;
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OSCCTRL->Dpll[1].DPLLRATIO.bit.LDR = CORE_CONF_CLK_DPLL1_LDR_VAL;
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// write dpll ctrlb
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OSCCTRL->Dpll[1].DPLLCTRLB.bit.DIV = CORE_CONF_CLK_DPLL1_DIV_VAL;
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OSCCTRL->Dpll[1].DPLLCTRLB.bit.DCOEN = CORE_CONF_CLK_DPLL1_DCOEN;
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OSCCTRL->Dpll[1].DPLLCTRLB.bit.DCOFILTER = CORE_CONF_CLK_DPLL1_DCOFILTER;
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OSCCTRL->Dpll[1].DPLLCTRLB.bit.LBYPASS = CORE_CONF_CLK_DPLL1_LBYPASS;
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OSCCTRL->Dpll[1].DPLLCTRLB.bit.LTIME = CORE_CONF_CLK_DPLL1_LTIME;
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OSCCTRL->Dpll[1].DPLLCTRLB.bit.REFCLK = CORE_CONF_CLK_DPLL1_REFCLK;
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OSCCTRL->Dpll[1].DPLLCTRLB.bit.WUF = CORE_CONF_CLK_DPLL1_WUF;
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OSCCTRL->Dpll[1].DPLLCTRLB.bit.FILTER = CORE_CONF_CLK_DPLL1_FILTER;
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OSCCTRL->Dpll[1].DPLLCTRLA.bit.RUNSTDBY = CORE_CONF_CLK_DPLL1_RUNSTDBY;
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OSCCTRL->Dpll[1].DPLLCTRLA.bit.ENABLE = CORE_CONF_CLK_DPLL1_ENABLE;
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CRITICAL_SECTION_LEAVE();
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#endif
|
|
|
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#if CORE_CONF_CLK_DPLL0_ENABLE == 1
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while(!(OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK || OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY));
|
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CRITICAL_SECTION_ENTER();
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|
#if CORE_CONF_CLK_DPLL0_ONDEMAND == 1
|
|
OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = CORE_CONF_CLK_DPLL0_ONDEMAND;
|
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#endif
|
|
CRITICAL_SECTION_LEAVE();
|
|
#endif
|
|
|
|
#if CORE_CONF_CLK_DPLL1_ENABLE == 1
|
|
while(!(OSCCTRL->Dpll[1].DPLLSTATUS.bit.LOCK || OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY));
|
|
CRITICAL_SECTION_ENTER();
|
|
#if CORE_CONF_CLK_DPLL1_ONDEMAND == 1
|
|
OSCCTRL->Dpll[1].DPLLCTRLA.bit.ONDEMAND = CORE_CONF_CLK_DPLL1_ONDEMAND;
|
|
#endif
|
|
CRITICAL_SECTION_LEAVE();
|
|
#endif
|
|
}
|
|
|
|
void clock_dfll_init(void)
|
|
{
|
|
#if CORE_CONF_CLK_DFLL_ENABLE
|
|
CRITICAL_SECTION_ENTER();
|
|
GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_OSCULP32K;
|
|
CRITICAL_SECTION_LEAVE();
|
|
while(GCLK->SYNCBUSY.bit.GENCTRL0);
|
|
|
|
CRITICAL_SECTION_ENTER();
|
|
// reset stuff
|
|
OSCCTRL->DFLLCTRLA.reg = 0;
|
|
CRITICAL_SECTION_LEAVE();
|
|
#if CORE_CONF_CLK_DFLL_USBCRM != 1 && CORE_CONF_CLK_DFLL_MODE != 0
|
|
CRITICAL_SECTION_ENTER();
|
|
// reset stuff
|
|
GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].bit.GEN =
|
|
GCLK_PCHCTRL_GEN(CORE_CONF_CLK_DFLL_GCLK_SRC);
|
|
GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].bit.EN = CORE_CONF_CLK_DFLL_ENABLE;
|
|
CRITICAL_SECTION_LEAVE();
|
|
#endif
|
|
|
|
CRITICAL_SECTION_ENTER();
|
|
// configure clock multiplier stuff
|
|
OSCCTRL->DFLLMUL.bit.MUL = CORE_CONF_CLK_DFLL_MUL_VAL;
|
|
OSCCTRL->DFLLMUL.bit.CSTEP = CORE_CONF_CLK_DFLL_CSTEP_VAL;
|
|
OSCCTRL->DFLLMUL.bit.FSTEP = CORE_CONF_CLK_DFLL_FSTEP_VAL;
|
|
CRITICAL_SECTION_LEAVE();
|
|
while(OSCCTRL->DFLLSYNC.bit.DFLLMUL);
|
|
|
|
CRITICAL_SECTION_ENTER();
|
|
// reset dfll ctrlb
|
|
OSCCTRL->DFLLCTRLB.reg = 0;
|
|
CRITICAL_SECTION_LEAVE();
|
|
// wait for ctrlb sync
|
|
while(OSCCTRL->DFLLSYNC.bit.DFLLCTRLB);
|
|
|
|
#if CORE_CONF_CLK_DFLL_OVERWRITE_CAL == 1
|
|
CRITICAL_SECTION_ENTER();
|
|
// set calib for dfll48m
|
|
OSCCTRL->DFLLVAL.bit.COARSE = CORE_CONF_CLK_DFLL_COARSE_VAL;
|
|
OSCCTRL->DFLLVAL.bit.FINE = CORE_CONF_CLK_DFLL_FINE_VAL;
|
|
OSCCTRL->DFLLVAL.bit.DIFF = CORE_CONF_CLK_DFLL_DIFF_VAL;
|
|
CRITICAL_SECTION_LEAVE();
|
|
#endif
|
|
|
|
CRITICAL_SECTION_ENTER();
|
|
// write dfll val
|
|
// rewriting this for some reason?
|
|
OSCCTRL->DFLLVAL.reg = OSCCTRL->DFLLVAL.reg;
|
|
CRITICAL_SECTION_LEAVE();
|
|
// let dfll val sync
|
|
while(OSCCTRL->DFLLSYNC.bit.DFLLVAL);
|
|
|
|
CRITICAL_SECTION_ENTER();
|
|
// write dfll ctrlb
|
|
OSCCTRL->DFLLCTRLB.bit.WAITLOCK = CORE_CONF_CLK_DFLL_WAITLOCK;
|
|
OSCCTRL->DFLLCTRLB.bit.QLDIS = CORE_CONF_CLK_DFLL_QLDIS;
|
|
OSCCTRL->DFLLCTRLB.bit.USBCRM = CORE_CONF_CLK_DFLL_USBCRM;
|
|
OSCCTRL->DFLLCTRLB.bit.STABLE = CORE_CONF_CLK_DFLL_STABLE_FCALIB;
|
|
CRITICAL_SECTION_LEAVE();
|
|
|
|
if (OSCCTRL->DFLLCTRLB.bit.MODE)
|
|
{
|
|
while(OSCCTRL->STATUS.reg != (OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC));
|
|
}
|
|
else
|
|
{
|
|
while(!OSCCTRL->STATUS.bit.DFLLRDY);
|
|
}
|
|
|
|
#if CORE_CONF_CLK_DFLL_ONDEMAND == 1
|
|
CRITICAL_SECTION_ENTER();
|
|
OSCCTRL->DFLLCTRLA.bit.ONDEMAND = CORE_CONF_CLK_DFLL_ONDEMAND;
|
|
CRITICAL_SECTION_LEAVE();
|
|
#endif
|
|
|
|
while(GCLK->SYNCBUSY.reg);
|
|
CRITICAL_SECTION_ENTER();
|
|
// reset gclk 0
|
|
GCLK->GENCTRL[0].bit.SRC = CORE_CONF_GCLK_0_CLOCK_SOURCE;
|
|
CRITICAL_SECTION_LEAVE();
|
|
#endif
|
|
}
|