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<a name="Simple-Constraints"></a>
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Next: <a rel="next" accesskey="n" href="Multi_002dAlternative.html#Multi_002dAlternative">Multi-Alternative</a>,
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<h5 class="subsubsection">6.43.3.1 Simple Constraints</h5>
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<p><a name="index-simple-constraints-3436"></a>
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The simplest kind of constraint is a string full of letters, each of
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which describes one kind of operand that is permitted. Here are
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the letters that are allowed:
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<dl>
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<dt>whitespace<dd>Whitespace characters are ignored and can be inserted at any position
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except the first. This enables each alternative for different operands to
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be visually aligned in the machine description even if they have different
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number of constraints and modifiers.
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<p><a name="index-g_t_0040samp_007bm_007d-in-constraint-3437"></a><a name="index-memory-references-in-constraints-3438"></a><br><dt>‘<samp><span class="samp">m</span></samp>’<dd>A memory operand is allowed, with any kind of address that the machine
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supports in general.
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Note that the letter used for the general memory constraint can be
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re-defined by a back end using the <code>TARGET_MEM_CONSTRAINT</code> macro.
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<p><a name="index-offsettable-address-3439"></a><a name="index-g_t_0040samp_007bo_007d-in-constraint-3440"></a><br><dt>‘<samp><span class="samp">o</span></samp>’<dd>A memory operand is allowed, but only if the address is
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<dfn>offsettable</dfn>. This means that adding a small integer (actually,
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the width in bytes of the operand, as determined by its machine mode)
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may be added to the address and the result is also a valid memory
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address.
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<p><a name="index-autoincrement_002fdecrement-addressing-3441"></a>For example, an address which is constant is offsettable; so is an
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address that is the sum of a register and a constant (as long as a
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slightly larger constant is also within the range of address-offsets
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supported by the machine); but an autoincrement or autodecrement
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address is not offsettable. More complicated indirect/indexed
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addresses may or may not be offsettable depending on the other
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addressing modes that the machine supports.
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<p>Note that in an output operand which can be matched by another
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operand, the constraint letter ‘<samp><span class="samp">o</span></samp>’ is valid only when accompanied
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by both ‘<samp><span class="samp"><</span></samp>’ (if the target machine has predecrement addressing)
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and ‘<samp><span class="samp">></span></samp>’ (if the target machine has preincrement addressing).
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<p><a name="index-g_t_0040samp_007bV_007d-in-constraint-3442"></a><br><dt>‘<samp><span class="samp">V</span></samp>’<dd>A memory operand that is not offsettable. In other words, anything that
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would fit the ‘<samp><span class="samp">m</span></samp>’ constraint but not the ‘<samp><span class="samp">o</span></samp>’ constraint.
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<p><a name="index-g_t_0040samp_007b_003c_007d-in-constraint-3443"></a><br><dt>‘<samp><span class="samp"><</span></samp>’<dd>A memory operand with autodecrement addressing (either predecrement or
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postdecrement) is allowed. In inline <code>asm</code> this constraint is only
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allowed if the operand is used exactly once in an instruction that can
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handle the side-effects. Not using an operand with ‘<samp><span class="samp"><</span></samp>’ in constraint
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string in the inline <code>asm</code> pattern at all or using it in multiple
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instructions isn't valid, because the side-effects wouldn't be performed
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or would be performed more than once. Furthermore, on some targets
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the operand with ‘<samp><span class="samp"><</span></samp>’ in constraint string must be accompanied by
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special instruction suffixes like <code>%U0</code> instruction suffix on PowerPC
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or <code>%P0</code> on IA-64.
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<p><a name="index-g_t_0040samp_007b_003e_007d-in-constraint-3444"></a><br><dt>‘<samp><span class="samp">></span></samp>’<dd>A memory operand with autoincrement addressing (either preincrement or
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postincrement) is allowed. In inline <code>asm</code> the same restrictions
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as for ‘<samp><span class="samp"><</span></samp>’ apply.
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<p><a name="index-g_t_0040samp_007br_007d-in-constraint-3445"></a><a name="index-registers-in-constraints-3446"></a><br><dt>‘<samp><span class="samp">r</span></samp>’<dd>A register operand is allowed provided that it is in a general
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register.
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<p><a name="index-constants-in-constraints-3447"></a><a name="index-g_t_0040samp_007bi_007d-in-constraint-3448"></a><br><dt>‘<samp><span class="samp">i</span></samp>’<dd>An immediate integer operand (one with constant value) is allowed.
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This includes symbolic constants whose values will be known only at
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assembly time or later.
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<p><a name="index-g_t_0040samp_007bn_007d-in-constraint-3449"></a><br><dt>‘<samp><span class="samp">n</span></samp>’<dd>An immediate integer operand with a known numeric value is allowed.
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Many systems cannot support assembly-time constants for operands less
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than a word wide. Constraints for these operands should use ‘<samp><span class="samp">n</span></samp>’
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rather than ‘<samp><span class="samp">i</span></samp>’.
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<p><a name="index-g_t_0040samp_007bI_007d-in-constraint-3450"></a><br><dt>‘<samp><span class="samp">I</span></samp>’, ‘<samp><span class="samp">J</span></samp>’, ‘<samp><span class="samp">K</span></samp>’, <small class="dots">...</small> ‘<samp><span class="samp">P</span></samp>’<dd>Other letters in the range ‘<samp><span class="samp">I</span></samp>’ through ‘<samp><span class="samp">P</span></samp>’ may be defined in
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a machine-dependent fashion to permit immediate integer operands with
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explicit integer values in specified ranges. For example, on the
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68000, ‘<samp><span class="samp">I</span></samp>’ is defined to stand for the range of values 1 to 8.
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This is the range permitted as a shift count in the shift
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instructions.
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<p><a name="index-g_t_0040samp_007bE_007d-in-constraint-3451"></a><br><dt>‘<samp><span class="samp">E</span></samp>’<dd>An immediate floating operand (expression code <code>const_double</code>) is
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allowed, but only if the target floating point format is the same as
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that of the host machine (on which the compiler is running).
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<p><a name="index-g_t_0040samp_007bF_007d-in-constraint-3452"></a><br><dt>‘<samp><span class="samp">F</span></samp>’<dd>An immediate floating operand (expression code <code>const_double</code> or
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<code>const_vector</code>) is allowed.
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<p><a name="index-g_t_0040samp_007bG_007d-in-constraint-3453"></a><a name="index-g_t_0040samp_007bH_007d-in-constraint-3454"></a><br><dt>‘<samp><span class="samp">G</span></samp>’, ‘<samp><span class="samp">H</span></samp>’<dd>‘<samp><span class="samp">G</span></samp>’ and ‘<samp><span class="samp">H</span></samp>’ may be defined in a machine-dependent fashion to
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permit immediate floating operands in particular ranges of values.
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<p><a name="index-g_t_0040samp_007bs_007d-in-constraint-3455"></a><br><dt>‘<samp><span class="samp">s</span></samp>’<dd>An immediate integer operand whose value is not an explicit integer is
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allowed.
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<p>This might appear strange; if an insn allows a constant operand with a
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value not known at compile time, it certainly must allow any known
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value. So why use ‘<samp><span class="samp">s</span></samp>’ instead of ‘<samp><span class="samp">i</span></samp>’? Sometimes it allows
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better code to be generated.
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<p>For example, on the 68000 in a fullword instruction it is possible to
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use an immediate operand; but if the immediate value is between −128
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and 127, better code results from loading the value into a register and
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using the register. This is because the load into the register can be
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done with a ‘<samp><span class="samp">moveq</span></samp>’ instruction. We arrange for this to happen
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by defining the letter ‘<samp><span class="samp">K</span></samp>’ to mean “any integer outside the
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range −128 to 127”, and then specifying ‘<samp><span class="samp">Ks</span></samp>’ in the operand
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constraints.
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<p><a name="index-g_t_0040samp_007bg_007d-in-constraint-3456"></a><br><dt>‘<samp><span class="samp">g</span></samp>’<dd>Any register, memory or immediate integer operand is allowed, except for
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registers that are not general registers.
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<p><a name="index-g_t_0040samp_007bX_007d-in-constraint-3457"></a><br><dt>‘<samp><span class="samp">X</span></samp>’<dd>Any operand whatsoever is allowed.
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<p><a name="index-g_t_0040samp_007b0_007d-in-constraint-3458"></a><a name="index-digits-in-constraint-3459"></a><br><dt>‘<samp><span class="samp">0</span></samp>’, ‘<samp><span class="samp">1</span></samp>’, ‘<samp><span class="samp">2</span></samp>’, <small class="dots">...</small> ‘<samp><span class="samp">9</span></samp>’<dd>An operand that matches the specified operand number is allowed. If a
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digit is used together with letters within the same alternative, the
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digit should come last.
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<p>This number is allowed to be more than a single digit. If multiple
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digits are encountered consecutively, they are interpreted as a single
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decimal integer. There is scant chance for ambiguity, since to-date
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it has never been desirable that ‘<samp><span class="samp">10</span></samp>’ be interpreted as matching
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either operand 1 <em>or</em> operand 0. Should this be desired, one
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can use multiple alternatives instead.
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<p><a name="index-matching-constraint-3460"></a><a name="index-constraint_002c-matching-3461"></a>This is called a <dfn>matching constraint</dfn> and what it really means is
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that the assembler has only a single operand that fills two roles
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which <code>asm</code> distinguishes. For example, an add instruction uses
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two input operands and an output operand, but on most CISC
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machines an add instruction really has only two operands, one of them an
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input-output operand:
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<pre class="smallexample"> addl #35,r12
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</pre>
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<p>Matching constraints are used in these circumstances.
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More precisely, the two operands that match must include one input-only
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operand and one output-only operand. Moreover, the digit must be a
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smaller number than the number of the operand that uses it in the
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constraint.
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<p><a name="index-load-address-instruction-3462"></a><a name="index-push-address-instruction-3463"></a><a name="index-address-constraints-3464"></a><a name="index-g_t_0040samp_007bp_007d-in-constraint-3465"></a><br><dt>‘<samp><span class="samp">p</span></samp>’<dd>An operand that is a valid memory address is allowed. This is
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for “load address” and “push address” instructions.
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<p><a name="index-address_005foperand-3466"></a>‘<samp><span class="samp">p</span></samp>’ in the constraint must be accompanied by <code>address_operand</code>
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as the predicate in the <code>match_operand</code>. This predicate interprets
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the mode specified in the <code>match_operand</code> as the mode of the memory
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reference for which the address would be valid.
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<p><a name="index-other-register-constraints-3467"></a><a name="index-extensible-constraints-3468"></a><br><dt><var>other-letters</var><dd>Other letters can be defined in machine-dependent fashion to stand for
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particular classes of registers or other arbitrary operand types.
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‘<samp><span class="samp">d</span></samp>’, ‘<samp><span class="samp">a</span></samp>’ and ‘<samp><span class="samp">f</span></samp>’ are defined on the 68000/68020 to stand
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for data, address and floating point registers.
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</dl>
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