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114 lines
8.3 KiB
C
114 lines
8.3 KiB
C
/**
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* \brief Component description for TRNG
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-03-12T17:27:04Z */
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#ifndef _SAME54_TRNG_COMPONENT_H_
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#define _SAME54_TRNG_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR TRNG */
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/* ************************************************************************** */
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/* -------- TRNG_CTRLA : (TRNG Offset: 0x00) (R/W 8) Control A -------- */
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#define TRNG_CTRLA_RESETVALUE _U_(0x00) /**< (TRNG_CTRLA) Control A Reset Value */
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#define TRNG_CTRLA_ENABLE_Pos _U_(1) /**< (TRNG_CTRLA) Enable Position */
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#define TRNG_CTRLA_ENABLE_Msk (_U_(0x1) << TRNG_CTRLA_ENABLE_Pos) /**< (TRNG_CTRLA) Enable Mask */
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#define TRNG_CTRLA_ENABLE(value) (TRNG_CTRLA_ENABLE_Msk & ((value) << TRNG_CTRLA_ENABLE_Pos))
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#define TRNG_CTRLA_RUNSTDBY_Pos _U_(6) /**< (TRNG_CTRLA) Run in Standby Position */
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#define TRNG_CTRLA_RUNSTDBY_Msk (_U_(0x1) << TRNG_CTRLA_RUNSTDBY_Pos) /**< (TRNG_CTRLA) Run in Standby Mask */
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#define TRNG_CTRLA_RUNSTDBY(value) (TRNG_CTRLA_RUNSTDBY_Msk & ((value) << TRNG_CTRLA_RUNSTDBY_Pos))
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#define TRNG_CTRLA_Msk _U_(0x42) /**< (TRNG_CTRLA) Register Mask */
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/* -------- TRNG_EVCTRL : (TRNG Offset: 0x04) (R/W 8) Event Control -------- */
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#define TRNG_EVCTRL_RESETVALUE _U_(0x00) /**< (TRNG_EVCTRL) Event Control Reset Value */
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#define TRNG_EVCTRL_DATARDYEO_Pos _U_(0) /**< (TRNG_EVCTRL) Data Ready Event Output Position */
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#define TRNG_EVCTRL_DATARDYEO_Msk (_U_(0x1) << TRNG_EVCTRL_DATARDYEO_Pos) /**< (TRNG_EVCTRL) Data Ready Event Output Mask */
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#define TRNG_EVCTRL_DATARDYEO(value) (TRNG_EVCTRL_DATARDYEO_Msk & ((value) << TRNG_EVCTRL_DATARDYEO_Pos))
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#define TRNG_EVCTRL_Msk _U_(0x01) /**< (TRNG_EVCTRL) Register Mask */
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/* -------- TRNG_INTENCLR : (TRNG Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */
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#define TRNG_INTENCLR_RESETVALUE _U_(0x00) /**< (TRNG_INTENCLR) Interrupt Enable Clear Reset Value */
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#define TRNG_INTENCLR_DATARDY_Pos _U_(0) /**< (TRNG_INTENCLR) Data Ready Interrupt Enable Position */
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#define TRNG_INTENCLR_DATARDY_Msk (_U_(0x1) << TRNG_INTENCLR_DATARDY_Pos) /**< (TRNG_INTENCLR) Data Ready Interrupt Enable Mask */
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#define TRNG_INTENCLR_DATARDY(value) (TRNG_INTENCLR_DATARDY_Msk & ((value) << TRNG_INTENCLR_DATARDY_Pos))
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#define TRNG_INTENCLR_Msk _U_(0x01) /**< (TRNG_INTENCLR) Register Mask */
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/* -------- TRNG_INTENSET : (TRNG Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */
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#define TRNG_INTENSET_RESETVALUE _U_(0x00) /**< (TRNG_INTENSET) Interrupt Enable Set Reset Value */
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#define TRNG_INTENSET_DATARDY_Pos _U_(0) /**< (TRNG_INTENSET) Data Ready Interrupt Enable Position */
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#define TRNG_INTENSET_DATARDY_Msk (_U_(0x1) << TRNG_INTENSET_DATARDY_Pos) /**< (TRNG_INTENSET) Data Ready Interrupt Enable Mask */
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#define TRNG_INTENSET_DATARDY(value) (TRNG_INTENSET_DATARDY_Msk & ((value) << TRNG_INTENSET_DATARDY_Pos))
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#define TRNG_INTENSET_Msk _U_(0x01) /**< (TRNG_INTENSET) Register Mask */
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/* -------- TRNG_INTFLAG : (TRNG Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */
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#define TRNG_INTFLAG_RESETVALUE _U_(0x00) /**< (TRNG_INTFLAG) Interrupt Flag Status and Clear Reset Value */
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#define TRNG_INTFLAG_DATARDY_Pos _U_(0) /**< (TRNG_INTFLAG) Data Ready Interrupt Flag Position */
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#define TRNG_INTFLAG_DATARDY_Msk (_U_(0x1) << TRNG_INTFLAG_DATARDY_Pos) /**< (TRNG_INTFLAG) Data Ready Interrupt Flag Mask */
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#define TRNG_INTFLAG_DATARDY(value) (TRNG_INTFLAG_DATARDY_Msk & ((value) << TRNG_INTFLAG_DATARDY_Pos))
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#define TRNG_INTFLAG_Msk _U_(0x01) /**< (TRNG_INTFLAG) Register Mask */
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/* -------- TRNG_DATA : (TRNG Offset: 0x20) ( R/ 32) Output Data -------- */
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#define TRNG_DATA_RESETVALUE _U_(0x00) /**< (TRNG_DATA) Output Data Reset Value */
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#define TRNG_DATA_DATA_Pos _U_(0) /**< (TRNG_DATA) Output Data Position */
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#define TRNG_DATA_DATA_Msk (_U_(0xFFFFFFFF) << TRNG_DATA_DATA_Pos) /**< (TRNG_DATA) Output Data Mask */
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#define TRNG_DATA_DATA(value) (TRNG_DATA_DATA_Msk & ((value) << TRNG_DATA_DATA_Pos))
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#define TRNG_DATA_Msk _U_(0xFFFFFFFF) /**< (TRNG_DATA) Register Mask */
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/** \brief TRNG register offsets definitions */
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#define TRNG_CTRLA_REG_OFST (0x00) /**< (TRNG_CTRLA) Control A Offset */
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#define TRNG_EVCTRL_REG_OFST (0x04) /**< (TRNG_EVCTRL) Event Control Offset */
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#define TRNG_INTENCLR_REG_OFST (0x08) /**< (TRNG_INTENCLR) Interrupt Enable Clear Offset */
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#define TRNG_INTENSET_REG_OFST (0x09) /**< (TRNG_INTENSET) Interrupt Enable Set Offset */
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#define TRNG_INTFLAG_REG_OFST (0x0A) /**< (TRNG_INTFLAG) Interrupt Flag Status and Clear Offset */
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#define TRNG_DATA_REG_OFST (0x20) /**< (TRNG_DATA) Output Data Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief TRNG register API structure */
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typedef struct
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{ /* True Random Generator */
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__IO uint8_t TRNG_CTRLA; /**< Offset: 0x00 (R/W 8) Control A */
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__I uint8_t Reserved1[0x03];
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__IO uint8_t TRNG_EVCTRL; /**< Offset: 0x04 (R/W 8) Event Control */
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__I uint8_t Reserved2[0x03];
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__IO uint8_t TRNG_INTENCLR; /**< Offset: 0x08 (R/W 8) Interrupt Enable Clear */
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__IO uint8_t TRNG_INTENSET; /**< Offset: 0x09 (R/W 8) Interrupt Enable Set */
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__IO uint8_t TRNG_INTFLAG; /**< Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */
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__I uint8_t Reserved3[0x15];
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__I uint32_t TRNG_DATA; /**< Offset: 0x20 (R/ 32) Output Data */
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} trng_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME54_TRNG_COMPONENT_H_ */
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