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103 lines
7.7 KiB
C
103 lines
7.7 KiB
C
/**
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* \brief Component description for TRNG
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*
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* Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.
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*
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* Subject to your compliance with these terms, you may use Microchip software and any derivatives
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* exclusively with Microchip products. It is your responsibility to comply with third party license
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* terms applicable to your use of third party software (including open source software) that may
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* accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY,
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* APPLY TO THIS SOFTWARE, INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND
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* FITNESS FOR A PARTICULAR PURPOSE.
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*
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* IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE SOFTWARE, HOWEVER CAUSED, EVEN IF
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* MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THIS SOFTWARE WILL NOT
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* EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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*/
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/* file generated from device description version 2020-03-04T11:03:42Z */
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#ifndef _SAME70_TRNG_COMPONENT_H_
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#define _SAME70_TRNG_COMPONENT_H_
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/* ************************************************************************** */
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/* SOFTWARE API DEFINITION FOR TRNG */
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/* ************************************************************************** */
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/* -------- TRNG_CR : (TRNG Offset: 0x00) ( /W 32) Control Register -------- */
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#define TRNG_CR_ENABLE_Pos _U_(0) /**< (TRNG_CR) Enables the TRNG to Provide Random Values Position */
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#define TRNG_CR_ENABLE_Msk (_U_(0x1) << TRNG_CR_ENABLE_Pos) /**< (TRNG_CR) Enables the TRNG to Provide Random Values Mask */
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#define TRNG_CR_ENABLE(value) (TRNG_CR_ENABLE_Msk & ((value) << TRNG_CR_ENABLE_Pos))
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#define TRNG_CR_KEY_Pos _U_(8) /**< (TRNG_CR) Security Key Position */
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#define TRNG_CR_KEY_Msk (_U_(0xFFFFFF) << TRNG_CR_KEY_Pos) /**< (TRNG_CR) Security Key Mask */
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#define TRNG_CR_KEY(value) (TRNG_CR_KEY_Msk & ((value) << TRNG_CR_KEY_Pos))
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#define TRNG_CR_KEY_PASSWD_Val _U_(0x524E47) /**< (TRNG_CR) Writing any other value in this field aborts the write operation. */
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#define TRNG_CR_KEY_PASSWD (TRNG_CR_KEY_PASSWD_Val << TRNG_CR_KEY_Pos) /**< (TRNG_CR) Writing any other value in this field aborts the write operation. Position */
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#define TRNG_CR_Msk _U_(0xFFFFFF01) /**< (TRNG_CR) Register Mask */
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/* -------- TRNG_IER : (TRNG Offset: 0x10) ( /W 32) Interrupt Enable Register -------- */
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#define TRNG_IER_DATRDY_Pos _U_(0) /**< (TRNG_IER) Data Ready Interrupt Enable Position */
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#define TRNG_IER_DATRDY_Msk (_U_(0x1) << TRNG_IER_DATRDY_Pos) /**< (TRNG_IER) Data Ready Interrupt Enable Mask */
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#define TRNG_IER_DATRDY(value) (TRNG_IER_DATRDY_Msk & ((value) << TRNG_IER_DATRDY_Pos))
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#define TRNG_IER_Msk _U_(0x00000001) /**< (TRNG_IER) Register Mask */
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/* -------- TRNG_IDR : (TRNG Offset: 0x14) ( /W 32) Interrupt Disable Register -------- */
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#define TRNG_IDR_DATRDY_Pos _U_(0) /**< (TRNG_IDR) Data Ready Interrupt Disable Position */
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#define TRNG_IDR_DATRDY_Msk (_U_(0x1) << TRNG_IDR_DATRDY_Pos) /**< (TRNG_IDR) Data Ready Interrupt Disable Mask */
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#define TRNG_IDR_DATRDY(value) (TRNG_IDR_DATRDY_Msk & ((value) << TRNG_IDR_DATRDY_Pos))
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#define TRNG_IDR_Msk _U_(0x00000001) /**< (TRNG_IDR) Register Mask */
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/* -------- TRNG_IMR : (TRNG Offset: 0x18) ( R/ 32) Interrupt Mask Register -------- */
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#define TRNG_IMR_DATRDY_Pos _U_(0) /**< (TRNG_IMR) Data Ready Interrupt Mask Position */
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#define TRNG_IMR_DATRDY_Msk (_U_(0x1) << TRNG_IMR_DATRDY_Pos) /**< (TRNG_IMR) Data Ready Interrupt Mask Mask */
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#define TRNG_IMR_DATRDY(value) (TRNG_IMR_DATRDY_Msk & ((value) << TRNG_IMR_DATRDY_Pos))
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#define TRNG_IMR_Msk _U_(0x00000001) /**< (TRNG_IMR) Register Mask */
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/* -------- TRNG_ISR : (TRNG Offset: 0x1C) ( R/ 32) Interrupt Status Register -------- */
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#define TRNG_ISR_DATRDY_Pos _U_(0) /**< (TRNG_ISR) Data Ready Position */
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#define TRNG_ISR_DATRDY_Msk (_U_(0x1) << TRNG_ISR_DATRDY_Pos) /**< (TRNG_ISR) Data Ready Mask */
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#define TRNG_ISR_DATRDY(value) (TRNG_ISR_DATRDY_Msk & ((value) << TRNG_ISR_DATRDY_Pos))
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#define TRNG_ISR_Msk _U_(0x00000001) /**< (TRNG_ISR) Register Mask */
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/* -------- TRNG_ODATA : (TRNG Offset: 0x50) ( R/ 32) Output Data Register -------- */
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#define TRNG_ODATA_ODATA_Pos _U_(0) /**< (TRNG_ODATA) Output Data Position */
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#define TRNG_ODATA_ODATA_Msk (_U_(0xFFFFFFFF) << TRNG_ODATA_ODATA_Pos) /**< (TRNG_ODATA) Output Data Mask */
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#define TRNG_ODATA_ODATA(value) (TRNG_ODATA_ODATA_Msk & ((value) << TRNG_ODATA_ODATA_Pos))
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#define TRNG_ODATA_Msk _U_(0xFFFFFFFF) /**< (TRNG_ODATA) Register Mask */
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/** \brief TRNG register offsets definitions */
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#define TRNG_CR_REG_OFST (0x00) /**< (TRNG_CR) Control Register Offset */
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#define TRNG_IER_REG_OFST (0x10) /**< (TRNG_IER) Interrupt Enable Register Offset */
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#define TRNG_IDR_REG_OFST (0x14) /**< (TRNG_IDR) Interrupt Disable Register Offset */
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#define TRNG_IMR_REG_OFST (0x18) /**< (TRNG_IMR) Interrupt Mask Register Offset */
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#define TRNG_ISR_REG_OFST (0x1C) /**< (TRNG_ISR) Interrupt Status Register Offset */
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#define TRNG_ODATA_REG_OFST (0x50) /**< (TRNG_ODATA) Output Data Register Offset */
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#if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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/** \brief TRNG register API structure */
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typedef struct
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{
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__O uint32_t TRNG_CR; /**< Offset: 0x00 ( /W 32) Control Register */
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__I uint8_t Reserved1[0x0C];
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__O uint32_t TRNG_IER; /**< Offset: 0x10 ( /W 32) Interrupt Enable Register */
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__O uint32_t TRNG_IDR; /**< Offset: 0x14 ( /W 32) Interrupt Disable Register */
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__I uint32_t TRNG_IMR; /**< Offset: 0x18 (R/ 32) Interrupt Mask Register */
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__I uint32_t TRNG_ISR; /**< Offset: 0x1C (R/ 32) Interrupt Status Register */
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__I uint8_t Reserved2[0x30];
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__I uint32_t TRNG_ODATA; /**< Offset: 0x50 (R/ 32) Output Data Register */
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} trng_registers_t;
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#endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAME70_TRNG_COMPONENT_H_ */
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