SAME54P20A Test Project
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TCC hardware registers. More...
#include <tcc.h>
Data Fields | |
__IO TCC_CTRLA_Type | CTRLA |
Offset: 0x00 (R/W 32) Control A. | |
__IO TCC_CTRLBCLR_Type | CTRLBCLR |
Offset: 0x04 (R/W 8) Control B Clear. | |
__IO TCC_CTRLBSET_Type | CTRLBSET |
Offset: 0x05 (R/W 8) Control B Set. | |
RoReg8 | Reserved1 [0x2] |
__I TCC_SYNCBUSY_Type | SYNCBUSY |
Offset: 0x08 (R/ 32) Synchronization Busy. | |
__IO TCC_FCTRLA_Type | FCTRLA |
Offset: 0x0C (R/W 32) Recoverable Fault A Configuration. | |
__IO TCC_FCTRLB_Type | FCTRLB |
Offset: 0x10 (R/W 32) Recoverable Fault B Configuration. | |
__IO TCC_WEXCTRL_Type | WEXCTRL |
Offset: 0x14 (R/W 32) Waveform Extension Configuration. | |
__IO TCC_DRVCTRL_Type | DRVCTRL |
Offset: 0x18 (R/W 32) Driver Control. | |
RoReg8 | Reserved2 [0x2] |
__IO TCC_DBGCTRL_Type | DBGCTRL |
Offset: 0x1E (R/W 8) Debug Control. | |
RoReg8 | Reserved3 [0x1] |
__IO TCC_EVCTRL_Type | EVCTRL |
Offset: 0x20 (R/W 32) Event Control. | |
__IO TCC_INTENCLR_Type | INTENCLR |
Offset: 0x24 (R/W 32) Interrupt Enable Clear. | |
__IO TCC_INTENSET_Type | INTENSET |
Offset: 0x28 (R/W 32) Interrupt Enable Set. | |
__IO TCC_INTFLAG_Type | INTFLAG |
Offset: 0x2C (R/W 32) Interrupt Flag Status and Clear. | |
__IO TCC_STATUS_Type | STATUS |
Offset: 0x30 (R/W 32) Status. | |
__IO TCC_COUNT_Type | COUNT |
Offset: 0x34 (R/W 32) Count. | |
__IO TCC_PATT_Type | PATT |
Offset: 0x38 (R/W 16) Pattern. | |
RoReg8 | Reserved4 [0x2] |
__IO TCC_WAVE_Type | WAVE |
Offset: 0x3C (R/W 32) Waveform Control. | |
__IO TCC_PER_Type | PER |
Offset: 0x40 (R/W 32) Period. | |
__IO TCC_CC_Type | CC [6] |
Offset: 0x44 (R/W 32) Compare and Capture. | |
RoReg8 | Reserved5 [0x8] |
__IO TCC_PATTBUF_Type | PATTBUF |
Offset: 0x64 (R/W 16) Pattern Buffer. | |
RoReg8 | Reserved6 [0x6] |
__IO TCC_PERBUF_Type | PERBUF |
Offset: 0x6C (R/W 32) Period Buffer. | |
__IO TCC_CCBUF_Type | CCBUF [6] |
Offset: 0x70 (R/W 32) Compare and Capture Buffer. | |