SAME54P20A Test Project
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Instance description for RTC. More...
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Macros | |
#define | REG_RTC_DBGCTRL (*(RwReg8 *)0x4000240EUL) |
(RTC) Debug Control | |
#define | REG_RTC_FREQCORR (*(RwReg8 *)0x40002414UL) |
(RTC) Frequency Correction | |
#define | REG_RTC_GP0 (*(RwReg *)0x40002440UL) |
(RTC) General Purpose 0 | |
#define | REG_RTC_GP1 (*(RwReg *)0x40002444UL) |
(RTC) General Purpose 1 | |
#define | REG_RTC_GP2 (*(RwReg *)0x40002448UL) |
(RTC) General Purpose 2 | |
#define | REG_RTC_GP3 (*(RwReg *)0x4000244CUL) |
(RTC) General Purpose 3 | |
#define | REG_RTC_TAMPCTRL (*(RwReg *)0x40002460UL) |
(RTC) Tamper Control | |
#define | REG_RTC_TAMPID (*(RwReg *)0x40002468UL) |
(RTC) Tamper ID | |
#define | REG_RTC_BKUP0 (*(RwReg *)0x40002480UL) |
(RTC) Backup 0 | |
#define | REG_RTC_BKUP1 (*(RwReg *)0x40002484UL) |
(RTC) Backup 1 | |
#define | REG_RTC_BKUP2 (*(RwReg *)0x40002488UL) |
(RTC) Backup 2 | |
#define | REG_RTC_BKUP3 (*(RwReg *)0x4000248CUL) |
(RTC) Backup 3 | |
#define | REG_RTC_BKUP4 (*(RwReg *)0x40002490UL) |
(RTC) Backup 4 | |
#define | REG_RTC_BKUP5 (*(RwReg *)0x40002494UL) |
(RTC) Backup 5 | |
#define | REG_RTC_BKUP6 (*(RwReg *)0x40002498UL) |
(RTC) Backup 6 | |
#define | REG_RTC_BKUP7 (*(RwReg *)0x4000249CUL) |
(RTC) Backup 7 | |
#define | REG_RTC_MODE0_CTRLA (*(RwReg16*)0x40002400UL) |
(RTC) MODE0 Control A | |
#define | REG_RTC_MODE0_CTRLB (*(RwReg16*)0x40002402UL) |
(RTC) MODE0 Control B | |
#define | REG_RTC_MODE0_EVCTRL (*(RwReg *)0x40002404UL) |
(RTC) MODE0 Event Control | |
#define | REG_RTC_MODE0_INTENCLR (*(RwReg16*)0x40002408UL) |
(RTC) MODE0 Interrupt Enable Clear | |
#define | REG_RTC_MODE0_INTENSET (*(RwReg16*)0x4000240AUL) |
(RTC) MODE0 Interrupt Enable Set | |
#define | REG_RTC_MODE0_INTFLAG (*(RwReg16*)0x4000240CUL) |
(RTC) MODE0 Interrupt Flag Status and Clear | |
#define | REG_RTC_MODE0_SYNCBUSY (*(RoReg *)0x40002410UL) |
(RTC) MODE0 Synchronization Busy Status | |
#define | REG_RTC_MODE0_COUNT (*(RwReg *)0x40002418UL) |
(RTC) MODE0 Counter Value | |
#define | REG_RTC_MODE0_COMP0 (*(RwReg *)0x40002420UL) |
(RTC) MODE0 Compare 0 Value | |
#define | REG_RTC_MODE0_COMP1 (*(RwReg *)0x40002424UL) |
(RTC) MODE0 Compare 1 Value | |
#define | REG_RTC_MODE0_TIMESTAMP (*(RoReg *)0x40002464UL) |
(RTC) MODE0 Timestamp | |
#define | REG_RTC_MODE1_CTRLA (*(RwReg16*)0x40002400UL) |
(RTC) MODE1 Control A | |
#define | REG_RTC_MODE1_CTRLB (*(RwReg16*)0x40002402UL) |
(RTC) MODE1 Control B | |
#define | REG_RTC_MODE1_EVCTRL (*(RwReg *)0x40002404UL) |
(RTC) MODE1 Event Control | |
#define | REG_RTC_MODE1_INTENCLR (*(RwReg16*)0x40002408UL) |
(RTC) MODE1 Interrupt Enable Clear | |
#define | REG_RTC_MODE1_INTENSET (*(RwReg16*)0x4000240AUL) |
(RTC) MODE1 Interrupt Enable Set | |
#define | REG_RTC_MODE1_INTFLAG (*(RwReg16*)0x4000240CUL) |
(RTC) MODE1 Interrupt Flag Status and Clear | |
#define | REG_RTC_MODE1_SYNCBUSY (*(RoReg *)0x40002410UL) |
(RTC) MODE1 Synchronization Busy Status | |
#define | REG_RTC_MODE1_COUNT (*(RwReg16*)0x40002418UL) |
(RTC) MODE1 Counter Value | |
#define | REG_RTC_MODE1_PER (*(RwReg16*)0x4000241CUL) |
(RTC) MODE1 Counter Period | |
#define | REG_RTC_MODE1_COMP0 (*(RwReg16*)0x40002420UL) |
(RTC) MODE1 Compare 0 Value | |
#define | REG_RTC_MODE1_COMP1 (*(RwReg16*)0x40002422UL) |
(RTC) MODE1 Compare 1 Value | |
#define | REG_RTC_MODE1_COMP2 (*(RwReg16*)0x40002424UL) |
(RTC) MODE1 Compare 2 Value | |
#define | REG_RTC_MODE1_COMP3 (*(RwReg16*)0x40002426UL) |
(RTC) MODE1 Compare 3 Value | |
#define | REG_RTC_MODE1_TIMESTAMP (*(RoReg *)0x40002464UL) |
(RTC) MODE1 Timestamp | |
#define | REG_RTC_MODE2_CTRLA (*(RwReg16*)0x40002400UL) |
(RTC) MODE2 Control A | |
#define | REG_RTC_MODE2_CTRLB (*(RwReg16*)0x40002402UL) |
(RTC) MODE2 Control B | |
#define | REG_RTC_MODE2_EVCTRL (*(RwReg *)0x40002404UL) |
(RTC) MODE2 Event Control | |
#define | REG_RTC_MODE2_INTENCLR (*(RwReg16*)0x40002408UL) |
(RTC) MODE2 Interrupt Enable Clear | |
#define | REG_RTC_MODE2_INTENSET (*(RwReg16*)0x4000240AUL) |
(RTC) MODE2 Interrupt Enable Set | |
#define | REG_RTC_MODE2_INTFLAG (*(RwReg16*)0x4000240CUL) |
(RTC) MODE2 Interrupt Flag Status and Clear | |
#define | REG_RTC_MODE2_SYNCBUSY (*(RoReg *)0x40002410UL) |
(RTC) MODE2 Synchronization Busy Status | |
#define | REG_RTC_MODE2_CLOCK (*(RwReg *)0x40002418UL) |
(RTC) MODE2 Clock Value | |
#define | REG_RTC_MODE2_TIMESTAMP (*(RoReg *)0x40002464UL) |
(RTC) MODE2 Timestamp | |
#define | REG_RTC_MODE2_ALARM_ALARM0 (*(RwReg *)0x40002420UL) |
(RTC) MODE2_ALARM Alarm 0 Value | |
#define | REG_RTC_MODE2_ALARM_MASK0 (*(RwReg8 *)0x40002424UL) |
(RTC) MODE2_ALARM Alarm 0 Mask | |
#define | REG_RTC_MODE2_ALARM_ALARM1 (*(RwReg *)0x40002428UL) |
(RTC) MODE2_ALARM Alarm 1 Value | |
#define | REG_RTC_MODE2_ALARM_MASK1 (*(RwReg8 *)0x4000242CUL) |
(RTC) MODE2_ALARM Alarm 1 Mask | |
#define | RTC_DMAC_ID_TIMESTAMP 1 |
#define | RTC_GPR_NUM 4 |
#define | RTC_NUM_OF_ALARMS 2 |
#define | RTC_NUM_OF_BKREGS 8 |
#define | RTC_NUM_OF_COMP16 4 |
#define | RTC_NUM_OF_COMP32 2 |
#define | RTC_NUM_OF_TAMPERS 5 |
#define | RTC_PER_NUM 8 |
Instance description for RTC.
Copyright (c) 2019 Microchip Technology Inc.
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Definition in file rtc.h.