SAME54P20A Test Project
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Instance description for QSPI. More...
Go to the source code of this file.
Macros | |
#define | REG_QSPI_CTRLA (*(RwReg *)0x42003400UL) |
(QSPI) Control A | |
#define | REG_QSPI_CTRLB (*(RwReg *)0x42003404UL) |
(QSPI) Control B | |
#define | REG_QSPI_BAUD (*(RwReg *)0x42003408UL) |
(QSPI) Baud Rate | |
#define | REG_QSPI_RXDATA (*(RoReg *)0x4200340CUL) |
(QSPI) Receive Data | |
#define | REG_QSPI_TXDATA (*(WoReg *)0x42003410UL) |
(QSPI) Transmit Data | |
#define | REG_QSPI_INTENCLR (*(RwReg *)0x42003414UL) |
(QSPI) Interrupt Enable Clear | |
#define | REG_QSPI_INTENSET (*(RwReg *)0x42003418UL) |
(QSPI) Interrupt Enable Set | |
#define | REG_QSPI_INTFLAG (*(RwReg *)0x4200341CUL) |
(QSPI) Interrupt Flag Status and Clear | |
#define | REG_QSPI_STATUS (*(RoReg *)0x42003420UL) |
(QSPI) Status Register | |
#define | REG_QSPI_INSTRADDR (*(RwReg *)0x42003430UL) |
(QSPI) Instruction Address | |
#define | REG_QSPI_INSTRCTRL (*(RwReg *)0x42003434UL) |
(QSPI) Instruction Code | |
#define | REG_QSPI_INSTRFRAME (*(RwReg *)0x42003438UL) |
(QSPI) Instruction Frame | |
#define | REG_QSPI_SCRAMBCTRL (*(RwReg *)0x42003440UL) |
(QSPI) Scrambling Mode | |
#define | REG_QSPI_SCRAMBKEY (*(WoReg *)0x42003444UL) |
(QSPI) Scrambling Key | |
#define | QSPI_DMAC_ID_RX 83 |
#define | QSPI_DMAC_ID_TX 84 |
#define | QSPI_HADDR_MSB 23 |
#define | QSPI_OCMS 1 |
Instance description for QSPI.
Copyright (c) 2019 Microchip Technology Inc.
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Definition in file qspi.h.