Instance description for GMAC. More...

Macros
#define	REG_GMAC_NCR ((RwReg )0x42000800UL)
	(GMAC) Network Control Register

#define	REG_GMAC_NCFGR ((RwReg )0x42000804UL)
	(GMAC) Network Configuration Register

#define	REG_GMAC_NSR ((RoReg )0x42000808UL)
	(GMAC) Network Status Register

#define	REG_GMAC_UR ((RwReg )0x4200080CUL)
	(GMAC) User Register

#define	REG_GMAC_DCFGR ((RwReg )0x42000810UL)
	(GMAC) DMA Configuration Register

#define	REG_GMAC_TSR ((RwReg )0x42000814UL)
	(GMAC) Transmit Status Register

#define	REG_GMAC_RBQB ((RwReg )0x42000818UL)
	(GMAC) Receive Buffer Queue Base Address

#define	REG_GMAC_TBQB ((RwReg )0x4200081CUL)
	(GMAC) Transmit Buffer Queue Base Address

#define	REG_GMAC_RSR ((RwReg )0x42000820UL)
	(GMAC) Receive Status Register

#define	REG_GMAC_ISR ((RwReg )0x42000824UL)
	(GMAC) Interrupt Status Register

#define	REG_GMAC_IER ((WoReg )0x42000828UL)
	(GMAC) Interrupt Enable Register

#define	REG_GMAC_IDR ((WoReg )0x4200082CUL)
	(GMAC) Interrupt Disable Register

#define	REG_GMAC_IMR ((RoReg )0x42000830UL)
	(GMAC) Interrupt Mask Register

#define	REG_GMAC_MAN ((RwReg )0x42000834UL)
	(GMAC) PHY Maintenance Register

#define	REG_GMAC_RPQ ((RoReg )0x42000838UL)
	(GMAC) Received Pause Quantum Register

#define	REG_GMAC_TPQ ((RwReg )0x4200083CUL)
	(GMAC) Transmit Pause Quantum Register

#define	REG_GMAC_TPSF ((RwReg )0x42000840UL)
	(GMAC) TX partial store and forward Register

#define	REG_GMAC_RPSF ((RwReg )0x42000844UL)
	(GMAC) RX partial store and forward Register

#define	REG_GMAC_RJFML ((RwReg )0x42000848UL)
	(GMAC) RX Jumbo Frame Max Length Register

#define	REG_GMAC_HRB ((RwReg )0x42000880UL)
	(GMAC) Hash Register Bottom [31:0]

#define	REG_GMAC_HRT ((RwReg )0x42000884UL)
	(GMAC) Hash Register Top [63:32]

#define	REG_GMAC_SAB0 ((RwReg )0x42000888UL)
	(GMAC) Specific Address Bottom [31:0] Register 0

#define	REG_GMAC_SAT0 ((RwReg )0x4200088CUL)
	(GMAC) Specific Address Top [47:32] Register 0

#define	REG_GMAC_SAB1 ((RwReg )0x42000890UL)
	(GMAC) Specific Address Bottom [31:0] Register 1

#define	REG_GMAC_SAT1 ((RwReg )0x42000894UL)
	(GMAC) Specific Address Top [47:32] Register 1

#define	REG_GMAC_SAB2 ((RwReg )0x42000898UL)
	(GMAC) Specific Address Bottom [31:0] Register 2

#define	REG_GMAC_SAT2 ((RwReg )0x4200089CUL)
	(GMAC) Specific Address Top [47:32] Register 2

#define	REG_GMAC_SAB3 ((RwReg )0x420008A0UL)
	(GMAC) Specific Address Bottom [31:0] Register 3

#define	REG_GMAC_SAT3 ((RwReg )0x420008A4UL)
	(GMAC) Specific Address Top [47:32] Register 3

#define	REG_GMAC_TIDM0 ((RwReg )0x420008A8UL)
	(GMAC) Type ID Match Register 0

#define	REG_GMAC_TIDM1 ((RwReg )0x420008ACUL)
	(GMAC) Type ID Match Register 1

#define	REG_GMAC_TIDM2 ((RwReg )0x420008B0UL)
	(GMAC) Type ID Match Register 2

#define	REG_GMAC_TIDM3 ((RwReg )0x420008B4UL)
	(GMAC) Type ID Match Register 3

#define	REG_GMAC_WOL ((RwReg )0x420008B8UL)
	(GMAC) Wake on LAN

#define	REG_GMAC_IPGS ((RwReg )0x420008BCUL)
	(GMAC) IPG Stretch Register

#define	REG_GMAC_SVLAN ((RwReg )0x420008C0UL)
	(GMAC) Stacked VLAN Register

#define	REG_GMAC_TPFCP ((RwReg )0x420008C4UL)
	(GMAC) Transmit PFC Pause Register

#define	REG_GMAC_SAMB1 ((RwReg )0x420008C8UL)
	(GMAC) Specific Address 1 Mask Bottom [31:0] Register

#define	REG_GMAC_SAMT1 ((RwReg )0x420008CCUL)
	(GMAC) Specific Address 1 Mask Top [47:32] Register

#define	REG_GMAC_NSC ((RwReg )0x420008DCUL)
	(GMAC) Tsu timer comparison nanoseconds Register

#define	REG_GMAC_SCL ((RwReg )0x420008E0UL)
	(GMAC) Tsu timer second comparison Register

#define	REG_GMAC_SCH ((RwReg )0x420008E4UL)
	(GMAC) Tsu timer second comparison Register

#define	REG_GMAC_EFTSH ((RoReg )0x420008E8UL)
	(GMAC) PTP Event Frame Transmitted Seconds High Register

#define	REG_GMAC_EFRSH ((RoReg )0x420008ECUL)
	(GMAC) PTP Event Frame Received Seconds High Register

#define	REG_GMAC_PEFTSH ((RoReg )0x420008F0UL)
	(GMAC) PTP Peer Event Frame Transmitted Seconds High Register

#define	REG_GMAC_PEFRSH ((RoReg )0x420008F4UL)
	(GMAC) PTP Peer Event Frame Received Seconds High Register

#define	REG_GMAC_OTLO ((RoReg )0x42000900UL)
	(GMAC) Octets Transmitted [31:0] Register

#define	REG_GMAC_OTHI ((RoReg )0x42000904UL)
	(GMAC) Octets Transmitted [47:32] Register

#define	REG_GMAC_FT ((RoReg )0x42000908UL)
	(GMAC) Frames Transmitted Register

#define	REG_GMAC_BCFT ((RoReg )0x4200090CUL)
	(GMAC) Broadcast Frames Transmitted Register

#define	REG_GMAC_MFT ((RoReg )0x42000910UL)
	(GMAC) Multicast Frames Transmitted Register

#define	REG_GMAC_PFT ((RoReg )0x42000914UL)
	(GMAC) Pause Frames Transmitted Register

#define	REG_GMAC_BFT64 ((RoReg )0x42000918UL)
	(GMAC) 64 Byte Frames Transmitted Register

#define	REG_GMAC_TBFT127 ((RoReg )0x4200091CUL)
	(GMAC) 65 to 127 Byte Frames Transmitted Register

#define	REG_GMAC_TBFT255 ((RoReg )0x42000920UL)
	(GMAC) 128 to 255 Byte Frames Transmitted Register

#define	REG_GMAC_TBFT511 ((RoReg )0x42000924UL)
	(GMAC) 256 to 511 Byte Frames Transmitted Register

#define	REG_GMAC_TBFT1023 ((RoReg )0x42000928UL)
	(GMAC) 512 to 1023 Byte Frames Transmitted Register

#define	REG_GMAC_TBFT1518 ((RoReg )0x4200092CUL)
	(GMAC) 1024 to 1518 Byte Frames Transmitted Register

#define	REG_GMAC_GTBFT1518 ((RoReg )0x42000930UL)
	(GMAC) Greater Than 1518 Byte Frames Transmitted Register

#define	REG_GMAC_TUR ((RoReg )0x42000934UL)
	(GMAC) Transmit Underruns Register

#define	REG_GMAC_SCF ((RoReg )0x42000938UL)
	(GMAC) Single Collision Frames Register

#define	REG_GMAC_MCF ((RoReg )0x4200093CUL)
	(GMAC) Multiple Collision Frames Register

#define	REG_GMAC_EC ((RoReg )0x42000940UL)
	(GMAC) Excessive Collisions Register

#define	REG_GMAC_LC ((RoReg )0x42000944UL)
	(GMAC) Late Collisions Register

#define	REG_GMAC_DTF ((RoReg )0x42000948UL)
	(GMAC) Deferred Transmission Frames Register

#define	REG_GMAC_CSE ((RoReg )0x4200094CUL)
	(GMAC) Carrier Sense Errors Register

#define	REG_GMAC_ORLO ((RoReg )0x42000950UL)
	(GMAC) Octets Received [31:0] Received

#define	REG_GMAC_ORHI ((RoReg )0x42000954UL)
	(GMAC) Octets Received [47:32] Received

#define	REG_GMAC_FR ((RoReg )0x42000958UL)
	(GMAC) Frames Received Register

#define	REG_GMAC_BCFR ((RoReg )0x4200095CUL)
	(GMAC) Broadcast Frames Received Register

#define	REG_GMAC_MFR ((RoReg )0x42000960UL)
	(GMAC) Multicast Frames Received Register

#define	REG_GMAC_PFR ((RoReg )0x42000964UL)
	(GMAC) Pause Frames Received Register

#define	REG_GMAC_BFR64 ((RoReg )0x42000968UL)
	(GMAC) 64 Byte Frames Received Register

#define	REG_GMAC_TBFR127 ((RoReg )0x4200096CUL)
	(GMAC) 65 to 127 Byte Frames Received Register

#define	REG_GMAC_TBFR255 ((RoReg )0x42000970UL)
	(GMAC) 128 to 255 Byte Frames Received Register

#define	REG_GMAC_TBFR511 ((RoReg )0x42000974UL)
	(GMAC) 256 to 511Byte Frames Received Register

#define	REG_GMAC_TBFR1023 ((RoReg )0x42000978UL)
	(GMAC) 512 to 1023 Byte Frames Received Register

#define	REG_GMAC_TBFR1518 ((RoReg )0x4200097CUL)
	(GMAC) 1024 to 1518 Byte Frames Received Register

#define	REG_GMAC_TMXBFR ((RoReg )0x42000980UL)
	(GMAC) 1519 to Maximum Byte Frames Received Register

#define	REG_GMAC_UFR ((RoReg )0x42000984UL)
	(GMAC) Undersize Frames Received Register

#define	REG_GMAC_OFR ((RoReg )0x42000988UL)
	(GMAC) Oversize Frames Received Register

#define	REG_GMAC_JR ((RoReg )0x4200098CUL)
	(GMAC) Jabbers Received Register

#define	REG_GMAC_FCSE ((RoReg )0x42000990UL)
	(GMAC) Frame Check Sequence Errors Register

#define	REG_GMAC_LFFE ((RoReg )0x42000994UL)
	(GMAC) Length Field Frame Errors Register

#define	REG_GMAC_RSE ((RoReg )0x42000998UL)
	(GMAC) Receive Symbol Errors Register

#define	REG_GMAC_AE ((RoReg )0x4200099CUL)
	(GMAC) Alignment Errors Register

#define	REG_GMAC_RRE ((RoReg )0x420009A0UL)
	(GMAC) Receive Resource Errors Register

#define	REG_GMAC_ROE ((RoReg )0x420009A4UL)
	(GMAC) Receive Overrun Register

#define	REG_GMAC_IHCE ((RoReg )0x420009A8UL)
	(GMAC) IP Header Checksum Errors Register

#define	REG_GMAC_TCE ((RoReg )0x420009ACUL)
	(GMAC) TCP Checksum Errors Register

#define	REG_GMAC_UCE ((RoReg )0x420009B0UL)
	(GMAC) UDP Checksum Errors Register

#define	REG_GMAC_TISUBN ((RwReg )0x420009BCUL)
	(GMAC) 1588 Timer Increment [15:0] Sub-Nanoseconds Register

#define	REG_GMAC_TSH ((RwReg )0x420009C0UL)
	(GMAC) 1588 Timer Seconds High [15:0] Register

#define	REG_GMAC_TSSSL ((RwReg )0x420009C8UL)
	(GMAC) 1588 Timer Sync Strobe Seconds [31:0] Register

#define	REG_GMAC_TSSN ((RwReg )0x420009CCUL)
	(GMAC) 1588 Timer Sync Strobe Nanoseconds Register

#define	REG_GMAC_TSL ((RwReg )0x420009D0UL)
	(GMAC) 1588 Timer Seconds [31:0] Register

#define	REG_GMAC_TN ((RwReg )0x420009D4UL)
	(GMAC) 1588 Timer Nanoseconds Register

#define	REG_GMAC_TA ((WoReg )0x420009D8UL)
	(GMAC) 1588 Timer Adjust Register

#define	REG_GMAC_TI ((RwReg )0x420009DCUL)
	(GMAC) 1588 Timer Increment Register

#define	REG_GMAC_EFTSL ((RoReg )0x420009E0UL)
	(GMAC) PTP Event Frame Transmitted Seconds Low Register

#define	REG_GMAC_EFTN ((RoReg )0x420009E4UL)
	(GMAC) PTP Event Frame Transmitted Nanoseconds

#define	REG_GMAC_EFRSL ((RoReg )0x420009E8UL)
	(GMAC) PTP Event Frame Received Seconds Low Register

#define	REG_GMAC_EFRN ((RoReg )0x420009ECUL)
	(GMAC) PTP Event Frame Received Nanoseconds

#define	REG_GMAC_PEFTSL ((RoReg )0x420009F0UL)
	(GMAC) PTP Peer Event Frame Transmitted Seconds Low Register

#define	REG_GMAC_PEFTN ((RoReg )0x420009F4UL)
	(GMAC) PTP Peer Event Frame Transmitted Nanoseconds

#define	REG_GMAC_PEFRSL ((RoReg )0x420009F8UL)
	(GMAC) PTP Peer Event Frame Received Seconds Low Register

#define	REG_GMAC_PEFRN ((RoReg )0x420009FCUL)
	(GMAC) PTP Peer Event Frame Received Nanoseconds

#define	REG_GMAC_RLPITR ((RoReg )0x42000A70UL)
	(GMAC) Receive LPI transition Register

#define	REG_GMAC_RLPITI ((RoReg )0x42000A74UL)
	(GMAC) Receive LPI Time Register

#define	REG_GMAC_TLPITR ((RoReg )0x42000A78UL)
	(GMAC) Receive LPI transition Register

#define	REG_GMAC_TLPITI ((RoReg )0x42000A7CUL)
	(GMAC) Receive LPI Time Register

#define	GMAC_CLK_AHB_ID 14

Detailed Description

Instance description for GMAC.

\asf_license_start

Definition in file gmac.h.

Macros

Detailed Description