ramecc.h File Reference

Component description for RAMECC. More...

Go to the source code of this file.

Data Structures
union	RAMECC_INTENCLR_Type
union	RAMECC_INTENSET_Type
union	RAMECC_INTFLAG_Type
union	RAMECC_STATUS_Type
union	RAMECC_ERRADDR_Type
union	RAMECC_DBGCTRL_Type
struct	Ramecc
	RAMECC hardware registers. More...

Macros
#define	RAMECC_U2268
#define	REV_RAMECC   0x100
#define	RAMECC_INTENCLR_OFFSET   0x0
	(RAMECC_INTENCLR offset) Interrupt Enable Clear
#define	RAMECC_INTENCLR_RESETVALUE   _U_(0x00)
	(RAMECC_INTENCLR reset_value) Interrupt Enable Clear
#define	RAMECC_INTENCLR_SINGLEE_Pos   0
	(RAMECC_INTENCLR) Single Bit ECC Error Interrupt Enable Clear
#define	RAMECC_INTENCLR_SINGLEE   (_U_(0x1) << RAMECC_INTENCLR_SINGLEE_Pos)
#define	RAMECC_INTENCLR_DUALE_Pos   1
	(RAMECC_INTENCLR) Dual Bit ECC Error Interrupt Enable Clear
#define	RAMECC_INTENCLR_DUALE   (_U_(0x1) << RAMECC_INTENCLR_DUALE_Pos)
#define	RAMECC_INTENCLR_MASK   _U_(0x03)
	(RAMECC_INTENCLR) MASK Register
#define	RAMECC_INTENSET_OFFSET   0x1
	(RAMECC_INTENSET offset) Interrupt Enable Set
#define	RAMECC_INTENSET_RESETVALUE   _U_(0x00)
	(RAMECC_INTENSET reset_value) Interrupt Enable Set
#define	RAMECC_INTENSET_SINGLEE_Pos   0
	(RAMECC_INTENSET) Single Bit ECC Error Interrupt Enable Set
#define	RAMECC_INTENSET_SINGLEE   (_U_(0x1) << RAMECC_INTENSET_SINGLEE_Pos)
#define	RAMECC_INTENSET_DUALE_Pos   1
	(RAMECC_INTENSET) Dual Bit ECC Error Interrupt Enable Set
#define	RAMECC_INTENSET_DUALE   (_U_(0x1) << RAMECC_INTENSET_DUALE_Pos)
#define	RAMECC_INTENSET_MASK   _U_(0x03)
	(RAMECC_INTENSET) MASK Register
#define	RAMECC_INTFLAG_OFFSET   0x2
	(RAMECC_INTFLAG offset) Interrupt Flag
#define	RAMECC_INTFLAG_RESETVALUE   _U_(0x00)
	(RAMECC_INTFLAG reset_value) Interrupt Flag
#define	RAMECC_INTFLAG_SINGLEE_Pos   0
	(RAMECC_INTFLAG) Single Bit ECC Error Interrupt
#define	RAMECC_INTFLAG_SINGLEE   (_U_(0x1) << RAMECC_INTFLAG_SINGLEE_Pos)
#define	RAMECC_INTFLAG_DUALE_Pos   1
	(RAMECC_INTFLAG) Dual Bit ECC Error Interrupt
#define	RAMECC_INTFLAG_DUALE   (_U_(0x1) << RAMECC_INTFLAG_DUALE_Pos)
#define	RAMECC_INTFLAG_MASK   _U_(0x03)
	(RAMECC_INTFLAG) MASK Register
#define	RAMECC_STATUS_OFFSET   0x3
	(RAMECC_STATUS offset) Status
#define	RAMECC_STATUS_RESETVALUE   _U_(0x00)
	(RAMECC_STATUS reset_value) Status
#define	RAMECC_STATUS_ECCDIS_Pos   0
	(RAMECC_STATUS) ECC Disable
#define	RAMECC_STATUS_ECCDIS   (_U_(0x1) << RAMECC_STATUS_ECCDIS_Pos)
#define	RAMECC_STATUS_MASK   _U_(0x01)
	(RAMECC_STATUS) MASK Register
#define	RAMECC_ERRADDR_OFFSET   0x4
	(RAMECC_ERRADDR offset) Error Address
#define	RAMECC_ERRADDR_RESETVALUE   _U_(0x00000000)
	(RAMECC_ERRADDR reset_value) Error Address
#define	RAMECC_ERRADDR_ERRADDR_Pos   0
	(RAMECC_ERRADDR) Error Address
#define	RAMECC_ERRADDR_ERRADDR_Msk   (_U_(0x1FFFF) << RAMECC_ERRADDR_ERRADDR_Pos)
#define	RAMECC_ERRADDR_ERRADDR(value)   (RAMECC_ERRADDR_ERRADDR_Msk & ((value) << RAMECC_ERRADDR_ERRADDR_Pos))
#define	RAMECC_ERRADDR_MASK   _U_(0x0001FFFF)
	(RAMECC_ERRADDR) MASK Register
#define	RAMECC_DBGCTRL_OFFSET   0xF
	(RAMECC_DBGCTRL offset) Debug Control
#define	RAMECC_DBGCTRL_RESETVALUE   _U_(0x00)
	(RAMECC_DBGCTRL reset_value) Debug Control
#define	RAMECC_DBGCTRL_ECCDIS_Pos   0
	(RAMECC_DBGCTRL) ECC Disable
#define	RAMECC_DBGCTRL_ECCDIS   (_U_(0x1) << RAMECC_DBGCTRL_ECCDIS_Pos)
#define	RAMECC_DBGCTRL_ECCELOG_Pos   1
	(RAMECC_DBGCTRL) ECC Error Log
#define	RAMECC_DBGCTRL_ECCELOG   (_U_(0x1) << RAMECC_DBGCTRL_ECCELOG_Pos)
#define	RAMECC_DBGCTRL_MASK   _U_(0x03)
	(RAMECC_DBGCTRL) MASK Register

Detailed Description

Component description for RAMECC.

Copyright (c) 2019 Microchip Technology Inc.

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Definition in file ramecc.h.