SAME54P20A Test Project
Data Structures | Macros
qspi.h File Reference

Component description for QSPI. More...

Go to the source code of this file.

Data Structures

union  QSPI_CTRLA_Type
 
union  QSPI_CTRLB_Type
 
union  QSPI_BAUD_Type
 
union  QSPI_RXDATA_Type
 
union  QSPI_TXDATA_Type
 
union  QSPI_INTENCLR_Type
 
union  QSPI_INTENSET_Type
 
union  QSPI_INTFLAG_Type
 
union  QSPI_STATUS_Type
 
union  QSPI_INSTRADDR_Type
 
union  QSPI_INSTRCTRL_Type
 
union  QSPI_INSTRFRAME_Type
 
union  QSPI_SCRAMBCTRL_Type
 
union  QSPI_SCRAMBKEY_Type
 
struct  Qspi
 QSPI APB hardware registers. More...
 

Macros

#define QSPI_U2008
 
#define REV_QSPI   0x163
 
#define QSPI_CTRLA_OFFSET   0x00
 (QSPI_CTRLA offset) Control A
 
#define QSPI_CTRLA_RESETVALUE   _U_(0x00000000)
 (QSPI_CTRLA reset_value) Control A
 
#define QSPI_CTRLA_SWRST_Pos   0
 (QSPI_CTRLA) Software Reset
 
#define QSPI_CTRLA_SWRST   (_U_(0x1) << QSPI_CTRLA_SWRST_Pos)
 
#define QSPI_CTRLA_ENABLE_Pos   1
 (QSPI_CTRLA) Enable
 
#define QSPI_CTRLA_ENABLE   (_U_(0x1) << QSPI_CTRLA_ENABLE_Pos)
 
#define QSPI_CTRLA_LASTXFER_Pos   24
 (QSPI_CTRLA) Last Transfer
 
#define QSPI_CTRLA_LASTXFER   (_U_(0x1) << QSPI_CTRLA_LASTXFER_Pos)
 
#define QSPI_CTRLA_MASK   _U_(0x01000003)
 (QSPI_CTRLA) MASK Register
 
#define QSPI_CTRLB_OFFSET   0x04
 (QSPI_CTRLB offset) Control B
 
#define QSPI_CTRLB_RESETVALUE   _U_(0x00000000)
 (QSPI_CTRLB reset_value) Control B
 
#define QSPI_CTRLB_MODE_Pos   0
 (QSPI_CTRLB) Serial Memory Mode
 
#define QSPI_CTRLB_MODE   (_U_(0x1) << QSPI_CTRLB_MODE_Pos)
 
#define QSPI_CTRLB_MODE_SPI_Val   _U_(0x0)
 (QSPI_CTRLB) SPI operating mode
 
#define QSPI_CTRLB_MODE_MEMORY_Val   _U_(0x1)
 (QSPI_CTRLB) Serial Memory operating mode
 
#define QSPI_CTRLB_MODE_SPI   (QSPI_CTRLB_MODE_SPI_Val << QSPI_CTRLB_MODE_Pos)
 
#define QSPI_CTRLB_MODE_MEMORY   (QSPI_CTRLB_MODE_MEMORY_Val << QSPI_CTRLB_MODE_Pos)
 
#define QSPI_CTRLB_LOOPEN_Pos   1
 (QSPI_CTRLB) Local Loopback Enable
 
#define QSPI_CTRLB_LOOPEN   (_U_(0x1) << QSPI_CTRLB_LOOPEN_Pos)
 
#define QSPI_CTRLB_WDRBT_Pos   2
 (QSPI_CTRLB) Wait Data Read Before Transfer
 
#define QSPI_CTRLB_WDRBT   (_U_(0x1) << QSPI_CTRLB_WDRBT_Pos)
 
#define QSPI_CTRLB_SMEMREG_Pos   3
 (QSPI_CTRLB) Serial Memory reg
 
#define QSPI_CTRLB_SMEMREG   (_U_(0x1) << QSPI_CTRLB_SMEMREG_Pos)
 
#define QSPI_CTRLB_CSMODE_Pos   4
 (QSPI_CTRLB) Chip Select Mode
 
#define QSPI_CTRLB_CSMODE_Msk   (_U_(0x3) << QSPI_CTRLB_CSMODE_Pos)
 
#define QSPI_CTRLB_CSMODE(value)   (QSPI_CTRLB_CSMODE_Msk & ((value) << QSPI_CTRLB_CSMODE_Pos))
 
#define QSPI_CTRLB_CSMODE_NORELOAD_Val   _U_(0x0)
 (QSPI_CTRLB) The chip select is deasserted if TD has not been reloaded before the end of the current transfer.
 
#define QSPI_CTRLB_CSMODE_LASTXFER_Val   _U_(0x1)
 (QSPI_CTRLB) The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred.
 
#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val   _U_(0x2)
 (QSPI_CTRLB) The chip select is deasserted systematically after each transfer.
 
#define QSPI_CTRLB_CSMODE_NORELOAD   (QSPI_CTRLB_CSMODE_NORELOAD_Val << QSPI_CTRLB_CSMODE_Pos)
 
#define QSPI_CTRLB_CSMODE_LASTXFER   (QSPI_CTRLB_CSMODE_LASTXFER_Val << QSPI_CTRLB_CSMODE_Pos)
 
#define QSPI_CTRLB_CSMODE_SYSTEMATICALLY   (QSPI_CTRLB_CSMODE_SYSTEMATICALLY_Val << QSPI_CTRLB_CSMODE_Pos)
 
#define QSPI_CTRLB_DATALEN_Pos   8
 (QSPI_CTRLB) Data Length
 
#define QSPI_CTRLB_DATALEN_Msk   (_U_(0xF) << QSPI_CTRLB_DATALEN_Pos)
 
#define QSPI_CTRLB_DATALEN(value)   (QSPI_CTRLB_DATALEN_Msk & ((value) << QSPI_CTRLB_DATALEN_Pos))
 
#define QSPI_CTRLB_DATALEN_8BITS_Val   _U_(0x0)
 (QSPI_CTRLB) 8-bits transfer
 
#define QSPI_CTRLB_DATALEN_9BITS_Val   _U_(0x1)
 (QSPI_CTRLB) 9 bits transfer
 
#define QSPI_CTRLB_DATALEN_10BITS_Val   _U_(0x2)
 (QSPI_CTRLB) 10-bits transfer
 
#define QSPI_CTRLB_DATALEN_11BITS_Val   _U_(0x3)
 (QSPI_CTRLB) 11-bits transfer
 
#define QSPI_CTRLB_DATALEN_12BITS_Val   _U_(0x4)
 (QSPI_CTRLB) 12-bits transfer
 
#define QSPI_CTRLB_DATALEN_13BITS_Val   _U_(0x5)
 (QSPI_CTRLB) 13-bits transfer
 
#define QSPI_CTRLB_DATALEN_14BITS_Val   _U_(0x6)
 (QSPI_CTRLB) 14-bits transfer
 
#define QSPI_CTRLB_DATALEN_15BITS_Val   _U_(0x7)
 (QSPI_CTRLB) 15-bits transfer
 
#define QSPI_CTRLB_DATALEN_16BITS_Val   _U_(0x8)
 (QSPI_CTRLB) 16-bits transfer
 
#define QSPI_CTRLB_DATALEN_8BITS   (QSPI_CTRLB_DATALEN_8BITS_Val << QSPI_CTRLB_DATALEN_Pos)
 
#define QSPI_CTRLB_DATALEN_9BITS   (QSPI_CTRLB_DATALEN_9BITS_Val << QSPI_CTRLB_DATALEN_Pos)
 
#define QSPI_CTRLB_DATALEN_10BITS   (QSPI_CTRLB_DATALEN_10BITS_Val << QSPI_CTRLB_DATALEN_Pos)
 
#define QSPI_CTRLB_DATALEN_11BITS   (QSPI_CTRLB_DATALEN_11BITS_Val << QSPI_CTRLB_DATALEN_Pos)
 
#define QSPI_CTRLB_DATALEN_12BITS   (QSPI_CTRLB_DATALEN_12BITS_Val << QSPI_CTRLB_DATALEN_Pos)
 
#define QSPI_CTRLB_DATALEN_13BITS   (QSPI_CTRLB_DATALEN_13BITS_Val << QSPI_CTRLB_DATALEN_Pos)
 
#define QSPI_CTRLB_DATALEN_14BITS   (QSPI_CTRLB_DATALEN_14BITS_Val << QSPI_CTRLB_DATALEN_Pos)
 
#define QSPI_CTRLB_DATALEN_15BITS   (QSPI_CTRLB_DATALEN_15BITS_Val << QSPI_CTRLB_DATALEN_Pos)
 
#define QSPI_CTRLB_DATALEN_16BITS   (QSPI_CTRLB_DATALEN_16BITS_Val << QSPI_CTRLB_DATALEN_Pos)
 
#define QSPI_CTRLB_DLYBCT_Pos   16
 (QSPI_CTRLB) Delay Between Consecutive Transfers
 
#define QSPI_CTRLB_DLYBCT_Msk   (_U_(0xFF) << QSPI_CTRLB_DLYBCT_Pos)
 
#define QSPI_CTRLB_DLYBCT(value)   (QSPI_CTRLB_DLYBCT_Msk & ((value) << QSPI_CTRLB_DLYBCT_Pos))
 
#define QSPI_CTRLB_DLYCS_Pos   24
 (QSPI_CTRLB) Minimum Inactive CS Delay
 
#define QSPI_CTRLB_DLYCS_Msk   (_U_(0xFF) << QSPI_CTRLB_DLYCS_Pos)
 
#define QSPI_CTRLB_DLYCS(value)   (QSPI_CTRLB_DLYCS_Msk & ((value) << QSPI_CTRLB_DLYCS_Pos))
 
#define QSPI_CTRLB_MASK   _U_(0xFFFF0F3F)
 (QSPI_CTRLB) MASK Register
 
#define QSPI_BAUD_OFFSET   0x08
 (QSPI_BAUD offset) Baud Rate
 
#define QSPI_BAUD_RESETVALUE   _U_(0x00000000)
 (QSPI_BAUD reset_value) Baud Rate
 
#define QSPI_BAUD_CPOL_Pos   0
 (QSPI_BAUD) Clock Polarity
 
#define QSPI_BAUD_CPOL   (_U_(0x1) << QSPI_BAUD_CPOL_Pos)
 
#define QSPI_BAUD_CPHA_Pos   1
 (QSPI_BAUD) Clock Phase
 
#define QSPI_BAUD_CPHA   (_U_(0x1) << QSPI_BAUD_CPHA_Pos)
 
#define QSPI_BAUD_BAUD_Pos   8
 (QSPI_BAUD) Serial Clock Baud Rate
 
#define QSPI_BAUD_BAUD_Msk   (_U_(0xFF) << QSPI_BAUD_BAUD_Pos)
 
#define QSPI_BAUD_BAUD(value)   (QSPI_BAUD_BAUD_Msk & ((value) << QSPI_BAUD_BAUD_Pos))
 
#define QSPI_BAUD_DLYBS_Pos   16
 (QSPI_BAUD) Delay Before SCK
 
#define QSPI_BAUD_DLYBS_Msk   (_U_(0xFF) << QSPI_BAUD_DLYBS_Pos)
 
#define QSPI_BAUD_DLYBS(value)   (QSPI_BAUD_DLYBS_Msk & ((value) << QSPI_BAUD_DLYBS_Pos))
 
#define QSPI_BAUD_MASK   _U_(0x00FFFF03)
 (QSPI_BAUD) MASK Register
 
#define QSPI_RXDATA_OFFSET   0x0C
 (QSPI_RXDATA offset) Receive Data
 
#define QSPI_RXDATA_RESETVALUE   _U_(0x00000000)
 (QSPI_RXDATA reset_value) Receive Data
 
#define QSPI_RXDATA_DATA_Pos   0
 (QSPI_RXDATA) Receive Data
 
#define QSPI_RXDATA_DATA_Msk   (_U_(0xFFFF) << QSPI_RXDATA_DATA_Pos)
 
#define QSPI_RXDATA_DATA(value)   (QSPI_RXDATA_DATA_Msk & ((value) << QSPI_RXDATA_DATA_Pos))
 
#define QSPI_RXDATA_MASK   _U_(0x0000FFFF)
 (QSPI_RXDATA) MASK Register
 
#define QSPI_TXDATA_OFFSET   0x10
 (QSPI_TXDATA offset) Transmit Data
 
#define QSPI_TXDATA_RESETVALUE   _U_(0x00000000)
 (QSPI_TXDATA reset_value) Transmit Data
 
#define QSPI_TXDATA_DATA_Pos   0
 (QSPI_TXDATA) Transmit Data
 
#define QSPI_TXDATA_DATA_Msk   (_U_(0xFFFF) << QSPI_TXDATA_DATA_Pos)
 
#define QSPI_TXDATA_DATA(value)   (QSPI_TXDATA_DATA_Msk & ((value) << QSPI_TXDATA_DATA_Pos))
 
#define QSPI_TXDATA_MASK   _U_(0x0000FFFF)
 (QSPI_TXDATA) MASK Register
 
#define QSPI_INTENCLR_OFFSET   0x14
 (QSPI_INTENCLR offset) Interrupt Enable Clear
 
#define QSPI_INTENCLR_RESETVALUE   _U_(0x00000000)
 (QSPI_INTENCLR reset_value) Interrupt Enable Clear
 
#define QSPI_INTENCLR_RXC_Pos   0
 (QSPI_INTENCLR) Receive Data Register Full Interrupt Disable
 
#define QSPI_INTENCLR_RXC   (_U_(0x1) << QSPI_INTENCLR_RXC_Pos)
 
#define QSPI_INTENCLR_DRE_Pos   1
 (QSPI_INTENCLR) Transmit Data Register Empty Interrupt Disable
 
#define QSPI_INTENCLR_DRE   (_U_(0x1) << QSPI_INTENCLR_DRE_Pos)
 
#define QSPI_INTENCLR_TXC_Pos   2
 (QSPI_INTENCLR) Transmission Complete Interrupt Disable
 
#define QSPI_INTENCLR_TXC   (_U_(0x1) << QSPI_INTENCLR_TXC_Pos)
 
#define QSPI_INTENCLR_ERROR_Pos   3
 (QSPI_INTENCLR) Overrun Error Interrupt Disable
 
#define QSPI_INTENCLR_ERROR   (_U_(0x1) << QSPI_INTENCLR_ERROR_Pos)
 
#define QSPI_INTENCLR_CSRISE_Pos   8
 (QSPI_INTENCLR) Chip Select Rise Interrupt Disable
 
#define QSPI_INTENCLR_CSRISE   (_U_(0x1) << QSPI_INTENCLR_CSRISE_Pos)
 
#define QSPI_INTENCLR_INSTREND_Pos   10
 (QSPI_INTENCLR) Instruction End Interrupt Disable
 
#define QSPI_INTENCLR_INSTREND   (_U_(0x1) << QSPI_INTENCLR_INSTREND_Pos)
 
#define QSPI_INTENCLR_MASK   _U_(0x0000050F)
 (QSPI_INTENCLR) MASK Register
 
#define QSPI_INTENSET_OFFSET   0x18
 (QSPI_INTENSET offset) Interrupt Enable Set
 
#define QSPI_INTENSET_RESETVALUE   _U_(0x00000000)
 (QSPI_INTENSET reset_value) Interrupt Enable Set
 
#define QSPI_INTENSET_RXC_Pos   0
 (QSPI_INTENSET) Receive Data Register Full Interrupt Enable
 
#define QSPI_INTENSET_RXC   (_U_(0x1) << QSPI_INTENSET_RXC_Pos)
 
#define QSPI_INTENSET_DRE_Pos   1
 (QSPI_INTENSET) Transmit Data Register Empty Interrupt Enable
 
#define QSPI_INTENSET_DRE   (_U_(0x1) << QSPI_INTENSET_DRE_Pos)
 
#define QSPI_INTENSET_TXC_Pos   2
 (QSPI_INTENSET) Transmission Complete Interrupt Enable
 
#define QSPI_INTENSET_TXC   (_U_(0x1) << QSPI_INTENSET_TXC_Pos)
 
#define QSPI_INTENSET_ERROR_Pos   3
 (QSPI_INTENSET) Overrun Error Interrupt Enable
 
#define QSPI_INTENSET_ERROR   (_U_(0x1) << QSPI_INTENSET_ERROR_Pos)
 
#define QSPI_INTENSET_CSRISE_Pos   8
 (QSPI_INTENSET) Chip Select Rise Interrupt Enable
 
#define QSPI_INTENSET_CSRISE   (_U_(0x1) << QSPI_INTENSET_CSRISE_Pos)
 
#define QSPI_INTENSET_INSTREND_Pos   10
 (QSPI_INTENSET) Instruction End Interrupt Enable
 
#define QSPI_INTENSET_INSTREND   (_U_(0x1) << QSPI_INTENSET_INSTREND_Pos)
 
#define QSPI_INTENSET_MASK   _U_(0x0000050F)
 (QSPI_INTENSET) MASK Register
 
#define QSPI_INTFLAG_OFFSET   0x1C
 (QSPI_INTFLAG offset) Interrupt Flag Status and Clear
 
#define QSPI_INTFLAG_RESETVALUE   _U_(0x00000000)
 (QSPI_INTFLAG reset_value) Interrupt Flag Status and Clear
 
#define QSPI_INTFLAG_RXC_Pos   0
 (QSPI_INTFLAG) Receive Data Register Full
 
#define QSPI_INTFLAG_RXC   (_U_(0x1) << QSPI_INTFLAG_RXC_Pos)
 
#define QSPI_INTFLAG_DRE_Pos   1
 (QSPI_INTFLAG) Transmit Data Register Empty
 
#define QSPI_INTFLAG_DRE   (_U_(0x1) << QSPI_INTFLAG_DRE_Pos)
 
#define QSPI_INTFLAG_TXC_Pos   2
 (QSPI_INTFLAG) Transmission Complete
 
#define QSPI_INTFLAG_TXC   (_U_(0x1) << QSPI_INTFLAG_TXC_Pos)
 
#define QSPI_INTFLAG_ERROR_Pos   3
 (QSPI_INTFLAG) Overrun Error
 
#define QSPI_INTFLAG_ERROR   (_U_(0x1) << QSPI_INTFLAG_ERROR_Pos)
 
#define QSPI_INTFLAG_CSRISE_Pos   8
 (QSPI_INTFLAG) Chip Select Rise
 
#define QSPI_INTFLAG_CSRISE   (_U_(0x1) << QSPI_INTFLAG_CSRISE_Pos)
 
#define QSPI_INTFLAG_INSTREND_Pos   10
 (QSPI_INTFLAG) Instruction End
 
#define QSPI_INTFLAG_INSTREND   (_U_(0x1) << QSPI_INTFLAG_INSTREND_Pos)
 
#define QSPI_INTFLAG_MASK   _U_(0x0000050F)
 (QSPI_INTFLAG) MASK Register
 
#define QSPI_STATUS_OFFSET   0x20
 (QSPI_STATUS offset) Status Register
 
#define QSPI_STATUS_RESETVALUE   _U_(0x00000200)
 (QSPI_STATUS reset_value) Status Register
 
#define QSPI_STATUS_ENABLE_Pos   1
 (QSPI_STATUS) Enable
 
#define QSPI_STATUS_ENABLE   (_U_(0x1) << QSPI_STATUS_ENABLE_Pos)
 
#define QSPI_STATUS_CSSTATUS_Pos   9
 (QSPI_STATUS) Chip Select
 
#define QSPI_STATUS_CSSTATUS   (_U_(0x1) << QSPI_STATUS_CSSTATUS_Pos)
 
#define QSPI_STATUS_MASK   _U_(0x00000202)
 (QSPI_STATUS) MASK Register
 
#define QSPI_INSTRADDR_OFFSET   0x30
 (QSPI_INSTRADDR offset) Instruction Address
 
#define QSPI_INSTRADDR_RESETVALUE   _U_(0x00000000)
 (QSPI_INSTRADDR reset_value) Instruction Address
 
#define QSPI_INSTRADDR_ADDR_Pos   0
 (QSPI_INSTRADDR) Instruction Address
 
#define QSPI_INSTRADDR_ADDR_Msk   (_U_(0xFFFFFFFF) << QSPI_INSTRADDR_ADDR_Pos)
 
#define QSPI_INSTRADDR_ADDR(value)   (QSPI_INSTRADDR_ADDR_Msk & ((value) << QSPI_INSTRADDR_ADDR_Pos))
 
#define QSPI_INSTRADDR_MASK   _U_(0xFFFFFFFF)
 (QSPI_INSTRADDR) MASK Register
 
#define QSPI_INSTRCTRL_OFFSET   0x34
 (QSPI_INSTRCTRL offset) Instruction Code
 
#define QSPI_INSTRCTRL_RESETVALUE   _U_(0x00000000)
 (QSPI_INSTRCTRL reset_value) Instruction Code
 
#define QSPI_INSTRCTRL_INSTR_Pos   0
 (QSPI_INSTRCTRL) Instruction Code
 
#define QSPI_INSTRCTRL_INSTR_Msk   (_U_(0xFF) << QSPI_INSTRCTRL_INSTR_Pos)
 
#define QSPI_INSTRCTRL_INSTR(value)   (QSPI_INSTRCTRL_INSTR_Msk & ((value) << QSPI_INSTRCTRL_INSTR_Pos))
 
#define QSPI_INSTRCTRL_OPTCODE_Pos   16
 (QSPI_INSTRCTRL) Option Code
 
#define QSPI_INSTRCTRL_OPTCODE_Msk   (_U_(0xFF) << QSPI_INSTRCTRL_OPTCODE_Pos)
 
#define QSPI_INSTRCTRL_OPTCODE(value)   (QSPI_INSTRCTRL_OPTCODE_Msk & ((value) << QSPI_INSTRCTRL_OPTCODE_Pos))
 
#define QSPI_INSTRCTRL_MASK   _U_(0x00FF00FF)
 (QSPI_INSTRCTRL) MASK Register
 
#define QSPI_INSTRFRAME_OFFSET   0x38
 (QSPI_INSTRFRAME offset) Instruction Frame
 
#define QSPI_INSTRFRAME_RESETVALUE   _U_(0x00000000)
 (QSPI_INSTRFRAME reset_value) Instruction Frame
 
#define QSPI_INSTRFRAME_WIDTH_Pos   0
 (QSPI_INSTRFRAME) Instruction Code, Address, Option Code and Data Width
 
#define QSPI_INSTRFRAME_WIDTH_Msk   (_U_(0x7) << QSPI_INSTRFRAME_WIDTH_Pos)
 
#define QSPI_INSTRFRAME_WIDTH(value)   (QSPI_INSTRFRAME_WIDTH_Msk & ((value) << QSPI_INSTRFRAME_WIDTH_Pos))
 
#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val   _U_(0x0)
 (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI
 
#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val   _U_(0x1)
 (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI
 
#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val   _U_(0x2)
 (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI
 
#define QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val   _U_(0x3)
 (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI
 
#define QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val   _U_(0x4)
 (QSPI_INSTRFRAME) Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI
 
#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val   _U_(0x5)
 (QSPI_INSTRFRAME) Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI
 
#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val   _U_(0x6)
 (QSPI_INSTRFRAME) Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI
 
#define QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI   (QSPI_INSTRFRAME_WIDTH_SINGLE_BIT_SPI_Val << QSPI_INSTRFRAME_WIDTH_Pos)
 
#define QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT   (QSPI_INSTRFRAME_WIDTH_DUAL_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
 
#define QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT   (QSPI_INSTRFRAME_WIDTH_QUAD_OUTPUT_Val << QSPI_INSTRFRAME_WIDTH_Pos)
 
#define QSPI_INSTRFRAME_WIDTH_DUAL_IO   (QSPI_INSTRFRAME_WIDTH_DUAL_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
 
#define QSPI_INSTRFRAME_WIDTH_QUAD_IO   (QSPI_INSTRFRAME_WIDTH_QUAD_IO_Val << QSPI_INSTRFRAME_WIDTH_Pos)
 
#define QSPI_INSTRFRAME_WIDTH_DUAL_CMD   (QSPI_INSTRFRAME_WIDTH_DUAL_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
 
#define QSPI_INSTRFRAME_WIDTH_QUAD_CMD   (QSPI_INSTRFRAME_WIDTH_QUAD_CMD_Val << QSPI_INSTRFRAME_WIDTH_Pos)
 
#define QSPI_INSTRFRAME_INSTREN_Pos   4
 (QSPI_INSTRFRAME) Instruction Enable
 
#define QSPI_INSTRFRAME_INSTREN   (_U_(0x1) << QSPI_INSTRFRAME_INSTREN_Pos)
 
#define QSPI_INSTRFRAME_ADDREN_Pos   5
 (QSPI_INSTRFRAME) Address Enable
 
#define QSPI_INSTRFRAME_ADDREN   (_U_(0x1) << QSPI_INSTRFRAME_ADDREN_Pos)
 
#define QSPI_INSTRFRAME_OPTCODEEN_Pos   6
 (QSPI_INSTRFRAME) Option Enable
 
#define QSPI_INSTRFRAME_OPTCODEEN   (_U_(0x1) << QSPI_INSTRFRAME_OPTCODEEN_Pos)
 
#define QSPI_INSTRFRAME_DATAEN_Pos   7
 (QSPI_INSTRFRAME) Data Enable
 
#define QSPI_INSTRFRAME_DATAEN   (_U_(0x1) << QSPI_INSTRFRAME_DATAEN_Pos)
 
#define QSPI_INSTRFRAME_OPTCODELEN_Pos   8
 (QSPI_INSTRFRAME) Option Code Length
 
#define QSPI_INSTRFRAME_OPTCODELEN_Msk   (_U_(0x3) << QSPI_INSTRFRAME_OPTCODELEN_Pos)
 
#define QSPI_INSTRFRAME_OPTCODELEN(value)   (QSPI_INSTRFRAME_OPTCODELEN_Msk & ((value) << QSPI_INSTRFRAME_OPTCODELEN_Pos))
 
#define QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val   _U_(0x0)
 (QSPI_INSTRFRAME) 1-bit length option code
 
#define QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val   _U_(0x1)
 (QSPI_INSTRFRAME) 2-bits length option code
 
#define QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val   _U_(0x2)
 (QSPI_INSTRFRAME) 4-bits length option code
 
#define QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val   _U_(0x3)
 (QSPI_INSTRFRAME) 8-bits length option code
 
#define QSPI_INSTRFRAME_OPTCODELEN_1BIT   (QSPI_INSTRFRAME_OPTCODELEN_1BIT_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
 
#define QSPI_INSTRFRAME_OPTCODELEN_2BITS   (QSPI_INSTRFRAME_OPTCODELEN_2BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
 
#define QSPI_INSTRFRAME_OPTCODELEN_4BITS   (QSPI_INSTRFRAME_OPTCODELEN_4BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
 
#define QSPI_INSTRFRAME_OPTCODELEN_8BITS   (QSPI_INSTRFRAME_OPTCODELEN_8BITS_Val << QSPI_INSTRFRAME_OPTCODELEN_Pos)
 
#define QSPI_INSTRFRAME_ADDRLEN_Pos   10
 (QSPI_INSTRFRAME) Address Length
 
#define QSPI_INSTRFRAME_ADDRLEN   (_U_(0x1) << QSPI_INSTRFRAME_ADDRLEN_Pos)
 
#define QSPI_INSTRFRAME_ADDRLEN_24BITS_Val   _U_(0x0)
 (QSPI_INSTRFRAME) 24-bits address length
 
#define QSPI_INSTRFRAME_ADDRLEN_32BITS_Val   _U_(0x1)
 (QSPI_INSTRFRAME) 32-bits address length
 
#define QSPI_INSTRFRAME_ADDRLEN_24BITS   (QSPI_INSTRFRAME_ADDRLEN_24BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
 
#define QSPI_INSTRFRAME_ADDRLEN_32BITS   (QSPI_INSTRFRAME_ADDRLEN_32BITS_Val << QSPI_INSTRFRAME_ADDRLEN_Pos)
 
#define QSPI_INSTRFRAME_TFRTYPE_Pos   12
 (QSPI_INSTRFRAME) Data Transfer Type
 
#define QSPI_INSTRFRAME_TFRTYPE_Msk   (_U_(0x3) << QSPI_INSTRFRAME_TFRTYPE_Pos)
 
#define QSPI_INSTRFRAME_TFRTYPE(value)   (QSPI_INSTRFRAME_TFRTYPE_Msk & ((value) << QSPI_INSTRFRAME_TFRTYPE_Pos))
 
#define QSPI_INSTRFRAME_TFRTYPE_READ_Val   _U_(0x0)
 (QSPI_INSTRFRAME) Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible.
 
#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val   _U_(0x1)
 (QSPI_INSTRFRAME) Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible.
 
#define QSPI_INSTRFRAME_TFRTYPE_WRITE_Val   _U_(0x2)
 (QSPI_INSTRFRAME) Write transfer into the serial memory.Scrambling is not performed.
 
#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val   _U_(0x3)
 (QSPI_INSTRFRAME) Write data transfer into the serial memory.If enabled, scrambling is performed.
 
#define QSPI_INSTRFRAME_TFRTYPE_READ   (QSPI_INSTRFRAME_TFRTYPE_READ_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
 
#define QSPI_INSTRFRAME_TFRTYPE_READMEMORY   (QSPI_INSTRFRAME_TFRTYPE_READMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
 
#define QSPI_INSTRFRAME_TFRTYPE_WRITE   (QSPI_INSTRFRAME_TFRTYPE_WRITE_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
 
#define QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY   (QSPI_INSTRFRAME_TFRTYPE_WRITEMEMORY_Val << QSPI_INSTRFRAME_TFRTYPE_Pos)
 
#define QSPI_INSTRFRAME_CRMODE_Pos   14
 (QSPI_INSTRFRAME) Continuous Read Mode
 
#define QSPI_INSTRFRAME_CRMODE   (_U_(0x1) << QSPI_INSTRFRAME_CRMODE_Pos)
 
#define QSPI_INSTRFRAME_DDREN_Pos   15
 (QSPI_INSTRFRAME) Double Data Rate Enable
 
#define QSPI_INSTRFRAME_DDREN   (_U_(0x1) << QSPI_INSTRFRAME_DDREN_Pos)
 
#define QSPI_INSTRFRAME_DUMMYLEN_Pos   16
 (QSPI_INSTRFRAME) Dummy Cycles Length
 
#define QSPI_INSTRFRAME_DUMMYLEN_Msk   (_U_(0x1F) << QSPI_INSTRFRAME_DUMMYLEN_Pos)
 
#define QSPI_INSTRFRAME_DUMMYLEN(value)   (QSPI_INSTRFRAME_DUMMYLEN_Msk & ((value) << QSPI_INSTRFRAME_DUMMYLEN_Pos))
 
#define QSPI_INSTRFRAME_MASK   _U_(0x001FF7F7)
 (QSPI_INSTRFRAME) MASK Register
 
#define QSPI_SCRAMBCTRL_OFFSET   0x40
 (QSPI_SCRAMBCTRL offset) Scrambling Mode
 
#define QSPI_SCRAMBCTRL_RESETVALUE   _U_(0x00000000)
 (QSPI_SCRAMBCTRL reset_value) Scrambling Mode
 
#define QSPI_SCRAMBCTRL_ENABLE_Pos   0
 (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Enable
 
#define QSPI_SCRAMBCTRL_ENABLE   (_U_(0x1) << QSPI_SCRAMBCTRL_ENABLE_Pos)
 
#define QSPI_SCRAMBCTRL_RANDOMDIS_Pos   1
 (QSPI_SCRAMBCTRL) Scrambling/Unscrambling Random Value Disable
 
#define QSPI_SCRAMBCTRL_RANDOMDIS   (_U_(0x1) << QSPI_SCRAMBCTRL_RANDOMDIS_Pos)
 
#define QSPI_SCRAMBCTRL_MASK   _U_(0x00000003)
 (QSPI_SCRAMBCTRL) MASK Register
 
#define QSPI_SCRAMBKEY_OFFSET   0x44
 (QSPI_SCRAMBKEY offset) Scrambling Key
 
#define QSPI_SCRAMBKEY_RESETVALUE   _U_(0x00000000)
 (QSPI_SCRAMBKEY reset_value) Scrambling Key
 
#define QSPI_SCRAMBKEY_KEY_Pos   0
 (QSPI_SCRAMBKEY) Scrambling User Key
 
#define QSPI_SCRAMBKEY_KEY_Msk   (_U_(0xFFFFFFFF) << QSPI_SCRAMBKEY_KEY_Pos)
 
#define QSPI_SCRAMBKEY_KEY(value)   (QSPI_SCRAMBKEY_KEY_Msk & ((value) << QSPI_SCRAMBKEY_KEY_Pos))
 
#define QSPI_SCRAMBKEY_MASK   _U_(0xFFFFFFFF)
 (QSPI_SCRAMBKEY) MASK Register
 

Detailed Description

Component description for QSPI.

Copyright (c) 2019 Microchip Technology Inc.

\asf_license_start

Definition in file qspi.h.