SAME54P20A Test Project
Data Structures | Macros
picop.h File Reference

Component description for PICOP. More...

Go to the source code of this file.

Data Structures

union  PICOP_ID_Type
 
union  PICOP_CONFIG_Type
 
union  PICOP_CTRL_Type
 
union  PICOP_CMD_Type
 
union  PICOP_PC_Type
 
union  PICOP_HF_Type
 
union  PICOP_HFCTRL_Type
 
union  PICOP_HFSETCLR0_Type
 
union  PICOP_HFSETCLR1_Type
 
union  PICOP_OCDCONFIG_Type
 
union  PICOP_OCDCONTROL_Type
 
union  PICOP_OCDSTATUS_Type
 
union  PICOP_OCDPC_Type
 
union  PICOP_OCDFEAT_Type
 
union  PICOP_OCDCCNT_Type
 
union  PICOP_OCDBPGEN_Type
 
union  PICOP_R3R0_Type
 
union  PICOP_R7R4_Type
 
union  PICOP_R11R8_Type
 
union  PICOP_R15R12_Type
 
union  PICOP_R19R16_Type
 
union  PICOP_R23R20_Type
 
union  PICOP_R27R24_Type
 
union  PICOP_R31R28_Type
 
union  PICOP_S1S0_Type
 
union  PICOP_S3S2_Type
 
union  PICOP_S5S4_Type
 
union  PICOP_S11S10_Type
 
union  PICOP_LINK_Type
 
union  PICOP_SP_Type
 
union  PICOP_MMUFLASH_Type
 
union  PICOP_MMU0_Type
 
union  PICOP_MMU1_Type
 
union  PICOP_MMUCTRL_Type
 
union  PICOP_ICACHE_Type
 
union  PICOP_ICACHELRU_Type
 
union  PICOP_QOSCTRL_Type
 
struct  Picop
 PICOP hardware registers. More...
 

Macros

#define PICOP_U2232
 
#define REV_PICOP   0x200
 
#define PICOP_ID_OFFSET   0x000
 (PICOP_ID offset) ID n
 
#define PICOP_ID_RESETVALUE   0x00000000ul
 (PICOP_ID reset_value) ID n
 
#define PICOP_ID_ID_Pos   0
 (PICOP_ID) ID String 0
 
#define PICOP_ID_ID_Msk   (0xFFFFFFFFul << PICOP_ID_ID_Pos)
 
#define PICOP_ID_ID(value)   (PICOP_ID_ID_Msk & ((value) << PICOP_ID_ID_Pos))
 
#define PICOP_ID_MASK   0xFFFFFFFFul
 (PICOP_ID) MASK Register
 
#define PICOP_CONFIG_OFFSET   0x020
 (PICOP_CONFIG offset) Configuration
 
#define PICOP_CONFIG_RESETVALUE   0x00000000ul
 (PICOP_CONFIG reset_value) Configuration
 
#define PICOP_CONFIG_ISA_Pos   0
 (PICOP_CONFIG) Instruction Set Architecture
 
#define PICOP_CONFIG_ISA_Msk   (0x3ul << PICOP_CONFIG_ISA_Pos)
 
#define PICOP_CONFIG_ISA(value)   (PICOP_CONFIG_ISA_Msk & ((value) << PICOP_CONFIG_ISA_Pos))
 
#define PICOP_CONFIG_ISA_AVR8_Val   0x0ul
 (PICOP_CONFIG) AVR8 ISA, AVR8SP=1
 
#define PICOP_CONFIG_ISA_AVR16C_Val   0x1ul
 (PICOP_CONFIG) AVR16 ISA fully compatible with AVR8 ISA, AVR8SP=1
 
#define PICOP_CONFIG_ISA_AVR16E_Val   0x2ul
 (PICOP_CONFIG) AVR16 ISA extended, AVR8SP=1
 
#define PICOP_CONFIG_ISA_AVR16_Val   0x3ul
 (PICOP_CONFIG) AVR16 ISA extended, AVR8SP=0
 
#define PICOP_CONFIG_ISA_AVR8   (PICOP_CONFIG_ISA_AVR8_Val << PICOP_CONFIG_ISA_Pos)
 
#define PICOP_CONFIG_ISA_AVR16C   (PICOP_CONFIG_ISA_AVR16C_Val << PICOP_CONFIG_ISA_Pos)
 
#define PICOP_CONFIG_ISA_AVR16E   (PICOP_CONFIG_ISA_AVR16E_Val << PICOP_CONFIG_ISA_Pos)
 
#define PICOP_CONFIG_ISA_AVR16   (PICOP_CONFIG_ISA_AVR16_Val << PICOP_CONFIG_ISA_Pos)
 
#define PICOP_CONFIG_ASP_Pos   2
 (PICOP_CONFIG) Aligned Stack Pointer
 
#define PICOP_CONFIG_ASP   (0x1ul << PICOP_CONFIG_ASP_Pos)
 
#define PICOP_CONFIG_MARRET_Pos   3
 (PICOP_CONFIG) Misaligned implicit long return register (GCC compatibility)
 
#define PICOP_CONFIG_MARRET   (0x1ul << PICOP_CONFIG_MARRET_Pos)
 
#define PICOP_CONFIG_RRET_Pos   4
 (PICOP_CONFIG) Implicit return word register
 
#define PICOP_CONFIG_RRET_Msk   (0xFul << PICOP_CONFIG_RRET_Pos)
 
#define PICOP_CONFIG_RRET(value)   (PICOP_CONFIG_RRET_Msk & ((value) << PICOP_CONFIG_RRET_Pos))
 
#define PICOP_CONFIG_PCEXEN_Pos   8
 (PICOP_CONFIG) PC_EX register enabled for reduced interrupt latency
 
#define PICOP_CONFIG_PCEXEN   (0x1ul << PICOP_CONFIG_PCEXEN_Pos)
 
#define PICOP_CONFIG_MASK   0x000001FFul
 (PICOP_CONFIG) MASK Register
 
#define PICOP_CTRL_OFFSET   0x024
 (PICOP_CTRL offset) Control
 
#define PICOP_CTRL_RESETVALUE   0x00000000ul
 (PICOP_CTRL reset_value) Control
 
#define PICOP_CTRL_MAPUEXCEPT_Pos   0
 (PICOP_CTRL) Enable exception for illegal access
 
#define PICOP_CTRL_MAPUEXCEPT   (0x1ul << PICOP_CTRL_MAPUEXCEPT_Pos)
 
#define PICOP_CTRL_WPICACHE_Pos   1
 (PICOP_CTRL) Write protect iCache
 
#define PICOP_CTRL_WPICACHE   (0x1ul << PICOP_CTRL_WPICACHE_Pos)
 
#define PICOP_CTRL_WPVEC_Pos   2
 (PICOP_CTRL) Write protect vectors
 
#define PICOP_CTRL_WPVEC_Msk   (0x3ul << PICOP_CTRL_WPVEC_Pos)
 
#define PICOP_CTRL_WPVEC(value)   (PICOP_CTRL_WPVEC_Msk & ((value) << PICOP_CTRL_WPVEC_Pos))
 
#define PICOP_CTRL_WPVEC_NONE_Val   0x0ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPVEC_RSTNMI_Val   0x1ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPVEC_NONE   (PICOP_CTRL_WPVEC_NONE_Val << PICOP_CTRL_WPVEC_Pos)
 
#define PICOP_CTRL_WPVEC_RSTNMI   (PICOP_CTRL_WPVEC_RSTNMI_Val << PICOP_CTRL_WPVEC_Pos)
 
#define PICOP_CTRL_WPCTX_Pos   4
 (PICOP_CTRL) Write protect contexts
 
#define PICOP_CTRL_WPCTX_Msk   (0x3ul << PICOP_CTRL_WPCTX_Pos)
 
#define PICOP_CTRL_WPCTX(value)   (PICOP_CTRL_WPCTX_Msk & ((value) << PICOP_CTRL_WPCTX_Pos))
 
#define PICOP_CTRL_WPCTX_NONE_Val   0x0ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCTX_CTX0_Val   0x1ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCTX_CTX01_Val   0x2ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCTX_CTX012_Val   0x3ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCTX_NONE   (PICOP_CTRL_WPCTX_NONE_Val << PICOP_CTRL_WPCTX_Pos)
 
#define PICOP_CTRL_WPCTX_CTX0   (PICOP_CTRL_WPCTX_CTX0_Val << PICOP_CTRL_WPCTX_Pos)
 
#define PICOP_CTRL_WPCTX_CTX01   (PICOP_CTRL_WPCTX_CTX01_Val << PICOP_CTRL_WPCTX_Pos)
 
#define PICOP_CTRL_WPCTX_CTX012   (PICOP_CTRL_WPCTX_CTX012_Val << PICOP_CTRL_WPCTX_Pos)
 
#define PICOP_CTRL_WPCODE_Pos   6
 (PICOP_CTRL) Write protect code
 
#define PICOP_CTRL_WPCODE_Msk   (0xFul << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE(value)   (PICOP_CTRL_WPCODE_Msk & ((value) << PICOP_CTRL_WPCODE_Pos))
 
#define PICOP_CTRL_WPCODE_NONE_Val   0x0ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_256B_Val   0x1ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_512B_Val   0x2ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_768B_Val   0x3ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_1024B_Val   0x4ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_1280B_Val   0x5ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_1536B_Val   0x6ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_1792B_Val   0x7ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_2048B_Val   0x8ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_2304B_Val   0x9ul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_2560B_Val   0xAul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_2816B_Val   0xBul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_3072B_Val   0xCul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_3328B_Val   0xDul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_3584B_Val   0xEul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_3840B_Val   0xFul
 (PICOP_CTRL)

 
#define PICOP_CTRL_WPCODE_NONE   (PICOP_CTRL_WPCODE_NONE_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_256B   (PICOP_CTRL_WPCODE_256B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_512B   (PICOP_CTRL_WPCODE_512B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_768B   (PICOP_CTRL_WPCODE_768B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_1024B   (PICOP_CTRL_WPCODE_1024B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_1280B   (PICOP_CTRL_WPCODE_1280B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_1536B   (PICOP_CTRL_WPCODE_1536B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_1792B   (PICOP_CTRL_WPCODE_1792B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_2048B   (PICOP_CTRL_WPCODE_2048B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_2304B   (PICOP_CTRL_WPCODE_2304B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_2560B   (PICOP_CTRL_WPCODE_2560B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_2816B   (PICOP_CTRL_WPCODE_2816B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_3072B   (PICOP_CTRL_WPCODE_3072B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_3328B   (PICOP_CTRL_WPCODE_3328B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_3584B   (PICOP_CTRL_WPCODE_3584B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_WPCODE_3840B   (PICOP_CTRL_WPCODE_3840B_Val << PICOP_CTRL_WPCODE_Pos)
 
#define PICOP_CTRL_MASK   0x000003FFul
 (PICOP_CTRL) MASK Register
 
#define PICOP_CMD_OFFSET   0x028
 (PICOP_CMD offset) Command
 
#define PICOP_CMD_RESETVALUE   0x00000000ul
 (PICOP_CMD reset_value) Command
 
#define PICOP_CMD_CMD_CMD_Pos   0
 (PICOP_CMD_CMD) Command
 
#define PICOP_CMD_CMD_CMD_Msk   (0xFul << PICOP_CMD_CMD_CMD_Pos)
 
#define PICOP_CMD_CMD_CMD(value)   (PICOP_CMD_CMD_CMD_Msk & ((value) << PICOP_CMD_CMD_CMD_Pos))
 
#define PICOP_CMD_CMD_CMD_NOACTION_Val   0x0ul
 (PICOP_CMD_CMD) No action
 
#define PICOP_CMD_CMD_CMD_STOP_Val   0x1ul
 (PICOP_CMD_CMD) Wait for ongoing execution to complete, then stop
 
#define PICOP_CMD_CMD_CMD_RESET_Val   0x2ul
 (PICOP_CMD_CMD) Stop, reset and stop
 
#define PICOP_CMD_CMD_CMD_RESTART_Val   0x3ul
 (PICOP_CMD_CMD) Stop, reset and run
 
#define PICOP_CMD_CMD_CMD_ABORT_Val   0x4ul
 (PICOP_CMD_CMD) Abort, reset and stop
 
#define PICOP_CMD_CMD_CMD_RUN_Val   0x5ul
 (PICOP_CMD_CMD) Start execution (from unlocked stopped state)
 
#define PICOP_CMD_CMD_CMD_RUNLOCK_Val   0x6ul
 (PICOP_CMD_CMD) Start execution and lock
 
#define PICOP_CMD_CMD_CMD_RUNOCD_Val   0x7ul
 (PICOP_CMD_CMD) Start execution and enable host-controlled OCD
 
#define PICOP_CMD_CMD_CMD_UNLOCK_Val   0x8ul
 (PICOP_CMD_CMD) Unlock and run
 
#define PICOP_CMD_CMD_CMD_NMI_Val   0x9ul
 (PICOP_CMD_CMD) Trigger a NMI
 
#define PICOP_CMD_CMD_CMD_WAKEUP_Val   0xAul
 (PICOP_CMD_CMD) Force a wakeup from sleep (if in sleep)
 
#define PICOP_CMD_CMD_CMD_NOACTION   (PICOP_CMD_CMD_CMD_NOACTION_Val << PICOP_CMD_CMD_CMD_Pos)
 
#define PICOP_CMD_CMD_CMD_STOP   (PICOP_CMD_CMD_CMD_STOP_Val << PICOP_CMD_CMD_CMD_Pos)
 
#define PICOP_CMD_CMD_CMD_RESET   (PICOP_CMD_CMD_CMD_RESET_Val << PICOP_CMD_CMD_CMD_Pos)
 
#define PICOP_CMD_CMD_CMD_RESTART   (PICOP_CMD_CMD_CMD_RESTART_Val << PICOP_CMD_CMD_CMD_Pos)
 
#define PICOP_CMD_CMD_CMD_ABORT   (PICOP_CMD_CMD_CMD_ABORT_Val << PICOP_CMD_CMD_CMD_Pos)
 
#define PICOP_CMD_CMD_CMD_RUN   (PICOP_CMD_CMD_CMD_RUN_Val << PICOP_CMD_CMD_CMD_Pos)
 
#define PICOP_CMD_CMD_CMD_RUNLOCK   (PICOP_CMD_CMD_CMD_RUNLOCK_Val << PICOP_CMD_CMD_CMD_Pos)
 
#define PICOP_CMD_CMD_CMD_RUNOCD   (PICOP_CMD_CMD_CMD_RUNOCD_Val << PICOP_CMD_CMD_CMD_Pos)
 
#define PICOP_CMD_CMD_CMD_UNLOCK   (PICOP_CMD_CMD_CMD_UNLOCK_Val << PICOP_CMD_CMD_CMD_Pos)
 
#define PICOP_CMD_CMD_CMD_NMI   (PICOP_CMD_CMD_CMD_NMI_Val << PICOP_CMD_CMD_CMD_Pos)
 
#define PICOP_CMD_CMD_CMD_WAKEUP   (PICOP_CMD_CMD_CMD_WAKEUP_Val << PICOP_CMD_CMD_CMD_Pos)
 
#define PICOP_CMD_CMD_UNLOCK_Pos   16
 (PICOP_CMD_CMD) Unlock
 
#define PICOP_CMD_CMD_UNLOCK_Msk   (0xFFFFul << PICOP_CMD_CMD_UNLOCK_Pos)
 
#define PICOP_CMD_CMD_UNLOCK(value)   (PICOP_CMD_CMD_UNLOCK_Msk & ((value) << PICOP_CMD_CMD_UNLOCK_Pos))
 
#define PICOP_CMD_CMD_MASK   0xFFFF000Ful
 (PICOP_CMD_CMD) MASK Register
 
#define PICOP_CMD_STATUS_CTTSEX_Pos   0
 (PICOP_CMD_STATUS) Context Task Switch
 
#define PICOP_CMD_STATUS_CTTSEX   (0x1ul << PICOP_CMD_STATUS_CTTSEX_Pos)
 
#define PICOP_CMD_STATUS_IL0EX_Pos   1
 (PICOP_CMD_STATUS) Interrupt Level 0 Exception
 
#define PICOP_CMD_STATUS_IL0EX   (0x1ul << PICOP_CMD_STATUS_IL0EX_Pos)
 
#define PICOP_CMD_STATUS_IL1EX_Pos   2
 (PICOP_CMD_STATUS) Interrupt Level 1 Exception
 
#define PICOP_CMD_STATUS_IL1EX   (0x1ul << PICOP_CMD_STATUS_IL1EX_Pos)
 
#define PICOP_CMD_STATUS_IL2EX_Pos   3
 (PICOP_CMD_STATUS) Interrupt Level 2 Exception
 
#define PICOP_CMD_STATUS_IL2EX   (0x1ul << PICOP_CMD_STATUS_IL2EX_Pos)
 
#define PICOP_CMD_STATUS_IL3EX_Pos   4
 (PICOP_CMD_STATUS) Interrupt Level 3 Exception
 
#define PICOP_CMD_STATUS_IL3EX   (0x1ul << PICOP_CMD_STATUS_IL3EX_Pos)
 
#define PICOP_CMD_STATUS_IL4EX_Pos   5
 (PICOP_CMD_STATUS) Interrupt Level 4 Exception
 
#define PICOP_CMD_STATUS_IL4EX   (0x1ul << PICOP_CMD_STATUS_IL4EX_Pos)
 
#define PICOP_CMD_STATUS_NMIEX_Pos   6
 (PICOP_CMD_STATUS) NMI Exception
 
#define PICOP_CMD_STATUS_NMIEX   (0x1ul << PICOP_CMD_STATUS_NMIEX_Pos)
 
#define PICOP_CMD_STATUS_EXCEPT_Pos   8
 (PICOP_CMD_STATUS) Exception
 
#define PICOP_CMD_STATUS_EXCEPT   (0x1ul << PICOP_CMD_STATUS_EXCEPT_Pos)
 
#define PICOP_CMD_STATUS_AVR16_Pos   9
 (PICOP_CMD_STATUS) AVR16 Mode
 
#define PICOP_CMD_STATUS_AVR16   (0x1ul << PICOP_CMD_STATUS_AVR16_Pos)
 
#define PICOP_CMD_STATUS_OCDCOF_Pos   10
 (PICOP_CMD_STATUS) OCD Change of Flow
 
#define PICOP_CMD_STATUS_OCDCOF   (0x1ul << PICOP_CMD_STATUS_OCDCOF_Pos)
 
#define PICOP_CMD_STATUS_UPC_Pos   16
 (PICOP_CMD_STATUS) Microcode State
 
#define PICOP_CMD_STATUS_UPC_Msk   (0xFFul << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC(value)   (PICOP_CMD_STATUS_UPC_Msk & ((value) << PICOP_CMD_STATUS_UPC_Pos))
 
#define PICOP_CMD_STATUS_UPC_EXEC_Val   0x0ul
 (PICOP_CMD_STATUS) Normal execution (no ucode)
 
#define PICOP_CMD_STATUS_UPC_EXEC_NOBRK_Val   0x1ul
 (PICOP_CMD_STATUS) Normal execution with break disabled
 
#define PICOP_CMD_STATUS_UPC_EXEC_NOP_Val   0x2ul
 (PICOP_CMD_STATUS) OCD NOP override execution (break disabled)
 
#define PICOP_CMD_STATUS_UPC_EXEC_IMM_Val   0x3ul
 (PICOP_CMD_STATUS) OCD IMM override execution (break disabled)
 
#define PICOP_CMD_STATUS_UPC_ICACHE_FLUSH_Val   0x4ul
 (PICOP_CMD_STATUS) Flush instruction cache
 
#define PICOP_CMD_STATUS_UPC_HALT_Val   0x10ul
 (PICOP_CMD_STATUS) HALT execution (shutdown)
 
#define PICOP_CMD_STATUS_UPC_HALTED_Val   0x11ul
 (PICOP_CMD_STATUS) Execution halted (shutdown)
 
#define PICOP_CMD_STATUS_UPC_SLEEP_Val   0x17ul
 (PICOP_CMD_STATUS) Wait until safe to go to sleeping state
 
#define PICOP_CMD_STATUS_UPC_SLEEPING_Val   0x18ul
 (PICOP_CMD_STATUS) Sleeping / reset cycle 0
 
#define PICOP_CMD_STATUS_UPC_WAKEUP_RST1_Val   0x19ul
 (PICOP_CMD_STATUS) Reset cycle 1
 
#define PICOP_CMD_STATUS_UPC_WAKEUP_CTR_SP_Val   0x1Aul
 (PICOP_CMD_STATUS) SLEEP: Context Restore CCR..SP
 
#define PICOP_CMD_STATUS_UPC_WAKEUP_CTR_ZY_Val   0x1Bul
 (PICOP_CMD_STATUS) SLEEP: Context Restore Z..Y
 
#define PICOP_CMD_STATUS_UPC_OCD_STATE_Val   0x20ul
 (PICOP_CMD_STATUS) OCD state: No break (sr.upc[1:0] == 2'b00)
 
#define PICOP_CMD_STATUS_UPC_OCD_STATE_NOP_Val   0x21ul
 (PICOP_CMD_STATUS) OCD state: NOP override (sr.upc[1:0] == 2'b01)
 
#define PICOP_CMD_STATUS_UPC_OCD_STATE_IMM_Val   0x22ul
 (PICOP_CMD_STATUS) OCD state: IMM override (sr.upc[1:0] == 2'b10)
 
#define PICOP_CMD_STATUS_UPC_OCD_STATE_SLEEP_Val   0x23ul
 (PICOP_CMD_STATUS) OCD state: SLEEP instruction (sr.upc[1:0] == 2'b11)
 
#define PICOP_CMD_STATUS_UPC_OCD_BREAKPOINT_Val   0x28ul
 (PICOP_CMD_STATUS) Breakpoint (sr.upc[0] == 1'b0)
 
#define PICOP_CMD_STATUS_UPC_OCD_BREAKI_Val   0x29ul
 (PICOP_CMD_STATUS) Breakpoint instruction (sr.upc[0] == 1'b1)
 
#define PICOP_CMD_STATUS_UPC_CANCEL_EX_Val   0x2Eul
 (PICOP_CMD_STATUS) Cancel exception
 
#define PICOP_CMD_STATUS_UPC_IRQ_Val   0x2Ful
 (PICOP_CMD_STATUS) IRQ: Context Save CCR..SP
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_0_Val   0x30ul
 (PICOP_CMD_STATUS) IRQ: Context Save R{m+0+1}.l
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_1_Val   0x31ul
 (PICOP_CMD_STATUS) IRQ: Context Save R{m+1+1}.l
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_2_Val   0x32ul
 (PICOP_CMD_STATUS) IRQ: Context Save R{m+2+1}.l
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_3_Val   0x33ul
 (PICOP_CMD_STATUS) IRQ: Context Save R{m+3+1}.l
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_4_Val   0x34ul
 (PICOP_CMD_STATUS) IRQ: Context Save R{m+4+1}.l
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_5_Val   0x35ul
 (PICOP_CMD_STATUS) IRQ: Context Save R{m+5+1}.l
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_6_Val   0x36ul
 (PICOP_CMD_STATUS) IRQ: Context Save R{m+6+1}.l
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_7_Val   0x37ul
 (PICOP_CMD_STATUS) IRQ: Context Save R{m+7+1}.l
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_PC_Val   0x38ul
 (PICOP_CMD_STATUS) IRQ: Context Save (SR):PC
 
#define PICOP_CMD_STATUS_UPC_IRQ_ACK_Val   0x39ul
 (PICOP_CMD_STATUS) IRQ: Acknowledge cycle
 
#define PICOP_CMD_STATUS_UPC_EXCEPT_Val   0x3Aul
 (PICOP_CMD_STATUS) Internal exceptions
 
#define PICOP_CMD_STATUS_UPC_RETI_SLEEP_Val   0x3Ful
 (PICOP_CMD_STATUS) RETI: Clear SLEEPMODE (RETI)
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R0_Val   0x40ul
 (PICOP_CMD_STATUS) RETI: Context Restore R3..R0 (RETIS)
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R4_Val   0x41ul
 (PICOP_CMD_STATUS) RETI: Context Restore R7..R4
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R8_Val   0x42ul
 (PICOP_CMD_STATUS) RETI: Context Restore R11..R8
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R12_Val   0x43ul
 (PICOP_CMD_STATUS) RETI: Context Restore R15..R12
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R16_Val   0x44ul
 (PICOP_CMD_STATUS) RETI: Context Restore R19..R16
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R20_Val   0x45ul
 (PICOP_CMD_STATUS) RETI: Context Restore R23..R20
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R24_Val   0x46ul
 (PICOP_CMD_STATUS) RETI: Context Restore R27..R24
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R28_Val   0x47ul
 (PICOP_CMD_STATUS) RETI: Context Restore R31..R28
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_SP_Val   0x48ul
 (PICOP_CMD_STATUS) RETI: Context Restore CCR..SP
 
#define PICOP_CMD_STATUS_UPC_RETI_EXEC_Val   0x49ul
 (PICOP_CMD_STATUS) RETI: Return to code execution (PC <- LINK)
 
#define PICOP_CMD_STATUS_UPC_EXEC   (PICOP_CMD_STATUS_UPC_EXEC_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_EXEC_NOBRK   (PICOP_CMD_STATUS_UPC_EXEC_NOBRK_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_EXEC_NOP   (PICOP_CMD_STATUS_UPC_EXEC_NOP_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_EXEC_IMM   (PICOP_CMD_STATUS_UPC_EXEC_IMM_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_ICACHE_FLUSH   (PICOP_CMD_STATUS_UPC_ICACHE_FLUSH_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_HALT   (PICOP_CMD_STATUS_UPC_HALT_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_HALTED   (PICOP_CMD_STATUS_UPC_HALTED_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_SLEEP   (PICOP_CMD_STATUS_UPC_SLEEP_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_SLEEPING   (PICOP_CMD_STATUS_UPC_SLEEPING_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_WAKEUP_RST1   (PICOP_CMD_STATUS_UPC_WAKEUP_RST1_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_WAKEUP_CTR_SP   (PICOP_CMD_STATUS_UPC_WAKEUP_CTR_SP_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_WAKEUP_CTR_ZY   (PICOP_CMD_STATUS_UPC_WAKEUP_CTR_ZY_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_OCD_STATE   (PICOP_CMD_STATUS_UPC_OCD_STATE_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_OCD_STATE_NOP   (PICOP_CMD_STATUS_UPC_OCD_STATE_NOP_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_OCD_STATE_IMM   (PICOP_CMD_STATUS_UPC_OCD_STATE_IMM_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_OCD_STATE_SLEEP   (PICOP_CMD_STATUS_UPC_OCD_STATE_SLEEP_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_OCD_BREAKPOINT   (PICOP_CMD_STATUS_UPC_OCD_BREAKPOINT_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_OCD_BREAKI   (PICOP_CMD_STATUS_UPC_OCD_BREAKI_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_CANCEL_EX   (PICOP_CMD_STATUS_UPC_CANCEL_EX_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_IRQ   (PICOP_CMD_STATUS_UPC_IRQ_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_0   (PICOP_CMD_STATUS_UPC_IRQ_CTS_0_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_1   (PICOP_CMD_STATUS_UPC_IRQ_CTS_1_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_2   (PICOP_CMD_STATUS_UPC_IRQ_CTS_2_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_3   (PICOP_CMD_STATUS_UPC_IRQ_CTS_3_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_4   (PICOP_CMD_STATUS_UPC_IRQ_CTS_4_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_5   (PICOP_CMD_STATUS_UPC_IRQ_CTS_5_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_6   (PICOP_CMD_STATUS_UPC_IRQ_CTS_6_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_7   (PICOP_CMD_STATUS_UPC_IRQ_CTS_7_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_IRQ_CTS_PC   (PICOP_CMD_STATUS_UPC_IRQ_CTS_PC_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_IRQ_ACK   (PICOP_CMD_STATUS_UPC_IRQ_ACK_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_EXCEPT   (PICOP_CMD_STATUS_UPC_EXCEPT_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_RETI_SLEEP   (PICOP_CMD_STATUS_UPC_RETI_SLEEP_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R0   (PICOP_CMD_STATUS_UPC_RETI_CTR_R0_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R4   (PICOP_CMD_STATUS_UPC_RETI_CTR_R4_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R8   (PICOP_CMD_STATUS_UPC_RETI_CTR_R8_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R12   (PICOP_CMD_STATUS_UPC_RETI_CTR_R12_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R16   (PICOP_CMD_STATUS_UPC_RETI_CTR_R16_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R20   (PICOP_CMD_STATUS_UPC_RETI_CTR_R20_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R24   (PICOP_CMD_STATUS_UPC_RETI_CTR_R24_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_R28   (PICOP_CMD_STATUS_UPC_RETI_CTR_R28_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_RETI_CTR_SP   (PICOP_CMD_STATUS_UPC_RETI_CTR_SP_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_UPC_RETI_EXEC   (PICOP_CMD_STATUS_UPC_RETI_EXEC_Val << PICOP_CMD_STATUS_UPC_Pos)
 
#define PICOP_CMD_STATUS_STATE_Pos   27
 (PICOP_CMD_STATUS) System State
 
#define PICOP_CMD_STATUS_STATE_Msk   (0x1Ful << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE(value)   (PICOP_CMD_STATUS_STATE_Msk & ((value) << PICOP_CMD_STATUS_STATE_Pos))
 
#define PICOP_CMD_STATUS_STATE_RESET_0_Val   0x0ul
 (PICOP_CMD_STATUS) Reset step 0
 
#define PICOP_CMD_STATUS_STATE_RESET_1_Val   0x1ul
 (PICOP_CMD_STATUS) Reset step 1
 
#define PICOP_CMD_STATUS_STATE_RESET_2_Val   0x2ul
 (PICOP_CMD_STATUS) Reset step 2
 
#define PICOP_CMD_STATUS_STATE_RESET_3_Val   0x3ul
 (PICOP_CMD_STATUS) Reset step 3
 
#define PICOP_CMD_STATUS_STATE_FUSE_CHECK_Val   0x4ul
 (PICOP_CMD_STATUS) Fuse check
 
#define PICOP_CMD_STATUS_STATE_INITIALIZED_Val   0x5ul
 (PICOP_CMD_STATUS) Initialized
 
#define PICOP_CMD_STATUS_STATE_STANDBY_Val   0x6ul
 (PICOP_CMD_STATUS) Standby
 
#define PICOP_CMD_STATUS_STATE_RUNNING_LOCKED_Val   0x8ul
 (PICOP_CMD_STATUS) Running locked
 
#define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_1_Val   0x9ul
 (PICOP_CMD_STATUS) Running unlock step 1
 
#define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_2_Val   0xAul
 (PICOP_CMD_STATUS) Running unlock step 2
 
#define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_3_Val   0xBul
 (PICOP_CMD_STATUS) Running unlock step 3
 
#define PICOP_CMD_STATUS_STATE_RUNNING_Val   0xCul
 (PICOP_CMD_STATUS) Running
 
#define PICOP_CMD_STATUS_STATE_RUNNING_BOOT_Val   0xDul
 (PICOP_CMD_STATUS) Running boot
 
#define PICOP_CMD_STATUS_STATE_RUNNING_HOSTOCD_Val   0xEul
 (PICOP_CMD_STATUS) Running hostocd
 
#define PICOP_CMD_STATUS_STATE_RESETTING_Val   0x10ul
 (PICOP_CMD_STATUS) Resetting
 
#define PICOP_CMD_STATUS_STATE_STOPPING_Val   0x11ul
 (PICOP_CMD_STATUS) Stopping
 
#define PICOP_CMD_STATUS_STATE_STOPPED_Val   0x12ul
 (PICOP_CMD_STATUS) Stopped
 
#define PICOP_CMD_STATUS_STATE_RESET_0   (PICOP_CMD_STATUS_STATE_RESET_0_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_RESET_1   (PICOP_CMD_STATUS_STATE_RESET_1_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_RESET_2   (PICOP_CMD_STATUS_STATE_RESET_2_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_RESET_3   (PICOP_CMD_STATUS_STATE_RESET_3_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_FUSE_CHECK   (PICOP_CMD_STATUS_STATE_FUSE_CHECK_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_INITIALIZED   (PICOP_CMD_STATUS_STATE_INITIALIZED_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_STANDBY   (PICOP_CMD_STATUS_STATE_STANDBY_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_RUNNING_LOCKED   (PICOP_CMD_STATUS_STATE_RUNNING_LOCKED_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_1   (PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_1_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_2   (PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_2_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_3   (PICOP_CMD_STATUS_STATE_RUNNING_UNLOCK_3_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_RUNNING   (PICOP_CMD_STATUS_STATE_RUNNING_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_RUNNING_BOOT   (PICOP_CMD_STATUS_STATE_RUNNING_BOOT_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_RUNNING_HOSTOCD   (PICOP_CMD_STATUS_STATE_RUNNING_HOSTOCD_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_RESETTING   (PICOP_CMD_STATUS_STATE_RESETTING_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_STOPPING   (PICOP_CMD_STATUS_STATE_STOPPING_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_STATE_STOPPED   (PICOP_CMD_STATUS_STATE_STOPPED_Val << PICOP_CMD_STATUS_STATE_Pos)
 
#define PICOP_CMD_STATUS_MASK   0xF8FF077Ful
 (PICOP_CMD_STATUS) MASK Register
 
#define PICOP_PC_OFFSET   0x02C
 (PICOP_PC offset) Program Counter
 
#define PICOP_PC_RESETVALUE   0x00000000ul
 (PICOP_PC reset_value) Program Counter
 
#define PICOP_PC_PC_Pos   0
 (PICOP_PC) Program Counter
 
#define PICOP_PC_PC_Msk   (0xFFFFul << PICOP_PC_PC_Pos)
 
#define PICOP_PC_PC(value)   (PICOP_PC_PC_Msk & ((value) << PICOP_PC_PC_Pos))
 
#define PICOP_PC_MASK   0x0000FFFFul
 (PICOP_PC) MASK Register
 
#define PICOP_HF_OFFSET   0x030
 (PICOP_HF offset) Host Flags
 
#define PICOP_HF_RESETVALUE   0x00000000ul
 (PICOP_HF reset_value) Host Flags
 
#define PICOP_HF_HF_Pos   0
 (PICOP_HF) Host Flags
 
#define PICOP_HF_HF_Msk   (0xFFFFFFFFul << PICOP_HF_HF_Pos)
 
#define PICOP_HF_HF(value)   (PICOP_HF_HF_Msk & ((value) << PICOP_HF_HF_Pos))
 
#define PICOP_HF_MASK   0xFFFFFFFFul
 (PICOP_HF) MASK Register
 
#define PICOP_HFCTRL_OFFSET   0x034
 (PICOP_HFCTRL offset) Host Flag Control
 
#define PICOP_HFCTRL_RESETVALUE   0x00000000ul
 (PICOP_HFCTRL reset_value) Host Flag Control
 
#define PICOP_HFCTRL_IRQENCLR_Pos   4
 (PICOP_HFCTRL) Host Flags IRQ Enable Clear
 
#define PICOP_HFCTRL_IRQENCLR_Msk   (0xFul << PICOP_HFCTRL_IRQENCLR_Pos)
 
#define PICOP_HFCTRL_IRQENCLR(value)   (PICOP_HFCTRL_IRQENCLR_Msk & ((value) << PICOP_HFCTRL_IRQENCLR_Pos))
 
#define PICOP_HFCTRL_IRQENSET_Pos   12
 (PICOP_HFCTRL) Host Flags IRQ Enable Set
 
#define PICOP_HFCTRL_IRQENSET_Msk   (0xFul << PICOP_HFCTRL_IRQENSET_Pos)
 
#define PICOP_HFCTRL_IRQENSET(value)   (PICOP_HFCTRL_IRQENSET_Msk & ((value) << PICOP_HFCTRL_IRQENSET_Pos))
 
#define PICOP_HFCTRL_MASK   0x0000F0F0ul
 (PICOP_HFCTRL) MASK Register
 
#define PICOP_HFSETCLR0_OFFSET   0x038
 (PICOP_HFSETCLR0 offset) Host Flags Set/Clr
 
#define PICOP_HFSETCLR0_RESETVALUE   0x00000000ul
 (PICOP_HFSETCLR0 reset_value) Host Flags Set/Clr
 
#define PICOP_HFSETCLR0_HFCLR0_Pos   0
 (PICOP_HFSETCLR0) Host Flags Clear bits 7:0
 
#define PICOP_HFSETCLR0_HFCLR0_Msk   (0xFFul << PICOP_HFSETCLR0_HFCLR0_Pos)
 
#define PICOP_HFSETCLR0_HFCLR0(value)   (PICOP_HFSETCLR0_HFCLR0_Msk & ((value) << PICOP_HFSETCLR0_HFCLR0_Pos))
 
#define PICOP_HFSETCLR0_HFSET0_Pos   8
 (PICOP_HFSETCLR0) Host Flags Set bits 7:0
 
#define PICOP_HFSETCLR0_HFSET0_Msk   (0xFFul << PICOP_HFSETCLR0_HFSET0_Pos)
 
#define PICOP_HFSETCLR0_HFSET0(value)   (PICOP_HFSETCLR0_HFSET0_Msk & ((value) << PICOP_HFSETCLR0_HFSET0_Pos))
 
#define PICOP_HFSETCLR0_HFCLR1_Pos   16
 (PICOP_HFSETCLR0) Host Flags Clear bits 15:8
 
#define PICOP_HFSETCLR0_HFCLR1_Msk   (0xFFul << PICOP_HFSETCLR0_HFCLR1_Pos)
 
#define PICOP_HFSETCLR0_HFCLR1(value)   (PICOP_HFSETCLR0_HFCLR1_Msk & ((value) << PICOP_HFSETCLR0_HFCLR1_Pos))
 
#define PICOP_HFSETCLR0_HFSET1_Pos   24
 (PICOP_HFSETCLR0) Host Flags Set bits 15:8
 
#define PICOP_HFSETCLR0_HFSET1_Msk   (0xFFul << PICOP_HFSETCLR0_HFSET1_Pos)
 
#define PICOP_HFSETCLR0_HFSET1(value)   (PICOP_HFSETCLR0_HFSET1_Msk & ((value) << PICOP_HFSETCLR0_HFSET1_Pos))
 
#define PICOP_HFSETCLR0_MASK   0xFFFFFFFFul
 (PICOP_HFSETCLR0) MASK Register
 
#define PICOP_HFSETCLR1_OFFSET   0x03C
 (PICOP_HFSETCLR1 offset) Host Flags Set/Clr
 
#define PICOP_HFSETCLR1_RESETVALUE   0x00000000ul
 (PICOP_HFSETCLR1 reset_value) Host Flags Set/Clr
 
#define PICOP_HFSETCLR1_HFCLR2_Pos   0
 (PICOP_HFSETCLR1) Host Flags Clear bits 23:16
 
#define PICOP_HFSETCLR1_HFCLR2_Msk   (0xFFul << PICOP_HFSETCLR1_HFCLR2_Pos)
 
#define PICOP_HFSETCLR1_HFCLR2(value)   (PICOP_HFSETCLR1_HFCLR2_Msk & ((value) << PICOP_HFSETCLR1_HFCLR2_Pos))
 
#define PICOP_HFSETCLR1_HFSET2_Pos   8
 (PICOP_HFSETCLR1) Host Flags Set bits 23:16
 
#define PICOP_HFSETCLR1_HFSET2_Msk   (0xFFul << PICOP_HFSETCLR1_HFSET2_Pos)
 
#define PICOP_HFSETCLR1_HFSET2(value)   (PICOP_HFSETCLR1_HFSET2_Msk & ((value) << PICOP_HFSETCLR1_HFSET2_Pos))
 
#define PICOP_HFSETCLR1_HFCLR3_Pos   16
 (PICOP_HFSETCLR1) Host Flags Clear bits 31:24
 
#define PICOP_HFSETCLR1_HFCLR3_Msk   (0xFFul << PICOP_HFSETCLR1_HFCLR3_Pos)
 
#define PICOP_HFSETCLR1_HFCLR3(value)   (PICOP_HFSETCLR1_HFCLR3_Msk & ((value) << PICOP_HFSETCLR1_HFCLR3_Pos))
 
#define PICOP_HFSETCLR1_HFSET3_Pos   24
 (PICOP_HFSETCLR1) Host Flags Set bits 31:24
 
#define PICOP_HFSETCLR1_HFSET3_Msk   (0xFFul << PICOP_HFSETCLR1_HFSET3_Pos)
 
#define PICOP_HFSETCLR1_HFSET3(value)   (PICOP_HFSETCLR1_HFSET3_Msk & ((value) << PICOP_HFSETCLR1_HFSET3_Pos))
 
#define PICOP_HFSETCLR1_MASK   0xFFFFFFFFul
 (PICOP_HFSETCLR1) MASK Register
 
#define PICOP_OCDCONFIG_OFFSET   0x050
 (PICOP_OCDCONFIG offset) OCD Configuration
 
#define PICOP_OCDCONFIG_RESETVALUE   0x00000000ul
 (PICOP_OCDCONFIG reset_value) OCD Configuration
 
#define PICOP_OCDCONFIG_CCNTEN_Pos   1
 (PICOP_OCDCONFIG) Cycle Counter Enable
 
#define PICOP_OCDCONFIG_CCNTEN   (0x1ul << PICOP_OCDCONFIG_CCNTEN_Pos)
 
#define PICOP_OCDCONFIG_MASK   0x00000002ul
 (PICOP_OCDCONFIG) MASK Register
 
#define PICOP_OCDCONTROL_OFFSET   0x054
 (PICOP_OCDCONTROL offset) OCD Control
 
#define PICOP_OCDCONTROL_RESETVALUE   0x00000000ul
 (PICOP_OCDCONTROL reset_value) OCD Control
 
#define PICOP_OCDCONTROL_OCDEN_Pos   0
 (PICOP_OCDCONTROL) OCD Enable
 
#define PICOP_OCDCONTROL_OCDEN   (0x1ul << PICOP_OCDCONTROL_OCDEN_Pos)
 
#define PICOP_OCDCONTROL_BPSSTEP_Pos   2
 (PICOP_OCDCONTROL) Single Step Breakpoint
 
#define PICOP_OCDCONTROL_BPSSTEP   (0x1ul << PICOP_OCDCONTROL_BPSSTEP_Pos)
 
#define PICOP_OCDCONTROL_BPCOF_Pos   3
 (PICOP_OCDCONTROL) Change of Flow Breakpoint
 
#define PICOP_OCDCONTROL_BPCOF   (0x1ul << PICOP_OCDCONTROL_BPCOF_Pos)
 
#define PICOP_OCDCONTROL_BPRST_Pos   4
 (PICOP_OCDCONTROL) Reset Breakpoint
 
#define PICOP_OCDCONTROL_BPRST   (0x1ul << PICOP_OCDCONTROL_BPRST_Pos)
 
#define PICOP_OCDCONTROL_BPEXCEPTION_Pos   5
 (PICOP_OCDCONTROL) Exception Breakpoint
 
#define PICOP_OCDCONTROL_BPEXCEPTION   (0x1ul << PICOP_OCDCONTROL_BPEXCEPTION_Pos)
 
#define PICOP_OCDCONTROL_BPIRQ_Pos   6
 (PICOP_OCDCONTROL) Interrupt Request Breakpoint
 
#define PICOP_OCDCONTROL_BPIRQ   (0x1ul << PICOP_OCDCONTROL_BPIRQ_Pos)
 
#define PICOP_OCDCONTROL_BPSW_Pos   7
 (PICOP_OCDCONTROL) Software Breakpoint
 
#define PICOP_OCDCONTROL_BPSW   (0x1ul << PICOP_OCDCONTROL_BPSW_Pos)
 
#define PICOP_OCDCONTROL_BPSLEEP_Pos   8
 (PICOP_OCDCONTROL) Sleep Breakpoint
 
#define PICOP_OCDCONTROL_BPSLEEP   (0x1ul << PICOP_OCDCONTROL_BPSLEEP_Pos)
 
#define PICOP_OCDCONTROL_BPWDT_Pos   9
 (PICOP_OCDCONTROL) Watchdog Timer Breakpoint
 
#define PICOP_OCDCONTROL_BPWDT   (0x1ul << PICOP_OCDCONTROL_BPWDT_Pos)
 
#define PICOP_OCDCONTROL_BPISA_Pos   10
 (PICOP_OCDCONTROL) ISA Breakpoint
 
#define PICOP_OCDCONTROL_BPISA   (0x1ul << PICOP_OCDCONTROL_BPISA_Pos)
 
#define PICOP_OCDCONTROL_BPCOMP_Pos   12
 (PICOP_OCDCONTROL) Comparator Breakpoint
 
#define PICOP_OCDCONTROL_BPCOMP_Msk   (0xFul << PICOP_OCDCONTROL_BPCOMP_Pos)
 
#define PICOP_OCDCONTROL_BPCOMP(value)   (PICOP_OCDCONTROL_BPCOMP_Msk & ((value) << PICOP_OCDCONTROL_BPCOMP_Pos))
 
#define PICOP_OCDCONTROL_BPGENMODE_Pos   16
 (PICOP_OCDCONTROL) Breakpoint Generator n Mode
 
#define PICOP_OCDCONTROL_BPGENMODE_Msk   (0xFul << PICOP_OCDCONTROL_BPGENMODE_Pos)
 
#define PICOP_OCDCONTROL_BPGENMODE(value)   (PICOP_OCDCONTROL_BPGENMODE_Msk & ((value) << PICOP_OCDCONTROL_BPGENMODE_Pos))
 
#define PICOP_OCDCONTROL_MASK   0x000FF7FDul
 (PICOP_OCDCONTROL) MASK Register
 
#define PICOP_OCDSTATUS_OFFSET   0x058
 (PICOP_OCDSTATUS offset) OCD Status and Command
 
#define PICOP_OCDSTATUS_RESETVALUE   0x00000000ul
 (PICOP_OCDSTATUS reset_value) OCD Status and Command
 
#define PICOP_OCDSTATUS_CMD_INST_Pos   0
 (PICOP_OCDSTATUS_CMD) Instruction Override
 
#define PICOP_OCDSTATUS_CMD_INST_Msk   (0xFFFFul << PICOP_OCDSTATUS_CMD_INST_Pos)
 
#define PICOP_OCDSTATUS_CMD_INST(value)   (PICOP_OCDSTATUS_CMD_INST_Msk & ((value) << PICOP_OCDSTATUS_CMD_INST_Pos))
 
#define PICOP_OCDSTATUS_CMD_MASK   0x0000FFFFul
 (PICOP_OCDSTATUS_CMD) MASK Register
 
#define PICOP_OCDSTATUS_STATUS_BPEXT_Pos   1
 (PICOP_OCDSTATUS_STATUS) External Breakpoint
 
#define PICOP_OCDSTATUS_STATUS_BPEXT   (0x1ul << PICOP_OCDSTATUS_STATUS_BPEXT_Pos)
 
#define PICOP_OCDSTATUS_STATUS_BPSSTEP_Pos   2
 (PICOP_OCDSTATUS_STATUS) Single Step Breakpoint
 
#define PICOP_OCDSTATUS_STATUS_BPSSTEP   (0x1ul << PICOP_OCDSTATUS_STATUS_BPSSTEP_Pos)
 
#define PICOP_OCDSTATUS_STATUS_BPCOF_Pos   3
 (PICOP_OCDSTATUS_STATUS) Change of Flow Breakpoint
 
#define PICOP_OCDSTATUS_STATUS_BPCOF   (0x1ul << PICOP_OCDSTATUS_STATUS_BPCOF_Pos)
 
#define PICOP_OCDSTATUS_STATUS_BPRST_Pos   4
 (PICOP_OCDSTATUS_STATUS) Reset Breakpoint
 
#define PICOP_OCDSTATUS_STATUS_BPRST   (0x1ul << PICOP_OCDSTATUS_STATUS_BPRST_Pos)
 
#define PICOP_OCDSTATUS_STATUS_BPEXCEPTION_Pos   5
 (PICOP_OCDSTATUS_STATUS) Exception Breakpoint
 
#define PICOP_OCDSTATUS_STATUS_BPEXCEPTION   (0x1ul << PICOP_OCDSTATUS_STATUS_BPEXCEPTION_Pos)
 
#define PICOP_OCDSTATUS_STATUS_BPIRQ_Pos   6
 (PICOP_OCDSTATUS_STATUS) Interrupt Request Breakpoint
 
#define PICOP_OCDSTATUS_STATUS_BPIRQ   (0x1ul << PICOP_OCDSTATUS_STATUS_BPIRQ_Pos)
 
#define PICOP_OCDSTATUS_STATUS_BPSW_Pos   7
 (PICOP_OCDSTATUS_STATUS) Software Breakpoint
 
#define PICOP_OCDSTATUS_STATUS_BPSW   (0x1ul << PICOP_OCDSTATUS_STATUS_BPSW_Pos)
 
#define PICOP_OCDSTATUS_STATUS_BPSLEEP_Pos   8
 (PICOP_OCDSTATUS_STATUS) Sleep Breakpoint
 
#define PICOP_OCDSTATUS_STATUS_BPSLEEP   (0x1ul << PICOP_OCDSTATUS_STATUS_BPSLEEP_Pos)
 
#define PICOP_OCDSTATUS_STATUS_BPWDT_Pos   9
 (PICOP_OCDSTATUS_STATUS) Watchdog Timer Breakpoint
 
#define PICOP_OCDSTATUS_STATUS_BPWDT   (0x1ul << PICOP_OCDSTATUS_STATUS_BPWDT_Pos)
 
#define PICOP_OCDSTATUS_STATUS_BPISA_Pos   10
 (PICOP_OCDSTATUS_STATUS) ISA Breakpoint
 
#define PICOP_OCDSTATUS_STATUS_BPISA   (0x1ul << PICOP_OCDSTATUS_STATUS_BPISA_Pos)
 
#define PICOP_OCDSTATUS_STATUS_BPCOMP_Pos   12
 (PICOP_OCDSTATUS_STATUS) Comparator Breakpoint
 
#define PICOP_OCDSTATUS_STATUS_BPCOMP_Msk   (0xFul << PICOP_OCDSTATUS_STATUS_BPCOMP_Pos)
 
#define PICOP_OCDSTATUS_STATUS_BPCOMP(value)   (PICOP_OCDSTATUS_STATUS_BPCOMP_Msk & ((value) << PICOP_OCDSTATUS_STATUS_BPCOMP_Pos))
 
#define PICOP_OCDSTATUS_STATUS_MASK   0x0000F7FEul
 (PICOP_OCDSTATUS_STATUS) MASK Register
 
#define PICOP_OCDPC_OFFSET   0x05C
 (PICOP_OCDPC offset) ODC Program Counter
 
#define PICOP_OCDPC_PC_Pos   0
 (PICOP_OCDPC) Program Counter
 
#define PICOP_OCDPC_PC_Msk   (0xFFFFul << PICOP_OCDPC_PC_Pos)
 
#define PICOP_OCDPC_PC(value)   (PICOP_OCDPC_PC_Msk & ((value) << PICOP_OCDPC_PC_Pos))
 
#define PICOP_OCDPC_MASK   0x0000FFFFul
 (PICOP_OCDPC) MASK Register
 
#define PICOP_OCDFEAT_OFFSET   0x060
 (PICOP_OCDFEAT offset) OCD Features
 
#define PICOP_OCDFEAT_RESETVALUE   0x00000000ul
 (PICOP_OCDFEAT reset_value) OCD Features
 
#define PICOP_OCDFEAT_CCNT_Pos   0
 (PICOP_OCDFEAT) Cycle Counter
 
#define PICOP_OCDFEAT_CCNT_Msk   (0x3ul << PICOP_OCDFEAT_CCNT_Pos)
 
#define PICOP_OCDFEAT_CCNT(value)   (PICOP_OCDFEAT_CCNT_Msk & ((value) << PICOP_OCDFEAT_CCNT_Pos))
 
#define PICOP_OCDFEAT_BPGEN_Pos   2
 (PICOP_OCDFEAT) Breakpoint Generators
 
#define PICOP_OCDFEAT_BPGEN_Msk   (0x3ul << PICOP_OCDFEAT_BPGEN_Pos)
 
#define PICOP_OCDFEAT_BPGEN(value)   (PICOP_OCDFEAT_BPGEN_Msk & ((value) << PICOP_OCDFEAT_BPGEN_Pos))
 
#define PICOP_OCDFEAT_MASK   0x0000000Ful
 (PICOP_OCDFEAT) MASK Register
 
#define PICOP_OCDCCNT_OFFSET   0x068
 (PICOP_OCDCCNT offset) OCD Cycle Counter
 
#define PICOP_OCDCCNT_RESETVALUE   0x00000000ul
 (PICOP_OCDCCNT reset_value) OCD Cycle Counter
 
#define PICOP_OCDCCNT_CCNT_Pos   0
 (PICOP_OCDCCNT) Cycle Count
 
#define PICOP_OCDCCNT_CCNT_Msk   (0xFFFFFFFFul << PICOP_OCDCCNT_CCNT_Pos)
 
#define PICOP_OCDCCNT_CCNT(value)   (PICOP_OCDCCNT_CCNT_Msk & ((value) << PICOP_OCDCCNT_CCNT_Pos))
 
#define PICOP_OCDCCNT_MASK   0xFFFFFFFFul
 (PICOP_OCDCCNT) MASK Register
 
#define PICOP_OCDBPGEN_OFFSET   0x070
 (PICOP_OCDBPGEN offset) OCD Breakpoint Generator n
 
#define PICOP_OCDBPGEN_RESETVALUE   0x00000000ul
 (PICOP_OCDBPGEN reset_value) OCD Breakpoint Generator n
 
#define PICOP_OCDBPGEN_BPGEN_Pos   0
 (PICOP_OCDBPGEN) Breakpoint Generator
 
#define PICOP_OCDBPGEN_BPGEN_Msk   (0xFFFFul << PICOP_OCDBPGEN_BPGEN_Pos)
 
#define PICOP_OCDBPGEN_BPGEN(value)   (PICOP_OCDBPGEN_BPGEN_Msk & ((value) << PICOP_OCDBPGEN_BPGEN_Pos))
 
#define PICOP_OCDBPGEN_MASK   0x0000FFFFul
 (PICOP_OCDBPGEN) MASK Register
 
#define PICOP_R3R0_OFFSET   0x080
 (PICOP_R3R0 offset) R3 to 0
 
#define PICOP_R3R0_R0_Pos   0
 (PICOP_R3R0) Register 0
 
#define PICOP_R3R0_R0_Msk   (0xFFul << PICOP_R3R0_R0_Pos)
 
#define PICOP_R3R0_R0(value)   (PICOP_R3R0_R0_Msk & ((value) << PICOP_R3R0_R0_Pos))
 
#define PICOP_R3R0_R1_Pos   8
 (PICOP_R3R0) Register 1
 
#define PICOP_R3R0_R1_Msk   (0xFFul << PICOP_R3R0_R1_Pos)
 
#define PICOP_R3R0_R1(value)   (PICOP_R3R0_R1_Msk & ((value) << PICOP_R3R0_R1_Pos))
 
#define PICOP_R3R0_R2_Pos   16
 (PICOP_R3R0) Register 2
 
#define PICOP_R3R0_R2_Msk   (0xFFul << PICOP_R3R0_R2_Pos)
 
#define PICOP_R3R0_R2(value)   (PICOP_R3R0_R2_Msk & ((value) << PICOP_R3R0_R2_Pos))
 
#define PICOP_R3R0_R3_Pos   24
 (PICOP_R3R0) Register 3
 
#define PICOP_R3R0_R3_Msk   (0xFFul << PICOP_R3R0_R3_Pos)
 
#define PICOP_R3R0_R3(value)   (PICOP_R3R0_R3_Msk & ((value) << PICOP_R3R0_R3_Pos))
 
#define PICOP_R3R0_MASK   0xFFFFFFFFul
 (PICOP_R3R0) MASK Register
 
#define PICOP_R7R4_OFFSET   0x084
 (PICOP_R7R4 offset) R7 to 4
 
#define PICOP_R7R4_R0_Pos   0
 (PICOP_R7R4) Register 0
 
#define PICOP_R7R4_R0_Msk   (0xFFul << PICOP_R7R4_R0_Pos)
 
#define PICOP_R7R4_R0(value)   (PICOP_R7R4_R0_Msk & ((value) << PICOP_R7R4_R0_Pos))
 
#define PICOP_R7R4_R1_Pos   8
 (PICOP_R7R4) Register 1
 
#define PICOP_R7R4_R1_Msk   (0xFFul << PICOP_R7R4_R1_Pos)
 
#define PICOP_R7R4_R1(value)   (PICOP_R7R4_R1_Msk & ((value) << PICOP_R7R4_R1_Pos))
 
#define PICOP_R7R4_R2_Pos   16
 (PICOP_R7R4) Register 2
 
#define PICOP_R7R4_R2_Msk   (0xFFul << PICOP_R7R4_R2_Pos)
 
#define PICOP_R7R4_R2(value)   (PICOP_R7R4_R2_Msk & ((value) << PICOP_R7R4_R2_Pos))
 
#define PICOP_R7R4_R3_Pos   24
 (PICOP_R7R4) Register 3
 
#define PICOP_R7R4_R3_Msk   (0xFFul << PICOP_R7R4_R3_Pos)
 
#define PICOP_R7R4_R3(value)   (PICOP_R7R4_R3_Msk & ((value) << PICOP_R7R4_R3_Pos))
 
#define PICOP_R7R4_MASK   0xFFFFFFFFul
 (PICOP_R7R4) MASK Register
 
#define PICOP_R11R8_OFFSET   0x088
 (PICOP_R11R8 offset) R11 to 8
 
#define PICOP_R11R8_R0_Pos   0
 (PICOP_R11R8) Register 0
 
#define PICOP_R11R8_R0_Msk   (0xFFul << PICOP_R11R8_R0_Pos)
 
#define PICOP_R11R8_R0(value)   (PICOP_R11R8_R0_Msk & ((value) << PICOP_R11R8_R0_Pos))
 
#define PICOP_R11R8_R1_Pos   8
 (PICOP_R11R8) Register 1
 
#define PICOP_R11R8_R1_Msk   (0xFFul << PICOP_R11R8_R1_Pos)
 
#define PICOP_R11R8_R1(value)   (PICOP_R11R8_R1_Msk & ((value) << PICOP_R11R8_R1_Pos))
 
#define PICOP_R11R8_R2_Pos   16
 (PICOP_R11R8) Register 2
 
#define PICOP_R11R8_R2_Msk   (0xFFul << PICOP_R11R8_R2_Pos)
 
#define PICOP_R11R8_R2(value)   (PICOP_R11R8_R2_Msk & ((value) << PICOP_R11R8_R2_Pos))
 
#define PICOP_R11R8_R3_Pos   24
 (PICOP_R11R8) Register 3
 
#define PICOP_R11R8_R3_Msk   (0xFFul << PICOP_R11R8_R3_Pos)
 
#define PICOP_R11R8_R3(value)   (PICOP_R11R8_R3_Msk & ((value) << PICOP_R11R8_R3_Pos))
 
#define PICOP_R11R8_MASK   0xFFFFFFFFul
 (PICOP_R11R8) MASK Register
 
#define PICOP_R15R12_OFFSET   0x08C
 (PICOP_R15R12 offset) R15 to 12
 
#define PICOP_R15R12_R0_Pos   0
 (PICOP_R15R12) Register 0
 
#define PICOP_R15R12_R0_Msk   (0xFFul << PICOP_R15R12_R0_Pos)
 
#define PICOP_R15R12_R0(value)   (PICOP_R15R12_R0_Msk & ((value) << PICOP_R15R12_R0_Pos))
 
#define PICOP_R15R12_R1_Pos   8
 (PICOP_R15R12) Register 1
 
#define PICOP_R15R12_R1_Msk   (0xFFul << PICOP_R15R12_R1_Pos)
 
#define PICOP_R15R12_R1(value)   (PICOP_R15R12_R1_Msk & ((value) << PICOP_R15R12_R1_Pos))
 
#define PICOP_R15R12_R2_Pos   16
 (PICOP_R15R12) Register 2
 
#define PICOP_R15R12_R2_Msk   (0xFFul << PICOP_R15R12_R2_Pos)
 
#define PICOP_R15R12_R2(value)   (PICOP_R15R12_R2_Msk & ((value) << PICOP_R15R12_R2_Pos))
 
#define PICOP_R15R12_R3_Pos   24
 (PICOP_R15R12) Register 3
 
#define PICOP_R15R12_R3_Msk   (0xFFul << PICOP_R15R12_R3_Pos)
 
#define PICOP_R15R12_R3(value)   (PICOP_R15R12_R3_Msk & ((value) << PICOP_R15R12_R3_Pos))
 
#define PICOP_R15R12_MASK   0xFFFFFFFFul
 (PICOP_R15R12) MASK Register
 
#define PICOP_R19R16_OFFSET   0x090
 (PICOP_R19R16 offset) R19 to 16
 
#define PICOP_R19R16_R0_Pos   0
 (PICOP_R19R16) Register 0
 
#define PICOP_R19R16_R0_Msk   (0xFFul << PICOP_R19R16_R0_Pos)
 
#define PICOP_R19R16_R0(value)   (PICOP_R19R16_R0_Msk & ((value) << PICOP_R19R16_R0_Pos))
 
#define PICOP_R19R16_R1_Pos   8
 (PICOP_R19R16) Register 1
 
#define PICOP_R19R16_R1_Msk   (0xFFul << PICOP_R19R16_R1_Pos)
 
#define PICOP_R19R16_R1(value)   (PICOP_R19R16_R1_Msk & ((value) << PICOP_R19R16_R1_Pos))
 
#define PICOP_R19R16_R2_Pos   16
 (PICOP_R19R16) Register 2
 
#define PICOP_R19R16_R2_Msk   (0xFFul << PICOP_R19R16_R2_Pos)
 
#define PICOP_R19R16_R2(value)   (PICOP_R19R16_R2_Msk & ((value) << PICOP_R19R16_R2_Pos))
 
#define PICOP_R19R16_R3_Pos   24
 (PICOP_R19R16) Register 3
 
#define PICOP_R19R16_R3_Msk   (0xFFul << PICOP_R19R16_R3_Pos)
 
#define PICOP_R19R16_R3(value)   (PICOP_R19R16_R3_Msk & ((value) << PICOP_R19R16_R3_Pos))
 
#define PICOP_R19R16_MASK   0xFFFFFFFFul
 (PICOP_R19R16) MASK Register
 
#define PICOP_R23R20_OFFSET   0x094
 (PICOP_R23R20 offset) R23 to 20
 
#define PICOP_R23R20_R0_Pos   0
 (PICOP_R23R20) Register 0
 
#define PICOP_R23R20_R0_Msk   (0xFFul << PICOP_R23R20_R0_Pos)
 
#define PICOP_R23R20_R0(value)   (PICOP_R23R20_R0_Msk & ((value) << PICOP_R23R20_R0_Pos))
 
#define PICOP_R23R20_R1_Pos   8
 (PICOP_R23R20) Register 1
 
#define PICOP_R23R20_R1_Msk   (0xFFul << PICOP_R23R20_R1_Pos)
 
#define PICOP_R23R20_R1(value)   (PICOP_R23R20_R1_Msk & ((value) << PICOP_R23R20_R1_Pos))
 
#define PICOP_R23R20_R2_Pos   16
 (PICOP_R23R20) Register 2
 
#define PICOP_R23R20_R2_Msk   (0xFFul << PICOP_R23R20_R2_Pos)
 
#define PICOP_R23R20_R2(value)   (PICOP_R23R20_R2_Msk & ((value) << PICOP_R23R20_R2_Pos))
 
#define PICOP_R23R20_R3_Pos   24
 (PICOP_R23R20) Register 3
 
#define PICOP_R23R20_R3_Msk   (0xFFul << PICOP_R23R20_R3_Pos)
 
#define PICOP_R23R20_R3(value)   (PICOP_R23R20_R3_Msk & ((value) << PICOP_R23R20_R3_Pos))
 
#define PICOP_R23R20_MASK   0xFFFFFFFFul
 (PICOP_R23R20) MASK Register
 
#define PICOP_R27R24_OFFSET   0x098
 (PICOP_R27R24 offset) R27 to 24: XH, XL, R25, R24
 
#define PICOP_R27R24_R0_Pos   0
 (PICOP_R27R24) Register 0
 
#define PICOP_R27R24_R0_Msk   (0xFFul << PICOP_R27R24_R0_Pos)
 
#define PICOP_R27R24_R0(value)   (PICOP_R27R24_R0_Msk & ((value) << PICOP_R27R24_R0_Pos))
 
#define PICOP_R27R24_R1_Pos   8
 (PICOP_R27R24) Register 1
 
#define PICOP_R27R24_R1_Msk   (0xFFul << PICOP_R27R24_R1_Pos)
 
#define PICOP_R27R24_R1(value)   (PICOP_R27R24_R1_Msk & ((value) << PICOP_R27R24_R1_Pos))
 
#define PICOP_R27R24_R2_Pos   16
 (PICOP_R27R24) Register 2
 
#define PICOP_R27R24_R2_Msk   (0xFFul << PICOP_R27R24_R2_Pos)
 
#define PICOP_R27R24_R2(value)   (PICOP_R27R24_R2_Msk & ((value) << PICOP_R27R24_R2_Pos))
 
#define PICOP_R27R24_R3_Pos   24
 (PICOP_R27R24) Register 3
 
#define PICOP_R27R24_R3_Msk   (0xFFul << PICOP_R27R24_R3_Pos)
 
#define PICOP_R27R24_R3(value)   (PICOP_R27R24_R3_Msk & ((value) << PICOP_R27R24_R3_Pos))
 
#define PICOP_R27R24_MASK   0xFFFFFFFFul
 (PICOP_R27R24) MASK Register
 
#define PICOP_R31R28_OFFSET   0x09C
 (PICOP_R31R28 offset) R31 to 28: ZH, ZL, YH, YL
 
#define PICOP_R31R28_R0_Pos   0
 (PICOP_R31R28) Register 0
 
#define PICOP_R31R28_R0_Msk   (0xFFul << PICOP_R31R28_R0_Pos)
 
#define PICOP_R31R28_R0(value)   (PICOP_R31R28_R0_Msk & ((value) << PICOP_R31R28_R0_Pos))
 
#define PICOP_R31R28_R1_Pos   8
 (PICOP_R31R28) Register 1
 
#define PICOP_R31R28_R1_Msk   (0xFFul << PICOP_R31R28_R1_Pos)
 
#define PICOP_R31R28_R1(value)   (PICOP_R31R28_R1_Msk & ((value) << PICOP_R31R28_R1_Pos))
 
#define PICOP_R31R28_R2_Pos   16
 (PICOP_R31R28) Register 2
 
#define PICOP_R31R28_R2_Msk   (0xFFul << PICOP_R31R28_R2_Pos)
 
#define PICOP_R31R28_R2(value)   (PICOP_R31R28_R2_Msk & ((value) << PICOP_R31R28_R2_Pos))
 
#define PICOP_R31R28_R3_Pos   24
 (PICOP_R31R28) Register 3
 
#define PICOP_R31R28_R3_Msk   (0xFFul << PICOP_R31R28_R3_Pos)
 
#define PICOP_R31R28_R3(value)   (PICOP_R31R28_R3_Msk & ((value) << PICOP_R31R28_R3_Pos))
 
#define PICOP_R31R28_MASK   0xFFFFFFFFul
 (PICOP_R31R28) MASK Register
 
#define PICOP_S1S0_OFFSET   0x0A0
 (PICOP_S1S0 offset) System Regs 1 to 0: SR
 
#define PICOP_S1S0_R0_Pos   0
 (PICOP_S1S0) Register 0
 
#define PICOP_S1S0_R0_Msk   (0xFFul << PICOP_S1S0_R0_Pos)
 
#define PICOP_S1S0_R0(value)   (PICOP_S1S0_R0_Msk & ((value) << PICOP_S1S0_R0_Pos))
 
#define PICOP_S1S0_R1_Pos   8
 (PICOP_S1S0) Register 1
 
#define PICOP_S1S0_R1_Msk   (0xFFul << PICOP_S1S0_R1_Pos)
 
#define PICOP_S1S0_R1(value)   (PICOP_S1S0_R1_Msk & ((value) << PICOP_S1S0_R1_Pos))
 
#define PICOP_S1S0_R2_Pos   16
 (PICOP_S1S0) Register 2
 
#define PICOP_S1S0_R2_Msk   (0xFFul << PICOP_S1S0_R2_Pos)
 
#define PICOP_S1S0_R2(value)   (PICOP_S1S0_R2_Msk & ((value) << PICOP_S1S0_R2_Pos))
 
#define PICOP_S1S0_R3_Pos   24
 (PICOP_S1S0) Register 3
 
#define PICOP_S1S0_R3_Msk   (0xFFul << PICOP_S1S0_R3_Pos)
 
#define PICOP_S1S0_R3(value)   (PICOP_S1S0_R3_Msk & ((value) << PICOP_S1S0_R3_Pos))
 
#define PICOP_S1S0_MASK   0xFFFFFFFFul
 (PICOP_S1S0) MASK Register
 
#define PICOP_S3S2_OFFSET   0x0A4
 (PICOP_S3S2 offset) System Regs 3 to 2: CTRL
 
#define PICOP_S3S2_R0_Pos   0
 (PICOP_S3S2) Register 0
 
#define PICOP_S3S2_R0_Msk   (0xFFul << PICOP_S3S2_R0_Pos)
 
#define PICOP_S3S2_R0(value)   (PICOP_S3S2_R0_Msk & ((value) << PICOP_S3S2_R0_Pos))
 
#define PICOP_S3S2_R1_Pos   8
 (PICOP_S3S2) Register 1
 
#define PICOP_S3S2_R1_Msk   (0xFFul << PICOP_S3S2_R1_Pos)
 
#define PICOP_S3S2_R1(value)   (PICOP_S3S2_R1_Msk & ((value) << PICOP_S3S2_R1_Pos))
 
#define PICOP_S3S2_R2_Pos   16
 (PICOP_S3S2) Register 2
 
#define PICOP_S3S2_R2_Msk   (0xFFul << PICOP_S3S2_R2_Pos)
 
#define PICOP_S3S2_R2(value)   (PICOP_S3S2_R2_Msk & ((value) << PICOP_S3S2_R2_Pos))
 
#define PICOP_S3S2_R3_Pos   24
 (PICOP_S3S2) Register 3
 
#define PICOP_S3S2_R3_Msk   (0xFFul << PICOP_S3S2_R3_Pos)
 
#define PICOP_S3S2_R3(value)   (PICOP_S3S2_R3_Msk & ((value) << PICOP_S3S2_R3_Pos))
 
#define PICOP_S3S2_MASK   0xFFFFFFFFul
 (PICOP_S3S2) MASK Register
 
#define PICOP_S5S4_OFFSET   0x0A8
 (PICOP_S5S4 offset) System Regs 5 to 4: SREG, CCR
 
#define PICOP_S5S4_R0_Pos   0
 (PICOP_S5S4) Register 0
 
#define PICOP_S5S4_R0_Msk   (0xFFul << PICOP_S5S4_R0_Pos)
 
#define PICOP_S5S4_R0(value)   (PICOP_S5S4_R0_Msk & ((value) << PICOP_S5S4_R0_Pos))
 
#define PICOP_S5S4_R1_Pos   8
 (PICOP_S5S4) Register 1
 
#define PICOP_S5S4_R1_Msk   (0xFFul << PICOP_S5S4_R1_Pos)
 
#define PICOP_S5S4_R1(value)   (PICOP_S5S4_R1_Msk & ((value) << PICOP_S5S4_R1_Pos))
 
#define PICOP_S5S4_R2_Pos   16
 (PICOP_S5S4) Register 2
 
#define PICOP_S5S4_R2_Msk   (0xFFul << PICOP_S5S4_R2_Pos)
 
#define PICOP_S5S4_R2(value)   (PICOP_S5S4_R2_Msk & ((value) << PICOP_S5S4_R2_Pos))
 
#define PICOP_S5S4_R3_Pos   24
 (PICOP_S5S4) Register 3
 
#define PICOP_S5S4_R3_Msk   (0xFFul << PICOP_S5S4_R3_Pos)
 
#define PICOP_S5S4_R3(value)   (PICOP_S5S4_R3_Msk & ((value) << PICOP_S5S4_R3_Pos))
 
#define PICOP_S5S4_MASK   0xFFFFFFFFul
 (PICOP_S5S4) MASK Register
 
#define PICOP_S11S10_OFFSET   0x0B4
 (PICOP_S11S10 offset) System Regs 11 to 10: Immediate
 
#define PICOP_S11S10_R0_Pos   0
 (PICOP_S11S10) Register 0
 
#define PICOP_S11S10_R0_Msk   (0xFFul << PICOP_S11S10_R0_Pos)
 
#define PICOP_S11S10_R0(value)   (PICOP_S11S10_R0_Msk & ((value) << PICOP_S11S10_R0_Pos))
 
#define PICOP_S11S10_R1_Pos   8
 (PICOP_S11S10) Register 1
 
#define PICOP_S11S10_R1_Msk   (0xFFul << PICOP_S11S10_R1_Pos)
 
#define PICOP_S11S10_R1(value)   (PICOP_S11S10_R1_Msk & ((value) << PICOP_S11S10_R1_Pos))
 
#define PICOP_S11S10_R2_Pos   16
 (PICOP_S11S10) Register 2
 
#define PICOP_S11S10_R2_Msk   (0xFFul << PICOP_S11S10_R2_Pos)
 
#define PICOP_S11S10_R2(value)   (PICOP_S11S10_R2_Msk & ((value) << PICOP_S11S10_R2_Pos))
 
#define PICOP_S11S10_R3_Pos   24
 (PICOP_S11S10) Register 3
 
#define PICOP_S11S10_R3_Msk   (0xFFul << PICOP_S11S10_R3_Pos)
 
#define PICOP_S11S10_R3(value)   (PICOP_S11S10_R3_Msk & ((value) << PICOP_S11S10_R3_Pos))
 
#define PICOP_S11S10_MASK   0xFFFFFFFFul
 (PICOP_S11S10) MASK Register
 
#define PICOP_LINK_OFFSET   0x0B8
 (PICOP_LINK offset) Link
 
#define PICOP_LINK_MASK   0xFFFFFFFFul
 (PICOP_LINK) MASK Register
 
#define PICOP_SP_OFFSET   0x0BC
 (PICOP_SP offset) Stack Pointer
 
#define PICOP_SP_R0_Pos   0
 (PICOP_SP) Register 0
 
#define PICOP_SP_R0_Msk   (0xFFul << PICOP_SP_R0_Pos)
 
#define PICOP_SP_R0(value)   (PICOP_SP_R0_Msk & ((value) << PICOP_SP_R0_Pos))
 
#define PICOP_SP_R1_Pos   8
 (PICOP_SP) Register 1
 
#define PICOP_SP_R1_Msk   (0xFFul << PICOP_SP_R1_Pos)
 
#define PICOP_SP_R1(value)   (PICOP_SP_R1_Msk & ((value) << PICOP_SP_R1_Pos))
 
#define PICOP_SP_R2_Pos   16
 (PICOP_SP) Register 2
 
#define PICOP_SP_R2_Msk   (0xFFul << PICOP_SP_R2_Pos)
 
#define PICOP_SP_R2(value)   (PICOP_SP_R2_Msk & ((value) << PICOP_SP_R2_Pos))
 
#define PICOP_SP_R3_Pos   24
 (PICOP_SP) Register 3
 
#define PICOP_SP_R3_Msk   (0xFFul << PICOP_SP_R3_Pos)
 
#define PICOP_SP_R3(value)   (PICOP_SP_R3_Msk & ((value) << PICOP_SP_R3_Pos))
 
#define PICOP_SP_MASK   0xFFFFFFFFul
 (PICOP_SP) MASK Register
 
#define PICOP_MMUFLASH_OFFSET   0x100
 (PICOP_MMUFLASH offset) MMU mapping for flash
 
#define PICOP_MMUFLASH_RESETVALUE   0x00000000ul
 (PICOP_MMUFLASH reset_value) MMU mapping for flash
 
#define PICOP_MMUFLASH_ADDRESS_Pos   0
 (PICOP_MMUFLASH) MMU Flash Address
 
#define PICOP_MMUFLASH_ADDRESS_Msk   (0xFul << PICOP_MMUFLASH_ADDRESS_Pos)
 
#define PICOP_MMUFLASH_ADDRESS(value)   (PICOP_MMUFLASH_ADDRESS_Msk & ((value) << PICOP_MMUFLASH_ADDRESS_Pos))
 
#define PICOP_MMUFLASH_MASK   0x0000000Ful
 (PICOP_MMUFLASH) MASK Register
 
#define PICOP_MMU0_OFFSET   0x118
 (PICOP_MMU0 offset) MMU mapping user 0
 
#define PICOP_MMU0_RESETVALUE   0x00000000ul
 (PICOP_MMU0 reset_value) MMU mapping user 0
 
#define PICOP_MMU0_ADDRESS_Pos   0
 (PICOP_MMU0) MMU User 0 Address
 
#define PICOP_MMU0_ADDRESS_Msk   (0xFFFFFFFFul << PICOP_MMU0_ADDRESS_Pos)
 
#define PICOP_MMU0_ADDRESS(value)   (PICOP_MMU0_ADDRESS_Msk & ((value) << PICOP_MMU0_ADDRESS_Pos))
 
#define PICOP_MMU0_MASK   0xFFFFFFFFul
 (PICOP_MMU0) MASK Register
 
#define PICOP_MMU1_OFFSET   0x11C
 (PICOP_MMU1 offset) MMU mapping user 1
 
#define PICOP_MMU1_RESETVALUE   0x00000000ul
 (PICOP_MMU1 reset_value) MMU mapping user 1
 
#define PICOP_MMU1_ADDRESS_Pos   0
 (PICOP_MMU1) MMU User 1 Address
 
#define PICOP_MMU1_ADDRESS_Msk   (0xFFFFFFFFul << PICOP_MMU1_ADDRESS_Pos)
 
#define PICOP_MMU1_ADDRESS(value)   (PICOP_MMU1_ADDRESS_Msk & ((value) << PICOP_MMU1_ADDRESS_Pos))
 
#define PICOP_MMU1_MASK   0xFFFFFFFFul
 (PICOP_MMU1) MASK Register
 
#define PICOP_MMUCTRL_OFFSET   0x120
 (PICOP_MMUCTRL offset) MMU Control
 
#define PICOP_MMUCTRL_RESETVALUE   0x00000000ul
 (PICOP_MMUCTRL reset_value) MMU Control
 
#define PICOP_MMUCTRL_IODIS_Pos   0
 (PICOP_MMUCTRL) Peripheral MMU Disable
 
#define PICOP_MMUCTRL_IODIS   (0x1ul << PICOP_MMUCTRL_IODIS_Pos)
 
#define PICOP_MMUCTRL_MEMDIS_Pos   1
 (PICOP_MMUCTRL) Memory MMU Disable
 
#define PICOP_MMUCTRL_MEMDIS   (0x1ul << PICOP_MMUCTRL_MEMDIS_Pos)
 
#define PICOP_MMUCTRL_MASK   0x00000003ul
 (PICOP_MMUCTRL) MASK Register
 
#define PICOP_ICACHE_OFFSET   0x180
 (PICOP_ICACHE offset) Instruction Cache Control
 
#define PICOP_ICACHE_RESETVALUE   0x00000000ul
 (PICOP_ICACHE reset_value) Instruction Cache Control
 
#define PICOP_ICACHE_CTRL_Pos   0
 (PICOP_ICACHE) Instruction Cache Control
 
#define PICOP_ICACHE_CTRL_Msk   (0x3ul << PICOP_ICACHE_CTRL_Pos)
 
#define PICOP_ICACHE_CTRL(value)   (PICOP_ICACHE_CTRL_Msk & ((value) << PICOP_ICACHE_CTRL_Pos))
 
#define PICOP_ICACHE_MASK   0x00000003ul
 (PICOP_ICACHE) MASK Register
 
#define PICOP_ICACHELRU_OFFSET   0x184
 (PICOP_ICACHELRU offset) Instruction Cache LRU
 
#define PICOP_ICACHELRU_RESETVALUE   0x00000000ul
 (PICOP_ICACHELRU reset_value) Instruction Cache LRU
 
#define PICOP_ICACHELRU_LRU0_Pos   0
 (PICOP_ICACHELRU) Instruction Cache LRU 0
 
#define PICOP_ICACHELRU_LRU0_Msk   (0x3ul << PICOP_ICACHELRU_LRU0_Pos)
 
#define PICOP_ICACHELRU_LRU0(value)   (PICOP_ICACHELRU_LRU0_Msk & ((value) << PICOP_ICACHELRU_LRU0_Pos))
 
#define PICOP_ICACHELRU_LRU1_Pos   2
 (PICOP_ICACHELRU) Instruction Cache LRU 1
 
#define PICOP_ICACHELRU_LRU1_Msk   (0x3ul << PICOP_ICACHELRU_LRU1_Pos)
 
#define PICOP_ICACHELRU_LRU1(value)   (PICOP_ICACHELRU_LRU1_Msk & ((value) << PICOP_ICACHELRU_LRU1_Pos))
 
#define PICOP_ICACHELRU_LRU2_Pos   4
 (PICOP_ICACHELRU) Instruction Cache LRU 2
 
#define PICOP_ICACHELRU_LRU2_Msk   (0x3ul << PICOP_ICACHELRU_LRU2_Pos)
 
#define PICOP_ICACHELRU_LRU2(value)   (PICOP_ICACHELRU_LRU2_Msk & ((value) << PICOP_ICACHELRU_LRU2_Pos))
 
#define PICOP_ICACHELRU_LRU3_Pos   6
 (PICOP_ICACHELRU) Instruction Cache LRU 3
 
#define PICOP_ICACHELRU_LRU3_Msk   (0x3ul << PICOP_ICACHELRU_LRU3_Pos)
 
#define PICOP_ICACHELRU_LRU3(value)   (PICOP_ICACHELRU_LRU3_Msk & ((value) << PICOP_ICACHELRU_LRU3_Pos))
 
#define PICOP_ICACHELRU_MASK   0x000000FFul
 (PICOP_ICACHELRU) MASK Register
 
#define PICOP_QOSCTRL_OFFSET   0x200
 (PICOP_QOSCTRL offset) QOS Control
 
#define PICOP_QOSCTRL_QOS_Pos   0
 (PICOP_QOSCTRL) Quality of Service
 
#define PICOP_QOSCTRL_QOS_Msk   (0x3ul << PICOP_QOSCTRL_QOS_Pos)
 
#define PICOP_QOSCTRL_QOS(value)   (PICOP_QOSCTRL_QOS_Msk & ((value) << PICOP_QOSCTRL_QOS_Pos))
 
#define PICOP_QOSCTRL_MASK   0x00000003ul
 (PICOP_QOSCTRL) MASK Register
 

Detailed Description

Component description for PICOP.

Copyright (c) 2015 Atmel Corporation. All rights reserved.

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Definition in file picop.h.

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