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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">OscctrlDpll Struct Reference</div> </div>
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<p><a class="el" href="structOscctrlDpll.html" title="OscctrlDpll hardware registers.">OscctrlDpll</a> hardware registers.
<a href="structOscctrlDpll.html#details">More...</a></p>
<p><code>#include <<a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>></code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:abcf1a25a3be1f40fd864723a908d94fc"><td class="memItemLeft" align="right" valign="top"><a id="abcf1a25a3be1f40fd864723a908d94fc"></a>
__IO <a class="el" href="unionOSCCTRL__DPLLCTRLA__Type.html">OSCCTRL_DPLLCTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrlDpll.html#abcf1a25a3be1f40fd864723a908d94fc">DPLLCTRLA</a></td></tr>
<tr class="memdesc:abcf1a25a3be1f40fd864723a908d94fc"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 8) DPLL Control A. <br /></td></tr>
<tr class="separator:abcf1a25a3be1f40fd864723a908d94fc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1df28a99c50d39221da31a9a103fe797"><td class="memItemLeft" align="right" valign="top"><a id="a1df28a99c50d39221da31a9a103fe797"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x3]</td></tr>
<tr class="separator:a1df28a99c50d39221da31a9a103fe797"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a927b7cc68a09013124bd6e75a18036fe"><td class="memItemLeft" align="right" valign="top"><a id="a927b7cc68a09013124bd6e75a18036fe"></a>
__IO <a class="el" href="unionOSCCTRL__DPLLRATIO__Type.html">OSCCTRL_DPLLRATIO_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrlDpll.html#a927b7cc68a09013124bd6e75a18036fe">DPLLRATIO</a></td></tr>
<tr class="memdesc:a927b7cc68a09013124bd6e75a18036fe"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 32) DPLL Ratio Control. <br /></td></tr>
<tr class="separator:a927b7cc68a09013124bd6e75a18036fe"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aced92a08cb7459d7008309378121e673"><td class="memItemLeft" align="right" valign="top"><a id="aced92a08cb7459d7008309378121e673"></a>
__IO <a class="el" href="unionOSCCTRL__DPLLCTRLB__Type.html">OSCCTRL_DPLLCTRLB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrlDpll.html#aced92a08cb7459d7008309378121e673">DPLLCTRLB</a></td></tr>
<tr class="memdesc:aced92a08cb7459d7008309378121e673"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 32) DPLL Control B. <br /></td></tr>
<tr class="separator:aced92a08cb7459d7008309378121e673"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ab10e65eef739e050ecde226adc98a2c5"><td class="memItemLeft" align="right" valign="top"><a id="ab10e65eef739e050ecde226adc98a2c5"></a>
__I <a class="el" href="unionOSCCTRL__DPLLSYNCBUSY__Type.html">OSCCTRL_DPLLSYNCBUSY_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrlDpll.html#ab10e65eef739e050ecde226adc98a2c5">DPLLSYNCBUSY</a></td></tr>
<tr class="memdesc:ab10e65eef739e050ecde226adc98a2c5"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/ 32) DPLL Synchronization Busy. <br /></td></tr>
<tr class="separator:ab10e65eef739e050ecde226adc98a2c5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa135801aa9692f3ddaec87315d253c3e"><td class="memItemLeft" align="right" valign="top"><a id="aa135801aa9692f3ddaec87315d253c3e"></a>
__I <a class="el" href="unionOSCCTRL__DPLLSTATUS__Type.html">OSCCTRL_DPLLSTATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structOscctrlDpll.html#aa135801aa9692f3ddaec87315d253c3e">DPLLSTATUS</a></td></tr>
<tr class="memdesc:aa135801aa9692f3ddaec87315d253c3e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/ 32) DPLL Status. <br /></td></tr>
<tr class="separator:aa135801aa9692f3ddaec87315d253c3e"><td class="memSeparator" colspan="2"> </td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p><a class="el" href="structOscctrlDpll.html" title="OscctrlDpll hardware registers.">OscctrlDpll</a> hardware registers. </p>
<p class="definition">Definition at line <a class="el" href="component_2oscctrl_8h_source.html#l00759">759</a> of file <a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a>.</p>
</div><hr/>The documentation for this struct was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2oscctrl_8h_source.html">oscctrl.h</a></li>
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