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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Nvmctrl Struct Reference</div> </div>
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<p>NVMCTRL APB hardware registers.
<a href="structNvmctrl.html#details">More...</a></p>
<p><code>#include <<a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>></code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a7e8613746f6e54c152a3eb2405ab30ef"><td class="memItemLeft" align="right" valign="top"><a id="a7e8613746f6e54c152a3eb2405ab30ef"></a>
__IO <a class="el" href="unionNVMCTRL__CTRLA__Type.html">NVMCTRL_CTRLA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#a7e8613746f6e54c152a3eb2405ab30ef">CTRLA</a></td></tr>
<tr class="memdesc:a7e8613746f6e54c152a3eb2405ab30ef"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 16) Control A. <br /></td></tr>
<tr class="separator:a7e8613746f6e54c152a3eb2405ab30ef"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aba0e2a481e283b58cdadcdd7b2fd4c00"><td class="memItemLeft" align="right" valign="top"><a id="aba0e2a481e283b58cdadcdd7b2fd4c00"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x2]</td></tr>
<tr class="separator:aba0e2a481e283b58cdadcdd7b2fd4c00"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa229892d3c632b4304cbd8050d1cc439"><td class="memItemLeft" align="right" valign="top"><a id="aa229892d3c632b4304cbd8050d1cc439"></a>
__O <a class="el" href="unionNVMCTRL__CTRLB__Type.html">NVMCTRL_CTRLB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#aa229892d3c632b4304cbd8050d1cc439">CTRLB</a></td></tr>
<tr class="memdesc:aa229892d3c632b4304cbd8050d1cc439"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 ( /W 16) Control B. <br /></td></tr>
<tr class="separator:aa229892d3c632b4304cbd8050d1cc439"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a62759d43d40f4141a894f58c480c2143"><td class="memItemLeft" align="right" valign="top"><a id="a62759d43d40f4141a894f58c480c2143"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x2]</td></tr>
<tr class="separator:a62759d43d40f4141a894f58c480c2143"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5ab09d2bf2f4d18b43b46cadf7d17657"><td class="memItemLeft" align="right" valign="top"><a id="a5ab09d2bf2f4d18b43b46cadf7d17657"></a>
__I <a class="el" href="unionNVMCTRL__PARAM__Type.html">NVMCTRL_PARAM_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#a5ab09d2bf2f4d18b43b46cadf7d17657">PARAM</a></td></tr>
<tr class="memdesc:a5ab09d2bf2f4d18b43b46cadf7d17657"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/ 32) NVM Parameter. <br /></td></tr>
<tr class="separator:a5ab09d2bf2f4d18b43b46cadf7d17657"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a7c7db1c3ef2a8a290f214ae45db87a83"><td class="memItemLeft" align="right" valign="top"><a id="a7c7db1c3ef2a8a290f214ae45db87a83"></a>
__IO <a class="el" href="unionNVMCTRL__INTENCLR__Type.html">NVMCTRL_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#a7c7db1c3ef2a8a290f214ae45db87a83">INTENCLR</a></td></tr>
<tr class="memdesc:a7c7db1c3ef2a8a290f214ae45db87a83"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0C (R/W 16) Interrupt Enable Clear. <br /></td></tr>
<tr class="separator:a7c7db1c3ef2a8a290f214ae45db87a83"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a47dd09a378257903197d6d6e47f8ff2e"><td class="memItemLeft" align="right" valign="top"><a id="a47dd09a378257903197d6d6e47f8ff2e"></a>
__IO <a class="el" href="unionNVMCTRL__INTENSET__Type.html">NVMCTRL_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#a47dd09a378257903197d6d6e47f8ff2e">INTENSET</a></td></tr>
<tr class="memdesc:a47dd09a378257903197d6d6e47f8ff2e"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x0E (R/W 16) Interrupt Enable Set. <br /></td></tr>
<tr class="separator:a47dd09a378257903197d6d6e47f8ff2e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa275ec3e71b3fd5455175d593b317548"><td class="memItemLeft" align="right" valign="top"><a id="aa275ec3e71b3fd5455175d593b317548"></a>
__IO <a class="el" href="unionNVMCTRL__INTFLAG__Type.html">NVMCTRL_INTFLAG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#aa275ec3e71b3fd5455175d593b317548">INTFLAG</a></td></tr>
<tr class="memdesc:aa275ec3e71b3fd5455175d593b317548"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/W 16) Interrupt Flag Status and Clear. <br /></td></tr>
<tr class="separator:aa275ec3e71b3fd5455175d593b317548"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a03025c297f9b114679d6f596715a7b78"><td class="memItemLeft" align="right" valign="top"><a id="a03025c297f9b114679d6f596715a7b78"></a>
__I <a class="el" href="unionNVMCTRL__STATUS__Type.html">NVMCTRL_STATUS_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#a03025c297f9b114679d6f596715a7b78">STATUS</a></td></tr>
<tr class="memdesc:a03025c297f9b114679d6f596715a7b78"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x12 (R/ 16) Status. <br /></td></tr>
<tr class="separator:a03025c297f9b114679d6f596715a7b78"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a839fdde23536d0554617f373c57e702f"><td class="memItemLeft" align="right" valign="top"><a id="a839fdde23536d0554617f373c57e702f"></a>
__IO <a class="el" href="unionNVMCTRL__ADDR__Type.html">NVMCTRL_ADDR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#a839fdde23536d0554617f373c57e702f">ADDR</a></td></tr>
<tr class="memdesc:a839fdde23536d0554617f373c57e702f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 32) Address. <br /></td></tr>
<tr class="separator:a839fdde23536d0554617f373c57e702f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a4b833eeaf5a4707c0f6cbacada4c8138"><td class="memItemLeft" align="right" valign="top"><a id="a4b833eeaf5a4707c0f6cbacada4c8138"></a>
__I <a class="el" href="unionNVMCTRL__RUNLOCK__Type.html">NVMCTRL_RUNLOCK_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#a4b833eeaf5a4707c0f6cbacada4c8138">RUNLOCK</a></td></tr>
<tr class="memdesc:a4b833eeaf5a4707c0f6cbacada4c8138"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x18 (R/ 32) Lock Section. <br /></td></tr>
<tr class="separator:a4b833eeaf5a4707c0f6cbacada4c8138"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:acb849d52e34bcfee0ea43c39e06c7a64"><td class="memItemLeft" align="right" valign="top"><a id="acb849d52e34bcfee0ea43c39e06c7a64"></a>
__I <a class="el" href="unionNVMCTRL__PBLDATA__Type.html">NVMCTRL_PBLDATA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#acb849d52e34bcfee0ea43c39e06c7a64">PBLDATA</a> [2]</td></tr>
<tr class="memdesc:acb849d52e34bcfee0ea43c39e06c7a64"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/ 32) Page Buffer Load Data x. <br /></td></tr>
<tr class="separator:acb849d52e34bcfee0ea43c39e06c7a64"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9012a764338f074e9a4a340fdc310614"><td class="memItemLeft" align="right" valign="top"><a id="a9012a764338f074e9a4a340fdc310614"></a>
__I <a class="el" href="unionNVMCTRL__ECCERR__Type.html">NVMCTRL_ECCERR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#a9012a764338f074e9a4a340fdc310614">ECCERR</a></td></tr>
<tr class="memdesc:a9012a764338f074e9a4a340fdc310614"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x24 (R/ 32) ECC Error Status Register. <br /></td></tr>
<tr class="separator:a9012a764338f074e9a4a340fdc310614"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a0d34c72c814368719cb2266f4a4e4059"><td class="memItemLeft" align="right" valign="top"><a id="a0d34c72c814368719cb2266f4a4e4059"></a>
__IO <a class="el" href="unionNVMCTRL__DBGCTRL__Type.html">NVMCTRL_DBGCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#a0d34c72c814368719cb2266f4a4e4059">DBGCTRL</a></td></tr>
<tr class="memdesc:a0d34c72c814368719cb2266f4a4e4059"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x28 (R/W 8) Debug Control. <br /></td></tr>
<tr class="separator:a0d34c72c814368719cb2266f4a4e4059"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a9e6c92e62abb8feff364e1f3559f2bc0"><td class="memItemLeft" align="right" valign="top"><a id="a9e6c92e62abb8feff364e1f3559f2bc0"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x1]</td></tr>
<tr class="separator:a9e6c92e62abb8feff364e1f3559f2bc0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a83918188239d1598f5abbcc3bc804110"><td class="memItemLeft" align="right" valign="top"><a id="a83918188239d1598f5abbcc3bc804110"></a>
__IO <a class="el" href="unionNVMCTRL__SEECFG__Type.html">NVMCTRL_SEECFG_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#a83918188239d1598f5abbcc3bc804110">SEECFG</a></td></tr>
<tr class="memdesc:a83918188239d1598f5abbcc3bc804110"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2A (R/W 8) SmartEEPROM Configuration Register. <br /></td></tr>
<tr class="separator:a83918188239d1598f5abbcc3bc804110"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a202269c16a8c1b799aa1ac80bf5f3f9b"><td class="memItemLeft" align="right" valign="top"><a id="a202269c16a8c1b799aa1ac80bf5f3f9b"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved4</b> [0x1]</td></tr>
<tr class="separator:a202269c16a8c1b799aa1ac80bf5f3f9b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac7ffb9869923d722cdbb8d5cf66778e2"><td class="memItemLeft" align="right" valign="top"><a id="ac7ffb9869923d722cdbb8d5cf66778e2"></a>
__I <a class="el" href="unionNVMCTRL__SEESTAT__Type.html">NVMCTRL_SEESTAT_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structNvmctrl.html#ac7ffb9869923d722cdbb8d5cf66778e2">SEESTAT</a></td></tr>
<tr class="memdesc:ac7ffb9869923d722cdbb8d5cf66778e2"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x2C (R/ 32) SmartEEPROM Status Register. <br /></td></tr>
<tr class="separator:ac7ffb9869923d722cdbb8d5cf66778e2"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>NVMCTRL APB hardware registers. </p>
<p class="definition">Definition at line <a class="el" href="component_2nvmctrl_8h_source.html#l00580">580</a> of file <a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a>.</p>
</div><hr/>The documentation for this struct was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2nvmctrl_8h_source.html">nvmctrl.h</a></li>
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