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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">freqm.h File Reference</div> </div>
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<p>Instance description for FREQM.
<a href="#details">More...</a></p>
<p><a href="instance_2freqm_8h_source.html">Go to the source code of this file.</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:a28d9b0e7e486e6787302acff9e92f979"><td class="memItemLeft" align="right" valign="top"><a id="a28d9b0e7e486e6787302acff9e92f979"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2freqm_8h.html#a28d9b0e7e486e6787302acff9e92f979">REG_FREQM_CTRLA</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40002C00UL)</td></tr>
<tr class="memdesc:a28d9b0e7e486e6787302acff9e92f979"><td class="mdescLeft"> </td><td class="mdescRight">(FREQM) Control A Register <br /></td></tr>
<tr class="separator:a28d9b0e7e486e6787302acff9e92f979"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a1b888918b4ba7ad74117bdbc27d9fa29"><td class="memItemLeft" align="right" valign="top"><a id="a1b888918b4ba7ad74117bdbc27d9fa29"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2freqm_8h.html#a1b888918b4ba7ad74117bdbc27d9fa29">REG_FREQM_CTRLB</a>   (*(<a class="el" href="same54n19a_8h.html#a5e336e5a36ee12ebeafb021108e5275b">WoReg8</a> *)0x40002C01UL)</td></tr>
<tr class="memdesc:a1b888918b4ba7ad74117bdbc27d9fa29"><td class="mdescLeft"> </td><td class="mdescRight">(FREQM) Control B Register <br /></td></tr>
<tr class="separator:a1b888918b4ba7ad74117bdbc27d9fa29"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:add5a82bfe69dc3d6e6e6e0940cb89266"><td class="memItemLeft" align="right" valign="top"><a id="add5a82bfe69dc3d6e6e6e0940cb89266"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2freqm_8h.html#add5a82bfe69dc3d6e6e6e0940cb89266">REG_FREQM_CFGA</a>   (*(<a class="el" href="same54n19a_8h.html#acce07556c80fc352ae607f225f19fed5">RwReg16</a>*)0x40002C02UL)</td></tr>
<tr class="memdesc:add5a82bfe69dc3d6e6e6e0940cb89266"><td class="mdescLeft"> </td><td class="mdescRight">(FREQM) Config A register <br /></td></tr>
<tr class="separator:add5a82bfe69dc3d6e6e6e0940cb89266"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5fbfa3b60d44017ebef269ba971c5d90"><td class="memItemLeft" align="right" valign="top"><a id="a5fbfa3b60d44017ebef269ba971c5d90"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2freqm_8h.html#a5fbfa3b60d44017ebef269ba971c5d90">REG_FREQM_INTENCLR</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40002C08UL)</td></tr>
<tr class="memdesc:a5fbfa3b60d44017ebef269ba971c5d90"><td class="mdescLeft"> </td><td class="mdescRight">(FREQM) Interrupt Enable Clear Register <br /></td></tr>
<tr class="separator:a5fbfa3b60d44017ebef269ba971c5d90"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa1e490f91baa6c87e0d00307f18c864e"><td class="memItemLeft" align="right" valign="top"><a id="aa1e490f91baa6c87e0d00307f18c864e"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2freqm_8h.html#aa1e490f91baa6c87e0d00307f18c864e">REG_FREQM_INTENSET</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40002C09UL)</td></tr>
<tr class="memdesc:aa1e490f91baa6c87e0d00307f18c864e"><td class="mdescLeft"> </td><td class="mdescRight">(FREQM) Interrupt Enable Set Register <br /></td></tr>
<tr class="separator:aa1e490f91baa6c87e0d00307f18c864e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a22c51e68d8980611844bf6920f7ec7b9"><td class="memItemLeft" align="right" valign="top"><a id="a22c51e68d8980611844bf6920f7ec7b9"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2freqm_8h.html#a22c51e68d8980611844bf6920f7ec7b9">REG_FREQM_INTFLAG</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40002C0AUL)</td></tr>
<tr class="memdesc:a22c51e68d8980611844bf6920f7ec7b9"><td class="mdescLeft"> </td><td class="mdescRight">(FREQM) Interrupt Flag Register <br /></td></tr>
<tr class="separator:a22c51e68d8980611844bf6920f7ec7b9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a43c4cf22f1be89d02848d673e9c0fd75"><td class="memItemLeft" align="right" valign="top"><a id="a43c4cf22f1be89d02848d673e9c0fd75"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2freqm_8h.html#a43c4cf22f1be89d02848d673e9c0fd75">REG_FREQM_STATUS</a>   (*(<a class="el" href="same54n19a_8h.html#ae361754be775bb192f85821d3ab33c17">RwReg8</a> *)0x40002C0BUL)</td></tr>
<tr class="memdesc:a43c4cf22f1be89d02848d673e9c0fd75"><td class="mdescLeft"> </td><td class="mdescRight">(FREQM) Status Register <br /></td></tr>
<tr class="separator:a43c4cf22f1be89d02848d673e9c0fd75"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a882e59fb2e502f2e813a26668fc5995c"><td class="memItemLeft" align="right" valign="top"><a id="a882e59fb2e502f2e813a26668fc5995c"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2freqm_8h.html#a882e59fb2e502f2e813a26668fc5995c">REG_FREQM_SYNCBUSY</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x40002C0CUL)</td></tr>
<tr class="memdesc:a882e59fb2e502f2e813a26668fc5995c"><td class="mdescLeft"> </td><td class="mdescRight">(FREQM) Synchronization Busy Register <br /></td></tr>
<tr class="separator:a882e59fb2e502f2e813a26668fc5995c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa89e9345e3093405ebbbcf803b2e8a2b"><td class="memItemLeft" align="right" valign="top"><a id="aa89e9345e3093405ebbbcf803b2e8a2b"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="instance_2freqm_8h.html#aa89e9345e3093405ebbbcf803b2e8a2b">REG_FREQM_VALUE</a>   (*(<a class="el" href="same54n19a_8h.html#a5d556f8391af4141be23f7334ac9dd68">RoReg</a> *)0x40002C10UL)</td></tr>
<tr class="memdesc:aa89e9345e3093405ebbbcf803b2e8a2b"><td class="mdescLeft"> </td><td class="mdescRight">(FREQM) Count Value Register <br /></td></tr>
<tr class="separator:aa89e9345e3093405ebbbcf803b2e8a2b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a5b33edaaeeb97524bd2e6e2b7eef207d"><td class="memItemLeft" align="right" valign="top"><a id="a5b33edaaeeb97524bd2e6e2b7eef207d"></a>
#define </td><td class="memItemRight" valign="bottom"><b>FREQM_GCLK_ID_MSR</b>   5</td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>Instance description for FREQM. </p>
<p>Copyright (c) 2019 Microchip Technology Inc.</p>
<p>\asf_license_start </p>
<p class="definition">Definition in file <a class="el" href="instance_2freqm_8h_source.html">freqm.h</a>.</p>
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