SAME54P20A Test Project
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Instance description for PAC. More...
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Macros | |
#define | REG_PAC_WRCTRL (*(RwReg *)0x40000000UL) |
(PAC) Write control | |
#define | REG_PAC_EVCTRL (*(RwReg8 *)0x40000004UL) |
(PAC) Event control | |
#define | REG_PAC_INTENCLR (*(RwReg8 *)0x40000008UL) |
(PAC) Interrupt enable clear | |
#define | REG_PAC_INTENSET (*(RwReg8 *)0x40000009UL) |
(PAC) Interrupt enable set | |
#define | REG_PAC_INTFLAGAHB (*(RwReg *)0x40000010UL) |
(PAC) Bridge interrupt flag status | |
#define | REG_PAC_INTFLAGA (*(RwReg *)0x40000014UL) |
(PAC) Peripheral interrupt flag status - Bridge A | |
#define | REG_PAC_INTFLAGB (*(RwReg *)0x40000018UL) |
(PAC) Peripheral interrupt flag status - Bridge B | |
#define | REG_PAC_INTFLAGC (*(RwReg *)0x4000001CUL) |
(PAC) Peripheral interrupt flag status - Bridge C | |
#define | REG_PAC_INTFLAGD (*(RwReg *)0x40000020UL) |
(PAC) Peripheral interrupt flag status - Bridge D | |
#define | REG_PAC_STATUSA (*(RoReg *)0x40000034UL) |
(PAC) Peripheral write protection status - Bridge A | |
#define | REG_PAC_STATUSB (*(RoReg *)0x40000038UL) |
(PAC) Peripheral write protection status - Bridge B | |
#define | REG_PAC_STATUSC (*(RoReg *)0x4000003CUL) |
(PAC) Peripheral write protection status - Bridge C | |
#define | REG_PAC_STATUSD (*(RoReg *)0x40000040UL) |
(PAC) Peripheral write protection status - Bridge D | |
#define | PAC_CLK_AHB_DOMAIN |
#define | PAC_CLK_AHB_ID 12 |
#define | PAC_HPB_NUM 4 |
Instance description for PAC.
Copyright (c) 2019 Microchip Technology Inc.
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Definition in file pac.h.