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SAME54P20A Test Project
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QSPI APB hardware registers. More...
#include <qspi.h>
Data Fields | |
| __IO QSPI_CTRLA_Type | CTRLA |
| Offset: 0x00 (R/W 32) Control A. | |
| __IO QSPI_CTRLB_Type | CTRLB |
| Offset: 0x04 (R/W 32) Control B. | |
| __IO QSPI_BAUD_Type | BAUD |
| Offset: 0x08 (R/W 32) Baud Rate. | |
| __I QSPI_RXDATA_Type | RXDATA |
| Offset: 0x0C (R/ 32) Receive Data. | |
| __O QSPI_TXDATA_Type | TXDATA |
| Offset: 0x10 ( /W 32) Transmit Data. | |
| __IO QSPI_INTENCLR_Type | INTENCLR |
| Offset: 0x14 (R/W 32) Interrupt Enable Clear. | |
| __IO QSPI_INTENSET_Type | INTENSET |
| Offset: 0x18 (R/W 32) Interrupt Enable Set. | |
| __IO QSPI_INTFLAG_Type | INTFLAG |
| Offset: 0x1C (R/W 32) Interrupt Flag Status and Clear. | |
| __I QSPI_STATUS_Type | STATUS |
| Offset: 0x20 (R/ 32) Status Register. | |
| RoReg8 | Reserved1 [0xC] |
| __IO QSPI_INSTRADDR_Type | INSTRADDR |
| Offset: 0x30 (R/W 32) Instruction Address. | |
| __IO QSPI_INSTRCTRL_Type | INSTRCTRL |
| Offset: 0x34 (R/W 32) Instruction Code. | |
| __IO QSPI_INSTRFRAME_Type | INSTRFRAME |
| Offset: 0x38 (R/W 32) Instruction Frame. | |
| RoReg8 | Reserved2 [0x4] |
| __IO QSPI_SCRAMBCTRL_Type | SCRAMBCTRL |
| Offset: 0x40 (R/W 32) Scrambling Mode. | |
| __O QSPI_SCRAMBKEY_Type | SCRAMBKEY |
| Offset: 0x44 ( /W 32) Scrambling Key. | |
1.8.20