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<a href="#pub-attribs">Data Fields</a> </div>
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<div class="title">Pac Struct Reference</div> </div>
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<p>PAC hardware registers.
<a href="structPac.html#details">More...</a></p>
<p><code>#include <<a class="el" href="component_2pac_8h_source.html">pac.h</a>></code></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a4b2496dfffd2d47da5afc77c0b259338"><td class="memItemLeft" align="right" valign="top"><a id="a4b2496dfffd2d47da5afc77c0b259338"></a>
__IO <a class="el" href="unionPAC__WRCTRL__Type.html">PAC_WRCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#a4b2496dfffd2d47da5afc77c0b259338">WRCTRL</a></td></tr>
<tr class="memdesc:a4b2496dfffd2d47da5afc77c0b259338"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x00 (R/W 32) Write control. <br /></td></tr>
<tr class="separator:a4b2496dfffd2d47da5afc77c0b259338"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a51f5feac918430a1638cc4184942003f"><td class="memItemLeft" align="right" valign="top"><a id="a51f5feac918430a1638cc4184942003f"></a>
__IO <a class="el" href="unionPAC__EVCTRL__Type.html">PAC_EVCTRL_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#a51f5feac918430a1638cc4184942003f">EVCTRL</a></td></tr>
<tr class="memdesc:a51f5feac918430a1638cc4184942003f"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x04 (R/W 8) Event control. <br /></td></tr>
<tr class="separator:a51f5feac918430a1638cc4184942003f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aef02b37a1faac8a0d93c1cd5c567913d"><td class="memItemLeft" align="right" valign="top"><a id="aef02b37a1faac8a0d93c1cd5c567913d"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved1</b> [0x3]</td></tr>
<tr class="separator:aef02b37a1faac8a0d93c1cd5c567913d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3c9266e1f270edd8e6eebc44cdce1005"><td class="memItemLeft" align="right" valign="top"><a id="a3c9266e1f270edd8e6eebc44cdce1005"></a>
__IO <a class="el" href="unionPAC__INTENCLR__Type.html">PAC_INTENCLR_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#a3c9266e1f270edd8e6eebc44cdce1005">INTENCLR</a></td></tr>
<tr class="memdesc:a3c9266e1f270edd8e6eebc44cdce1005"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x08 (R/W 8) Interrupt enable clear. <br /></td></tr>
<tr class="separator:a3c9266e1f270edd8e6eebc44cdce1005"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a710a1d05491b5b53c87e1ad8f98c178b"><td class="memItemLeft" align="right" valign="top"><a id="a710a1d05491b5b53c87e1ad8f98c178b"></a>
__IO <a class="el" href="unionPAC__INTENSET__Type.html">PAC_INTENSET_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#a710a1d05491b5b53c87e1ad8f98c178b">INTENSET</a></td></tr>
<tr class="memdesc:a710a1d05491b5b53c87e1ad8f98c178b"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x09 (R/W 8) Interrupt enable set. <br /></td></tr>
<tr class="separator:a710a1d05491b5b53c87e1ad8f98c178b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac631e37dd7df3e4148fb059bf2d08f79"><td class="memItemLeft" align="right" valign="top"><a id="ac631e37dd7df3e4148fb059bf2d08f79"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved2</b> [0x6]</td></tr>
<tr class="separator:ac631e37dd7df3e4148fb059bf2d08f79"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a43204082738d35bfd321db9f92960be4"><td class="memItemLeft" align="right" valign="top"><a id="a43204082738d35bfd321db9f92960be4"></a>
__IO <a class="el" href="unionPAC__INTFLAGAHB__Type.html">PAC_INTFLAGAHB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#a43204082738d35bfd321db9f92960be4">INTFLAGAHB</a></td></tr>
<tr class="memdesc:a43204082738d35bfd321db9f92960be4"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x10 (R/W 32) Bridge interrupt flag status. <br /></td></tr>
<tr class="separator:a43204082738d35bfd321db9f92960be4"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a88c4b94bbb43bfc8bc6ef1c8315dd4b3"><td class="memItemLeft" align="right" valign="top"><a id="a88c4b94bbb43bfc8bc6ef1c8315dd4b3"></a>
__IO <a class="el" href="unionPAC__INTFLAGA__Type.html">PAC_INTFLAGA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#a88c4b94bbb43bfc8bc6ef1c8315dd4b3">INTFLAGA</a></td></tr>
<tr class="memdesc:a88c4b94bbb43bfc8bc6ef1c8315dd4b3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x14 (R/W 32) Peripheral interrupt flag status - Bridge A. <br /></td></tr>
<tr class="separator:a88c4b94bbb43bfc8bc6ef1c8315dd4b3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:aa24c383457a9d02e95b5338afd45a1d0"><td class="memItemLeft" align="right" valign="top"><a id="aa24c383457a9d02e95b5338afd45a1d0"></a>
__IO <a class="el" href="unionPAC__INTFLAGB__Type.html">PAC_INTFLAGB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#aa24c383457a9d02e95b5338afd45a1d0">INTFLAGB</a></td></tr>
<tr class="memdesc:aa24c383457a9d02e95b5338afd45a1d0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x18 (R/W 32) Peripheral interrupt flag status - Bridge B. <br /></td></tr>
<tr class="separator:aa24c383457a9d02e95b5338afd45a1d0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3233539abbe44636f3206332631e017c"><td class="memItemLeft" align="right" valign="top"><a id="a3233539abbe44636f3206332631e017c"></a>
__IO <a class="el" href="unionPAC__INTFLAGC__Type.html">PAC_INTFLAGC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#a3233539abbe44636f3206332631e017c">INTFLAGC</a></td></tr>
<tr class="memdesc:a3233539abbe44636f3206332631e017c"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x1C (R/W 32) Peripheral interrupt flag status - Bridge C. <br /></td></tr>
<tr class="separator:a3233539abbe44636f3206332631e017c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac6d1478ff1d24eb47f9cb43edeb282b3"><td class="memItemLeft" align="right" valign="top"><a id="ac6d1478ff1d24eb47f9cb43edeb282b3"></a>
__IO <a class="el" href="unionPAC__INTFLAGD__Type.html">PAC_INTFLAGD_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#ac6d1478ff1d24eb47f9cb43edeb282b3">INTFLAGD</a></td></tr>
<tr class="memdesc:ac6d1478ff1d24eb47f9cb43edeb282b3"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x20 (R/W 32) Peripheral interrupt flag status - Bridge D. <br /></td></tr>
<tr class="separator:ac6d1478ff1d24eb47f9cb43edeb282b3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ac443a252b101a5839b44de53e45428e3"><td class="memItemLeft" align="right" valign="top"><a id="ac443a252b101a5839b44de53e45428e3"></a>
<a class="el" href="same54n19a_8h.html#a0d957f1433aaf5d70e4dc2b68288442d">RoReg8</a> </td><td class="memItemRight" valign="bottom"><b>Reserved3</b> [0x10]</td></tr>
<tr class="separator:ac443a252b101a5839b44de53e45428e3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:af6f8aa5f0054587a09947c68a321c229"><td class="memItemLeft" align="right" valign="top"><a id="af6f8aa5f0054587a09947c68a321c229"></a>
__I <a class="el" href="unionPAC__STATUSA__Type.html">PAC_STATUSA_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#af6f8aa5f0054587a09947c68a321c229">STATUSA</a></td></tr>
<tr class="memdesc:af6f8aa5f0054587a09947c68a321c229"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x34 (R/ 32) Peripheral write protection status - Bridge A. <br /></td></tr>
<tr class="separator:af6f8aa5f0054587a09947c68a321c229"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:a3a9b9a4ca0984c013fd139811a0a2ba0"><td class="memItemLeft" align="right" valign="top"><a id="a3a9b9a4ca0984c013fd139811a0a2ba0"></a>
__I <a class="el" href="unionPAC__STATUSB__Type.html">PAC_STATUSB_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#a3a9b9a4ca0984c013fd139811a0a2ba0">STATUSB</a></td></tr>
<tr class="memdesc:a3a9b9a4ca0984c013fd139811a0a2ba0"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x38 (R/ 32) Peripheral write protection status - Bridge B. <br /></td></tr>
<tr class="separator:a3a9b9a4ca0984c013fd139811a0a2ba0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:abf41a3781084f01e0d278300cb763f29"><td class="memItemLeft" align="right" valign="top"><a id="abf41a3781084f01e0d278300cb763f29"></a>
__I <a class="el" href="unionPAC__STATUSC__Type.html">PAC_STATUSC_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#abf41a3781084f01e0d278300cb763f29">STATUSC</a></td></tr>
<tr class="memdesc:abf41a3781084f01e0d278300cb763f29"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x3C (R/ 32) Peripheral write protection status - Bridge C. <br /></td></tr>
<tr class="separator:abf41a3781084f01e0d278300cb763f29"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:afaf2caaf5e4105c9a4cd93d998976793"><td class="memItemLeft" align="right" valign="top"><a id="afaf2caaf5e4105c9a4cd93d998976793"></a>
__I <a class="el" href="unionPAC__STATUSD__Type.html">PAC_STATUSD_Type</a> </td><td class="memItemRight" valign="bottom"><a class="el" href="structPac.html#afaf2caaf5e4105c9a4cd93d998976793">STATUSD</a></td></tr>
<tr class="memdesc:afaf2caaf5e4105c9a4cd93d998976793"><td class="mdescLeft"> </td><td class="mdescRight">Offset: 0x40 (R/ 32) Peripheral write protection status - Bridge D. <br /></td></tr>
<tr class="separator:afaf2caaf5e4105c9a4cd93d998976793"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock"><p>PAC hardware registers. </p>
<p class="definition">Definition at line <a class="el" href="component_2pac_8h_source.html#l00664">664</a> of file <a class="el" href="component_2pac_8h_source.html">pac.h</a>.</p>
</div><hr/>The documentation for this struct was generated from the following file:<ul>
<li>/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/<a class="el" href="component_2pac_8h_source.html">pac.h</a></li>
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