Data Fields
struct {
uint16_t __pad0__:2

uint16_t AUTOWS:1

uint16_t SUSPEN:1

uint16_t WMODE:2

uint16_t PRM:2

uint16_t RWS:4

uint16_t AHBNS0:1

uint16_t AHBNS1:1

uint16_t CACHEDIS0:1

uint16_t CACHEDIS1:1

}	bit

uint16_t	reg

Detailed Description

Definition at line 44 of file nvmctrl.h.

Field Documentation

◆ pad0

uint16_t NVMCTRL_CTRLA_Type::__pad0__

bit: 0.. 1 Reserved

Definition at line 46 of file nvmctrl.h.

◆ AHBNS0

uint16_t NVMCTRL_CTRLA_Type::AHBNS0

bit: 12 Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated

Definition at line 52 of file nvmctrl.h.

◆ AHBNS1

uint16_t NVMCTRL_CTRLA_Type::AHBNS1

bit: 13 Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated

Definition at line 53 of file nvmctrl.h.

◆ AUTOWS

uint16_t NVMCTRL_CTRLA_Type::AUTOWS

bit: 2 Auto Wait State Enable

Definition at line 47 of file nvmctrl.h.

◆ bit

struct { ... } NVMCTRL_CTRLA_Type::bit

Structure used for bit access

◆ CACHEDIS0

uint16_t NVMCTRL_CTRLA_Type::CACHEDIS0

bit: 14 AHB0 Cache Disable

Definition at line 54 of file nvmctrl.h.

◆ CACHEDIS1

uint16_t NVMCTRL_CTRLA_Type::CACHEDIS1

bit: 15 AHB1 Cache Disable

Definition at line 55 of file nvmctrl.h.

◆ PRM

uint16_t NVMCTRL_CTRLA_Type::PRM

bit: 6.. 7 Power Reduction Mode during Sleep

Definition at line 50 of file nvmctrl.h.

◆ reg

uint16_t NVMCTRL_CTRLA_Type::reg

Type used for register access

Definition at line 57 of file nvmctrl.h.

◆ RWS

uint16_t NVMCTRL_CTRLA_Type::RWS

bit: 8..11 NVM Read Wait States

Definition at line 51 of file nvmctrl.h.

◆ SUSPEN

uint16_t NVMCTRL_CTRLA_Type::SUSPEN

bit: 3 Suspend Enable

Definition at line 48 of file nvmctrl.h.

◆ WMODE

uint16_t NVMCTRL_CTRLA_Type::WMODE

bit: 4.. 5 Write Mode

Definition at line 49 of file nvmctrl.h.

The documentation for this union was generated from the following file:

/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/nvmctrl.h

Data Fields