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SAME54P20A Test Project
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TC_COUNT32 hardware registers. More...
#include <tc.h>
Data Fields | |
| __IO TC_CTRLA_Type | CTRLA |
| Offset: 0x00 (R/W 32) Control A. | |
| __IO TC_CTRLBCLR_Type | CTRLBCLR |
| Offset: 0x04 (R/W 8) Control B Clear. | |
| __IO TC_CTRLBSET_Type | CTRLBSET |
| Offset: 0x05 (R/W 8) Control B Set. | |
| __IO TC_EVCTRL_Type | EVCTRL |
| Offset: 0x06 (R/W 16) Event Control. | |
| __IO TC_INTENCLR_Type | INTENCLR |
| Offset: 0x08 (R/W 8) Interrupt Enable Clear. | |
| __IO TC_INTENSET_Type | INTENSET |
| Offset: 0x09 (R/W 8) Interrupt Enable Set. | |
| __IO TC_INTFLAG_Type | INTFLAG |
| Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear. | |
| __IO TC_STATUS_Type | STATUS |
| Offset: 0x0B (R/W 8) Status. | |
| __IO TC_WAVE_Type | WAVE |
| Offset: 0x0C (R/W 8) Waveform Generation Control. | |
| __IO TC_DRVCTRL_Type | DRVCTRL |
| Offset: 0x0D (R/W 8) Control C. | |
| RoReg8 | Reserved1 [0x1] |
| __IO TC_DBGCTRL_Type | DBGCTRL |
| Offset: 0x0F (R/W 8) Debug Control. | |
| __I TC_SYNCBUSY_Type | SYNCBUSY |
| Offset: 0x10 (R/ 32) Synchronization Status. | |
| __IO TC_COUNT32_COUNT_Type | COUNT |
| Offset: 0x14 (R/W 32) COUNT32 Count. | |
| RoReg8 | Reserved2 [0x4] |
| __IO TC_COUNT32_CC_Type | CC [2] |
| Offset: 0x1C (R/W 32) COUNT32 Compare and Capture. | |
| RoReg8 | Reserved3 [0xC] |
| __IO TC_COUNT32_CCBUF_Type | CCBUF [2] |
| Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer. | |
1.8.20