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SAME54P20A Test Project
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PDEC hardware registers. More...
#include <pdec.h>
Data Fields | |
| __IO PDEC_CTRLA_Type | CTRLA |
| Offset: 0x00 (R/W 32) Control A. | |
| __IO PDEC_CTRLBCLR_Type | CTRLBCLR |
| Offset: 0x04 (R/W 8) Control B Clear. | |
| __IO PDEC_CTRLBSET_Type | CTRLBSET |
| Offset: 0x05 (R/W 8) Control B Set. | |
| __IO PDEC_EVCTRL_Type | EVCTRL |
| Offset: 0x06 (R/W 16) Event Control. | |
| __IO PDEC_INTENCLR_Type | INTENCLR |
| Offset: 0x08 (R/W 8) Interrupt Enable Clear. | |
| __IO PDEC_INTENSET_Type | INTENSET |
| Offset: 0x09 (R/W 8) Interrupt Enable Set. | |
| __IO PDEC_INTFLAG_Type | INTFLAG |
| Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear. | |
| RoReg8 | Reserved1 [0x1] |
| __IO PDEC_STATUS_Type | STATUS |
| Offset: 0x0C (R/W 16) Status. | |
| RoReg8 | Reserved2 [0x1] |
| __IO PDEC_DBGCTRL_Type | DBGCTRL |
| Offset: 0x0F (R/W 8) Debug Control. | |
| __I PDEC_SYNCBUSY_Type | SYNCBUSY |
| Offset: 0x10 (R/ 32) Synchronization Status. | |
| __IO PDEC_PRESC_Type | PRESC |
| Offset: 0x14 (R/W 8) Prescaler Value. | |
| __IO PDEC_FILTER_Type | FILTER |
| Offset: 0x15 (R/W 8) Filter Value. | |
| RoReg8 | Reserved3 [0x2] |
| __IO PDEC_PRESCBUF_Type | PRESCBUF |
| Offset: 0x18 (R/W 8) Prescaler Buffer Value. | |
| __IO PDEC_FILTERBUF_Type | FILTERBUF |
| Offset: 0x19 (R/W 8) Filter Buffer Value. | |
| RoReg8 | Reserved4 [0x2] |
| __IO PDEC_COUNT_Type | COUNT |
| Offset: 0x1C (R/W 32) Counter Value. | |
| __IO PDEC_CC_Type | CC [2] |
| Offset: 0x20 (R/W 32) Channel n Compare Value. | |
| RoReg8 | Reserved5 [0x8] |
| __IO PDEC_CCBUF_Type | CCBUF [2] |
| Offset: 0x30 (R/W 32) Channel Compare Buffer Value. | |
1.8.20