Pcc Struct Reference

PCC hardware registers. More...

#include <pcc.h>

Data Fields
__IO PCC_MR_Type	MR
	Offset: 0x00 (R/W 32) Mode Register.
__O PCC_IER_Type	IER
	Offset: 0x04 ( /W 32) Interrupt Enable Register.
__O PCC_IDR_Type	IDR
	Offset: 0x08 ( /W 32) Interrupt Disable Register.
__I PCC_IMR_Type	IMR
	Offset: 0x0C (R/ 32) Interrupt Mask Register.
__I PCC_ISR_Type	ISR
	Offset: 0x10 (R/ 32) Interrupt Status Register.
__I PCC_RHR_Type	RHR
	Offset: 0x14 (R/ 32) Reception Holding Register.
RoReg8	Reserved1 [0xC8]
__IO PCC_WPMR_Type	WPMR
	Offset: 0xE0 (R/W 32) Write Protection Mode Register.
__I PCC_WPSR_Type	WPSR
	Offset: 0xE4 (R/ 32) Write Protection Status Register.

Detailed Description

PCC hardware registers.

Definition at line 236 of file pcc.h.

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The documentation for this struct was generated from the following file:

• /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/pcc.h