OscctrlDpll hardware registers. More...

#include <oscctrl.h>

Data Fields
__IO OSCCTRL_DPLLCTRLA_Type	DPLLCTRLA
	Offset: 0x00 (R/W 8) DPLL Control A.

RoReg8	Reserved1 [0x3]

__IO OSCCTRL_DPLLRATIO_Type	DPLLRATIO
	Offset: 0x04 (R/W 32) DPLL Ratio Control.

__IO OSCCTRL_DPLLCTRLB_Type	DPLLCTRLB
	Offset: 0x08 (R/W 32) DPLL Control B.

__I OSCCTRL_DPLLSYNCBUSY_Type	DPLLSYNCBUSY
	Offset: 0x0C (R/ 32) DPLL Synchronization Busy.

__I OSCCTRL_DPLLSTATUS_Type	DPLLSTATUS
	Offset: 0x10 (R/ 32) DPLL Status.

Detailed Description

OscctrlDpll hardware registers.

Definition at line 759 of file oscctrl.h.

The documentation for this struct was generated from the following file:

/storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/component/oscctrl.h

Data Fields