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SAME54P20A Test Project
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DMAC APB hardware registers. More...
#include <dmac.h>
Data Fields | |
| __IO DMAC_CTRL_Type | CTRL |
| Offset: 0x00 (R/W 16) Control. | |
| __IO DMAC_CRCCTRL_Type | CRCCTRL |
| Offset: 0x02 (R/W 16) CRC Control. | |
| __IO DMAC_CRCDATAIN_Type | CRCDATAIN |
| Offset: 0x04 (R/W 32) CRC Data Input. | |
| __IO DMAC_CRCCHKSUM_Type | CRCCHKSUM |
| Offset: 0x08 (R/W 32) CRC Checksum. | |
| __IO DMAC_CRCSTATUS_Type | CRCSTATUS |
| Offset: 0x0C (R/W 8) CRC Status. | |
| __IO DMAC_DBGCTRL_Type | DBGCTRL |
| Offset: 0x0D (R/W 8) Debug Control. | |
| RoReg8 | Reserved1 [0x2] |
| __IO DMAC_SWTRIGCTRL_Type | SWTRIGCTRL |
| Offset: 0x10 (R/W 32) Software Trigger Control. | |
| __IO DMAC_PRICTRL0_Type | PRICTRL0 |
| Offset: 0x14 (R/W 32) Priority Control 0. | |
| RoReg8 | Reserved2 [0x8] |
| __IO DMAC_INTPEND_Type | INTPEND |
| Offset: 0x20 (R/W 16) Interrupt Pending. | |
| RoReg8 | Reserved3 [0x2] |
| __I DMAC_INTSTATUS_Type | INTSTATUS |
| Offset: 0x24 (R/ 32) Interrupt Status. | |
| __I DMAC_BUSYCH_Type | BUSYCH |
| Offset: 0x28 (R/ 32) Busy Channels. | |
| __I DMAC_PENDCH_Type | PENDCH |
| Offset: 0x2C (R/ 32) Pending Channels. | |
| __I DMAC_ACTIVE_Type | ACTIVE |
| Offset: 0x30 (R/ 32) Active Channel and Levels. | |
| __IO DMAC_BASEADDR_Type | BASEADDR |
| Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address. | |
| __IO DMAC_WRBADDR_Type | WRBADDR |
| Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address. | |
| RoReg8 | Reserved4 [0x4] |
| DmacChannel | Channel [32] |
| Offset: 0x40 DmacChannel groups [CH_NUM]. | |
1.8.20