Component description for CMCC. More...

Data Structures
union	CMCC_TYPE_Type

union	CMCC_CFG_Type

union	CMCC_CTRL_Type

union	CMCC_SR_Type

union	CMCC_LCKWAY_Type

union	CMCC_MAINT0_Type

union	CMCC_MAINT1_Type

union	CMCC_MCFG_Type

union	CMCC_MEN_Type

union	CMCC_MCTRL_Type

union	CMCC_MSR_Type

struct	Cmcc
	CMCC APB hardware registers. More...

Macros
#define	CMCC_U2015

#define	REV_CMCC 0x600

#define	CMCC_TYPE_OFFSET 0x00
	(CMCC_TYPE offset) Cache Type Register

#define	CMCC_TYPE_RESETVALUE _U_(0x000012D2)
	(CMCC_TYPE reset_value) Cache Type Register

#define	CMCC_TYPE_GCLK_Pos 1
	(CMCC_TYPE) dynamic Clock Gating supported

#define	CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos)

#define	CMCC_TYPE_RRP_Pos 4
	(CMCC_TYPE) Round Robin Policy supported

#define	CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos)

#define	CMCC_TYPE_WAYNUM_Pos 5
	(CMCC_TYPE) Number of Way

#define	CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos)

#define	CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos))

#define	CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0)
	(CMCC_TYPE) Direct Mapped Cache

#define	CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1)
	(CMCC_TYPE) 2-WAY set associative

#define	CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2)
	(CMCC_TYPE) 4-WAY set associative

#define	CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos)

#define	CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos)

#define	CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos)

#define	CMCC_TYPE_LCKDOWN_Pos 7
	(CMCC_TYPE) Lock Down supported

#define	CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos)

#define	CMCC_TYPE_CSIZE_Pos 8
	(CMCC_TYPE) Cache Size

#define	CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos)

#define	CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos))

#define	CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0)
	(CMCC_TYPE) Cache Size is 1 KB

#define	CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1)
	(CMCC_TYPE) Cache Size is 2 KB

#define	CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2)
	(CMCC_TYPE) Cache Size is 4 KB

#define	CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3)
	(CMCC_TYPE) Cache Size is 8 KB

#define	CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4)
	(CMCC_TYPE) Cache Size is 16 KB

#define	CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5)
	(CMCC_TYPE) Cache Size is 32 KB

#define	CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6)
	(CMCC_TYPE) Cache Size is 64 KB

#define	CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos)

#define	CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos)

#define	CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos)

#define	CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos)

#define	CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos)

#define	CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos)

#define	CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos)

#define	CMCC_TYPE_CLSIZE_Pos 11
	(CMCC_TYPE) Cache Line Size

#define	CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos)

#define	CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos))

#define	CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0)
	(CMCC_TYPE) Cache Line Size is 4 bytes

#define	CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1)
	(CMCC_TYPE) Cache Line Size is 8 bytes

#define	CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2)
	(CMCC_TYPE) Cache Line Size is 16 bytes

#define	CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3)
	(CMCC_TYPE) Cache Line Size is 32 bytes

#define	CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4)
	(CMCC_TYPE) Cache Line Size is 64 bytes

#define	CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5)
	(CMCC_TYPE) Cache Line Size is 128 bytes

#define	CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos)

#define	CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos)

#define	CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos)

#define	CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos)

#define	CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos)

#define	CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos)

#define	CMCC_TYPE_MASK _U_(0x00003FF2)
	(CMCC_TYPE) MASK Register

#define	CMCC_CFG_OFFSET 0x04
	(CMCC_CFG offset) Cache Configuration Register

#define	CMCC_CFG_RESETVALUE _U_(0x00000020)
	(CMCC_CFG reset_value) Cache Configuration Register

#define	CMCC_CFG_ICDIS_Pos 1
	(CMCC_CFG) Instruction Cache Disable

#define	CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos)

#define	CMCC_CFG_DCDIS_Pos 2
	(CMCC_CFG) Data Cache Disable

#define	CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos)

#define	CMCC_CFG_CSIZESW_Pos 4
	(CMCC_CFG) Cache size configured by software

#define	CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos)

#define	CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos))

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0)
	(CMCC_CFG) the Cache Size is configured to 1KB

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1)
	(CMCC_CFG) the Cache Size is configured to 2KB

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2)
	(CMCC_CFG) the Cache Size is configured to 4KB

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3)
	(CMCC_CFG) the Cache Size is configured to 8KB

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4)
	(CMCC_CFG) the Cache Size is configured to 16KB

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5)
	(CMCC_CFG) the Cache Size is configured to 32KB

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6)
	(CMCC_CFG) the Cache Size is configured to 64KB

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos)

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos)

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos)

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos)

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos)

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos)

#define	CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos)

#define	CMCC_CFG_MASK _U_(0x00000076)
	(CMCC_CFG) MASK Register

#define	CMCC_CTRL_OFFSET 0x08
	(CMCC_CTRL offset) Cache Control Register

#define	CMCC_CTRL_RESETVALUE _U_(0x00000000)
	(CMCC_CTRL reset_value) Cache Control Register

#define	CMCC_CTRL_CEN_Pos 0
	(CMCC_CTRL) Cache Controller Enable

#define	CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos)

#define	CMCC_CTRL_MASK _U_(0x00000001)
	(CMCC_CTRL) MASK Register

#define	CMCC_SR_OFFSET 0x0C
	(CMCC_SR offset) Cache Status Register

#define	CMCC_SR_RESETVALUE _U_(0x00000000)
	(CMCC_SR reset_value) Cache Status Register

#define	CMCC_SR_CSTS_Pos 0
	(CMCC_SR) Cache Controller Status

#define	CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos)

#define	CMCC_SR_MASK _U_(0x00000001)
	(CMCC_SR) MASK Register

#define	CMCC_LCKWAY_OFFSET 0x10
	(CMCC_LCKWAY offset) Cache Lock per Way Register

#define	CMCC_LCKWAY_RESETVALUE _U_(0x00000000)
	(CMCC_LCKWAY reset_value) Cache Lock per Way Register

#define	CMCC_LCKWAY_LCKWAY_Pos 0
	(CMCC_LCKWAY) Lockdown way Register

#define	CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos)

#define	CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos))

#define	CMCC_LCKWAY_MASK _U_(0x0000000F)
	(CMCC_LCKWAY) MASK Register

#define	CMCC_MAINT0_OFFSET 0x20
	(CMCC_MAINT0 offset) Cache Maintenance Register 0

#define	CMCC_MAINT0_RESETVALUE _U_(0x00000000)
	(CMCC_MAINT0 reset_value) Cache Maintenance Register 0

#define	CMCC_MAINT0_INVALL_Pos 0
	(CMCC_MAINT0) Cache Controller invalidate All

#define	CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos)

#define	CMCC_MAINT0_MASK _U_(0x00000001)
	(CMCC_MAINT0) MASK Register

#define	CMCC_MAINT1_OFFSET 0x24
	(CMCC_MAINT1 offset) Cache Maintenance Register 1

#define	CMCC_MAINT1_RESETVALUE _U_(0x00000000)
	(CMCC_MAINT1 reset_value) Cache Maintenance Register 1

#define	CMCC_MAINT1_INDEX_Pos 4
	(CMCC_MAINT1) Invalidate Index

#define	CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos)

#define	CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos))

#define	CMCC_MAINT1_WAY_Pos 28
	(CMCC_MAINT1) Invalidate Way

#define	CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos)

#define	CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos))

#define	CMCC_MAINT1_WAY_WAY0_Val _U_(0x0)
	(CMCC_MAINT1) Way 0 is selection for index invalidation

#define	CMCC_MAINT1_WAY_WAY1_Val _U_(0x1)
	(CMCC_MAINT1) Way 1 is selection for index invalidation

#define	CMCC_MAINT1_WAY_WAY2_Val _U_(0x2)
	(CMCC_MAINT1) Way 2 is selection for index invalidation

#define	CMCC_MAINT1_WAY_WAY3_Val _U_(0x3)
	(CMCC_MAINT1) Way 3 is selection for index invalidation

#define	CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos)

#define	CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos)

#define	CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos)

#define	CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos)

#define	CMCC_MAINT1_MASK _U_(0xF0000FF0)
	(CMCC_MAINT1) MASK Register

#define	CMCC_MCFG_OFFSET 0x28
	(CMCC_MCFG offset) Cache Monitor Configuration Register

#define	CMCC_MCFG_RESETVALUE _U_(0x00000000)
	(CMCC_MCFG reset_value) Cache Monitor Configuration Register

#define	CMCC_MCFG_MODE_Pos 0
	(CMCC_MCFG) Cache Controller Monitor Counter Mode

#define	CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos)

#define	CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos))

#define	CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0)
	(CMCC_MCFG) cycle counter

#define	CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1)
	(CMCC_MCFG) instruction hit counter

#define	CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2)
	(CMCC_MCFG) data hit counter

#define	CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos)

#define	CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)

#define	CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos)

#define	CMCC_MCFG_MASK _U_(0x00000003)
	(CMCC_MCFG) MASK Register

#define	CMCC_MEN_OFFSET 0x2C
	(CMCC_MEN offset) Cache Monitor Enable Register

#define	CMCC_MEN_RESETVALUE _U_(0x00000000)
	(CMCC_MEN reset_value) Cache Monitor Enable Register

#define	CMCC_MEN_MENABLE_Pos 0
	(CMCC_MEN) Cache Controller Monitor Enable

#define	CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos)

#define	CMCC_MEN_MASK _U_(0x00000001)
	(CMCC_MEN) MASK Register

#define	CMCC_MCTRL_OFFSET 0x30
	(CMCC_MCTRL offset) Cache Monitor Control Register

#define	CMCC_MCTRL_RESETVALUE _U_(0x00000000)
	(CMCC_MCTRL reset_value) Cache Monitor Control Register

#define	CMCC_MCTRL_SWRST_Pos 0
	(CMCC_MCTRL) Cache Controller Software Reset

#define	CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos)

#define	CMCC_MCTRL_MASK _U_(0x00000001)
	(CMCC_MCTRL) MASK Register

#define	CMCC_MSR_OFFSET 0x34
	(CMCC_MSR offset) Cache Monitor Status Register

#define	CMCC_MSR_RESETVALUE _U_(0x00000000)
	(CMCC_MSR reset_value) Cache Monitor Status Register

#define	CMCC_MSR_EVENT_CNT_Pos 0
	(CMCC_MSR) Monitor Event Counter

#define	CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos)

#define	CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos))

#define	CMCC_MSR_MASK _U_(0xFFFFFFFF)
	(CMCC_MSR) MASK Register

Detailed Description

Component description for CMCC.

\asf_license_start

Definition in file cmcc.h.

Data Structures

Macros

Detailed Description